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//////////////////////////////////////////////////////////////////////
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//// ////
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//// adbg_jsp_module.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "adbg_defines.v"
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// Module interface
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module adbg_jsp_module (
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// JTAG signals
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tck_i,
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module_tdo_o,
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tdi_i,
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// TAP states
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capture_dr_i,
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shift_dr_i,
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update_dr_i,
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data_register_i, // the data register is at top level, shared between all modules
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module_select_i,
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top_inhibit_o,
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rst_i,
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// WISHBONE common signals
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wb_clk_i, wb_rst_i,
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// WISHBONE slave interface
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wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
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wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o
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);
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// JTAG signals
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input tck_i;
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output module_tdo_o;
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input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
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// TAP states
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input capture_dr_i;
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input shift_dr_i;
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input update_dr_i;
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input [52:0] data_register_i;
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input module_select_i;
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output top_inhibit_o;
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input rst_i;
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// WISHBONE slave interface
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input wb_clk_i;
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input wb_rst_i;
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input [31:0] wb_adr_i;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input wb_cyc_i;
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input wb_stb_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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output wb_ack_o;
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input wb_cab_i;
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output wb_err_o;
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input [2:0] wb_cti_i;
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input [1:0] wb_bte_i;
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output int_o;
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// Declare inputs / outputs as wires / registers
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wire module_tdo_o;
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wire top_inhibit_o;
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// NOTE: For the rest of this file, "input" and the "in" direction refer to bytes being transferred
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// from the PC, through the JTAG, and into the BIU FIFO. The "output" direction refers to data being
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// transferred from the BIU FIFO, through the JTAG to the PC.
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// The read and write bit counts are separated to allow for JTAG chains with multiple devices.
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// The read bit count starts right away (after a single throwaway bit), but the write count
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// waits to receive a '1' start bit.
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// Registers to hold state etc.
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reg [3:0] read_bit_count; // How many bits have been shifted out
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reg [3:0] write_bit_count; // How many bits have been shifted in
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reg [3:0] input_word_count; // space (bytes) remaining in input FIFO (from JTAG)
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reg [3:0] output_word_count; // bytes remaining in output FIFO (to JTAG)
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reg [3:0] user_word_count; // bytes user intends to send from PC
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reg [7:0] data_out_shift_reg; // parallel-load output shift register
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// Control signals for the various counters / registers / state machines
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reg rd_bit_ct_en; // enable bit counter
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reg rd_bit_ct_rst; // reset (zero) bit count register
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reg wr_bit_ct_en; // enable bit counter
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reg wr_bit_ct_rst; // reset (zero) bit count register
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reg in_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
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reg out_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
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reg in_word_ct_en; // Enable input byte counter register
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reg out_word_ct_en; // Enable output byte count register
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reg user_word_ct_en; // Enable user byte count registere
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reg user_word_ct_sel; // selects data for user byte counter. 0 = user data, 1 = decremented byte count
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reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg
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reg out_reg_shift_en; // Enable shift of data_out_shift_reg
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reg out_reg_data_sel; // 0 = BIU data, 1 = byte count data (also from BIU)
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reg biu_rd_strobe; // Indicates that the bus unit should ACK the last read operation + start another
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reg biu_wr_strobe; // Indicates BIU should latch input + begin a write operation
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// Status signals
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wire in_word_count_zero; // true when input byte counter is zero
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wire out_word_count_zero; // true when output byte counter is zero
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wire user_word_count_zero; // true when user byte counter is zero
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wire rd_bit_count_max; // true when bit counter is equal to current word size
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wire wr_bit_count_max; // true when bit counter is equal to current word size
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// Intermediate signals
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wire [3:0] data_to_in_word_counter; // output of the mux in front of the input byte counter reg
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wire [3:0] data_to_out_word_counter; // output of the mux in front of the output byte counter reg
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wire [3:0] data_to_user_word_counter; // output of mux in front of user word counter
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wire [3:0] decremented_in_word_count;
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wire [3:0] decremented_out_word_count;
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wire [3:0] decremented_user_word_count;
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wire [3:0] count_data_in; // from data_register_i
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wire [7:0] data_to_biu; // from data_register_i
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wire [7:0] data_from_biu; // to data_out_shift_register
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wire [3:0] biu_space_available;
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wire [3:0] biu_bytes_available;
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wire [7:0] count_data_from_biu; // combined space avail / bytes avail
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wire [7:0] out_reg_data; // parallel input to the output shift register
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/////////////////////////////////////////////////
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// Combinatorial assignments
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assign count_data_from_biu = {biu_bytes_available, biu_space_available};
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assign count_data_in = {tdi_i, data_register_i[52:50]}; // Second nibble of user data
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assign data_to_biu = {tdi_i,data_register_i[52:46]};
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assign top_inhibit_o = 1'b0;
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//////////////////////////////////////
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// Input bit counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) write_bit_count <= 4'h0;
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else if(wr_bit_ct_rst) write_bit_count <= 4'h0;
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else if(wr_bit_ct_en) write_bit_count <= write_bit_count + 4'h1;
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end
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assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;
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//////////////////////////////////////
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// Output bit counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) read_bit_count <= 4'h0;
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else if(rd_bit_ct_rst) read_bit_count <= 4'h0;
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else if(rd_bit_ct_en) read_bit_count <= read_bit_count + 4'h1;
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end
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assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;
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////////////////////////////////////////
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// Input word counter
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assign data_to_in_word_counter = (in_word_ct_sel) ? decremented_in_word_count : biu_space_available;
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assign decremented_in_word_count = input_word_count - 4'h1;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i)
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input_word_count <= 4'h0;
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else if(in_word_ct_en)
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input_word_count <= data_to_in_word_counter;
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end
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assign in_word_count_zero = (input_word_count == 4'h0);
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////////////////////////////////////////
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// Output word counter
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assign data_to_out_word_counter = (out_word_ct_sel) ? decremented_out_word_count : biu_bytes_available;
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assign decremented_out_word_count = output_word_count - 4'h1;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i)
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output_word_count <= 4'h0;
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else if(out_word_ct_en)
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output_word_count <= data_to_out_word_counter;
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end
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assign out_word_count_zero = (output_word_count == 4'h0);
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////////////////////////////////////////
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// User word counter
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assign data_to_user_word_counter = (user_word_ct_sel) ? decremented_user_word_count : count_data_in;
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assign decremented_user_word_count = user_word_count - 4'h1;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) user_word_count <= 4'h0;
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else if(user_word_ct_en) user_word_count <= data_to_user_word_counter;
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end
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assign user_word_count_zero = (user_word_count == 4'h0);
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/////////////////////////////////////////////////////
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// Output register and TDO output MUX
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assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) data_out_shift_reg <= 8'h0;
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else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
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else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
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end
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assign module_tdo_o = data_out_shift_reg[0];
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////////////////////////////////////////
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// Bus Interface Unit (to JTAG / WB UART)
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// It is assumed that the BIU has internal registers, and will
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// latch write data (and ack read data) on rising clock edge
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// when strobe is asserted
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adbg_jsp_biu jsp_biu_i (
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// Debug interface signals
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.tck_i (tck_i),
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.rst_i (rst_i),
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.data_i (data_to_biu),
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.data_o (data_from_biu),
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.bytes_available_o (biu_bytes_available),
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.bytes_free_o (biu_space_available),
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.rd_strobe_i (biu_rd_strobe),
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.wr_strobe_i (biu_wr_strobe),
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// Wishbone slave signals
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.wb_adr_i (wb_adr_i),
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.wb_dat_o (wb_dat_o),
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.wb_dat_i (wb_dat_i),
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.wb_cyc_i (wb_cyc_i),
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.wb_stb_i (wb_stb_i),
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.wb_sel_i (wb_sel_i),
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.wb_we_i (wb_we_i),
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.wb_ack_o (wb_ack_o),
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.wb_cab_i (wb_cab_i),
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.wb_err_o (wb_err_o),
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.wb_cti_i (wb_cti_i),
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.wb_bte_i (wb_bte_i),
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.int_o (int_o)
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);
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////////////////////////////////////////
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// Input Control FSM
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// Definition of machine state values.
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// Don't worry too much about the state encoding, the synthesis tool
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// will probably re-encode it anyway.
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`define STATE_wr_idle 3'h0
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`define STATE_wr_wait 3'h1
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`define STATE_wr_counts 3'h2
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`define STATE_wr_xfer 3'h3
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reg [2:0] wr_module_state; // FSM state
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reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register
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// sequential part of the FSM
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i)
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wr_module_state <= `STATE_wr_idle;
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else
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wr_module_state <= wr_module_next_state;
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end
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// Determination of next state; purely combinatorial
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317 |
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always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i
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or shift_dr_i or wr_bit_count_max or tdi_i)
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begin
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320 |
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case(wr_module_state)
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`STATE_wr_idle:
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begin
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`ifdef ADBG_JSP_SUPPORT_MULTI
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if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
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`else
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326 |
|
|
if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
|
327 |
|
|
`endif
|
328 |
|
|
else wr_module_next_state <= `STATE_wr_idle;
|
329 |
|
|
end
|
330 |
|
|
`STATE_wr_wait:
|
331 |
|
|
begin
|
332 |
|
|
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
|
333 |
|
|
else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts; // got start bit
|
334 |
|
|
else wr_module_next_state <= `STATE_wr_wait;
|
335 |
|
|
end
|
336 |
|
|
`STATE_wr_counts:
|
337 |
|
|
begin
|
338 |
|
|
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
|
339 |
|
|
else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
|
340 |
|
|
else wr_module_next_state <= `STATE_wr_counts;
|
341 |
|
|
end
|
342 |
|
|
|
343 |
|
|
`STATE_wr_xfer:
|
344 |
|
|
begin
|
345 |
|
|
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
|
346 |
|
|
else wr_module_next_state <= `STATE_wr_xfer;
|
347 |
|
|
end
|
348 |
|
|
|
349 |
|
|
default: wr_module_next_state <= `STATE_wr_idle; // shouldn't actually happen...
|
350 |
|
|
endcase
|
351 |
|
|
end
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
// Outputs of state machine, pure combinatorial
|
355 |
|
|
always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
|
356 |
|
|
or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
|
357 |
51 |
nyawn |
or decremented_out_word_count or user_word_count_zero)
|
358 |
42 |
nyawn |
begin
|
359 |
|
|
// Default everything to 0, keeps the case statement simple
|
360 |
|
|
wr_bit_ct_en <= 1'b0; // enable bit counter
|
361 |
|
|
wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register
|
362 |
|
|
in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
|
363 |
|
|
user_word_ct_sel <= 1'b0; // selects data for user byte counter, 0 = user data, 1 = decremented count
|
364 |
|
|
in_word_ct_en <= 1'b0; // Enable input byte counter register
|
365 |
|
|
user_word_ct_en <= 1'b0; // enable user byte count register
|
366 |
|
|
biu_wr_strobe <= 1'b0; // Indicates BIU should latch input + begin a write operation
|
367 |
|
|
|
368 |
|
|
case(wr_module_state)
|
369 |
|
|
`STATE_wr_idle:
|
370 |
|
|
begin
|
371 |
|
|
in_word_ct_sel <= 1'b0;
|
372 |
|
|
|
373 |
|
|
// Going to transfer; enable count registers and output register
|
374 |
|
|
if(wr_module_next_state != `STATE_wr_idle) begin
|
375 |
|
|
wr_bit_ct_rst <= 1'b1;
|
376 |
|
|
in_word_ct_en <= 1'b1;
|
377 |
|
|
end
|
378 |
|
|
end
|
379 |
|
|
|
380 |
|
|
// This state is only used when support for multi-device JTAG chains is enabled.
|
381 |
|
|
`STATE_wr_wait:
|
382 |
|
|
begin
|
383 |
|
|
wr_bit_ct_en <= 1'b0; // Don't do anything, just wait for the start bit.
|
384 |
|
|
end
|
385 |
|
|
|
386 |
|
|
`STATE_wr_counts:
|
387 |
|
|
begin
|
388 |
|
|
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
|
389 |
|
|
wr_bit_ct_en <= 1'b1;
|
390 |
|
|
user_word_ct_sel <= 1'b0;
|
391 |
|
|
|
392 |
|
|
if(wr_bit_count_max) begin
|
393 |
|
|
wr_bit_ct_rst <= 1'b1;
|
394 |
|
|
user_word_ct_en <= 1'b1;
|
395 |
|
|
end
|
396 |
|
|
end
|
397 |
|
|
end
|
398 |
|
|
|
399 |
|
|
`STATE_wr_xfer:
|
400 |
|
|
begin
|
401 |
|
|
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
|
402 |
|
|
wr_bit_ct_en <= 1'b1;
|
403 |
|
|
in_word_ct_sel <= 1'b1;
|
404 |
|
|
user_word_ct_sel <= 1'b1;
|
405 |
|
|
|
406 |
|
|
if(wr_bit_count_max) begin // Start biu transactions, if word counts allow
|
407 |
|
|
wr_bit_ct_rst <= 1'b1;
|
408 |
|
|
|
409 |
|
|
if(!(in_word_count_zero || user_word_count_zero)) begin
|
410 |
|
|
biu_wr_strobe <= 1'b1;
|
411 |
|
|
in_word_ct_en <= 1'b1;
|
412 |
|
|
user_word_ct_en <= 1'b1;
|
413 |
|
|
end
|
414 |
|
|
|
415 |
|
|
end
|
416 |
|
|
end
|
417 |
|
|
end
|
418 |
|
|
|
419 |
|
|
default: ;
|
420 |
|
|
endcase
|
421 |
|
|
end
|
422 |
|
|
|
423 |
|
|
////////////////////////////////////////
|
424 |
|
|
// Output Control FSM
|
425 |
|
|
|
426 |
|
|
// Definition of machine state values.
|
427 |
|
|
// Don't worry too much about the state encoding, the synthesis tool
|
428 |
|
|
// will probably re-encode it anyway.
|
429 |
|
|
|
430 |
|
|
`define STATE_rd_idle 4'h0
|
431 |
|
|
`define STATE_rd_counts 4'h1
|
432 |
|
|
`define STATE_rd_rdack 4'h2
|
433 |
|
|
`define STATE_rd_xfer 4'h3
|
434 |
|
|
|
435 |
|
|
// We do not send the equivalent of a 'start bit' (like the one the input FSM
|
436 |
|
|
// waits for when support for multi-device JTAG chains is enabled). Since the
|
437 |
|
|
// input and output are going to be offset anyway, why bother...
|
438 |
|
|
|
439 |
|
|
reg [2:0] rd_module_state; // FSM state
|
440 |
|
|
reg [2:0] rd_module_next_state; // combinatorial signal, not actually a register
|
441 |
|
|
|
442 |
|
|
|
443 |
|
|
// sequential part of the FSM
|
444 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
445 |
|
|
begin
|
446 |
|
|
if(rst_i)
|
447 |
|
|
rd_module_state <= `STATE_rd_idle;
|
448 |
|
|
else
|
449 |
|
|
rd_module_state <= rd_module_next_state;
|
450 |
|
|
end
|
451 |
|
|
|
452 |
|
|
|
453 |
|
|
// Determination of next state; purely combinatorial
|
454 |
|
|
always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
|
455 |
|
|
begin
|
456 |
|
|
case(rd_module_state)
|
457 |
|
|
`STATE_rd_idle:
|
458 |
|
|
begin
|
459 |
|
|
if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
|
460 |
|
|
else rd_module_next_state <= `STATE_rd_idle;
|
461 |
|
|
end
|
462 |
|
|
`STATE_rd_counts:
|
463 |
|
|
begin
|
464 |
|
|
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
|
465 |
|
|
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
|
466 |
|
|
else rd_module_next_state <= `STATE_rd_counts;
|
467 |
|
|
end
|
468 |
|
|
`STATE_rd_rdack:
|
469 |
|
|
begin
|
470 |
|
|
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
|
471 |
|
|
else rd_module_next_state <= `STATE_rd_xfer;
|
472 |
|
|
end
|
473 |
|
|
`STATE_rd_xfer:
|
474 |
|
|
begin
|
475 |
|
|
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
|
476 |
|
|
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
|
477 |
|
|
else rd_module_next_state <= `STATE_rd_xfer;
|
478 |
|
|
end
|
479 |
|
|
|
480 |
|
|
default: rd_module_next_state <= `STATE_rd_idle; // shouldn't actually happen...
|
481 |
|
|
endcase
|
482 |
|
|
end
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
// Outputs of state machine, pure combinatorial
|
486 |
|
|
always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
|
487 |
|
|
or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
|
488 |
|
|
or decremented_out_word_count)
|
489 |
|
|
begin
|
490 |
|
|
// Default everything to 0, keeps the case statement simple
|
491 |
|
|
rd_bit_ct_en <= 1'b0; // enable bit counter
|
492 |
|
|
rd_bit_ct_rst <= 1'b0; // reset (zero) bit count register
|
493 |
|
|
out_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
|
494 |
|
|
out_word_ct_en <= 1'b0; // Enable output byte count register
|
495 |
|
|
out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg
|
496 |
|
|
out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg
|
497 |
|
|
out_reg_data_sel <= 1'b0; // 0 = BIU data, 1 = byte count data (also from BIU)
|
498 |
|
|
biu_rd_strobe <= 1'b0; // Indicates that the bus unit should ACK the last read operation + start another
|
499 |
|
|
|
500 |
|
|
case(rd_module_state)
|
501 |
|
|
`STATE_rd_idle:
|
502 |
|
|
begin
|
503 |
|
|
out_reg_data_sel <= 1'b1;
|
504 |
|
|
out_word_ct_sel <= 1'b0;
|
505 |
|
|
|
506 |
|
|
// Going to transfer; enable count registers and output register
|
507 |
|
|
if(rd_module_next_state != `STATE_rd_idle) begin
|
508 |
|
|
out_reg_ld_en <= 1'b1;
|
509 |
|
|
rd_bit_ct_rst <= 1'b1;
|
510 |
|
|
out_word_ct_en <= 1'b1;
|
511 |
|
|
end
|
512 |
|
|
end
|
513 |
|
|
|
514 |
|
|
`STATE_rd_counts:
|
515 |
|
|
begin
|
516 |
|
|
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
|
517 |
|
|
rd_bit_ct_en <= 1'b1;
|
518 |
|
|
out_reg_shift_en <= 1'b1;
|
519 |
|
|
|
520 |
|
|
if(rd_bit_count_max) begin
|
521 |
|
|
rd_bit_ct_rst <= 1'b1;
|
522 |
|
|
|
523 |
|
|
// Latch the next output word, but don't ack until STATE_rd_rdack
|
524 |
|
|
if(!out_word_count_zero) begin
|
525 |
|
|
out_reg_ld_en <= 1'b1;
|
526 |
|
|
out_reg_shift_en <= 1'b0;
|
527 |
|
|
end
|
528 |
|
|
end
|
529 |
|
|
end
|
530 |
|
|
end
|
531 |
|
|
|
532 |
|
|
`STATE_rd_rdack:
|
533 |
|
|
begin
|
534 |
|
|
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
|
535 |
|
|
rd_bit_ct_en <= 1'b1;
|
536 |
|
|
out_reg_shift_en <= 1'b1;
|
537 |
|
|
out_reg_data_sel <= 1'b0;
|
538 |
|
|
|
539 |
|
|
// Never have to worry about bit_count_max here.
|
540 |
|
|
|
541 |
|
|
if(!out_word_count_zero) begin
|
542 |
|
|
biu_rd_strobe <= 1'b1;
|
543 |
|
|
end
|
544 |
|
|
end
|
545 |
|
|
end
|
546 |
|
|
|
547 |
|
|
`STATE_rd_xfer:
|
548 |
|
|
begin
|
549 |
|
|
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
|
550 |
|
|
rd_bit_ct_en <= 1'b1;
|
551 |
|
|
out_word_ct_sel <= 1'b1;
|
552 |
|
|
out_reg_shift_en <= 1'b1;
|
553 |
|
|
out_reg_data_sel <= 1'b0;
|
554 |
|
|
|
555 |
|
|
if(rd_bit_count_max) begin // Start biu transaction, if word count allows
|
556 |
|
|
rd_bit_ct_rst <= 1'b1;
|
557 |
|
|
|
558 |
|
|
// Don't ack the read byte here, we do it in STATE_rdack
|
559 |
|
|
if(!out_word_count_zero) begin
|
560 |
|
|
out_reg_ld_en <= 1'b1;
|
561 |
|
|
out_reg_shift_en <= 1'b0;
|
562 |
|
|
out_word_ct_en <= 1'b1;
|
563 |
|
|
end
|
564 |
|
|
end
|
565 |
|
|
end
|
566 |
|
|
end
|
567 |
|
|
|
568 |
|
|
default: ;
|
569 |
|
|
endcase
|
570 |
|
|
end
|
571 |
|
|
|
572 |
|
|
|
573 |
|
|
endmodule
|
574 |
|
|
|