1 |
3 |
nyawn |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// adbg_or1k_module.v ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// This file is part of the SoC Advanced Debug Interface. ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// Author(s): ////
|
9 |
|
|
//// Nathan Yawn (nathan.yawn@opencores.org) ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// ////
|
12 |
|
|
//// ////
|
13 |
|
|
//////////////////////////////////////////////////////////////////////
|
14 |
|
|
//// ////
|
15 |
32 |
nyawn |
//// Copyright (C) 2008 - 2010 Authors ////
|
16 |
3 |
nyawn |
//// ////
|
17 |
|
|
//// This source file may be used and distributed without ////
|
18 |
|
|
//// restriction provided that this copyright statement is not ////
|
19 |
|
|
//// removed from the file and that any derivative work contains ////
|
20 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
21 |
|
|
//// ////
|
22 |
|
|
//// This source file is free software; you can redistribute it ////
|
23 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
24 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
25 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
26 |
|
|
//// later version. ////
|
27 |
|
|
//// ////
|
28 |
|
|
//// This source is distributed in the hope that it will be ////
|
29 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
30 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
31 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
32 |
|
|
//// details. ////
|
33 |
|
|
//// ////
|
34 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
35 |
|
|
//// Public License along with this source; if not, download it ////
|
36 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
37 |
|
|
//// ////
|
38 |
|
|
//////////////////////////////////////////////////////////////////////
|
39 |
|
|
//
|
40 |
|
|
// CVS Revision History
|
41 |
|
|
//
|
42 |
|
|
// $Log: adbg_or1k_module.v,v $
|
43 |
42 |
nyawn |
// Revision 1.6 2010-03-08 21:04:18 Nathan
|
44 |
|
|
// Changes for the JTAG serial port module. Uncompiled, untestede. Removed CVS logs, minor fixes in comments.
|
45 |
|
|
//
|
46 |
32 |
nyawn |
// Revision 1.5 2010-01-13 00:55:45 Nathan
|
47 |
|
|
// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
|
48 |
|
|
//
|
49 |
3 |
nyawn |
// Revision 1.2 2009/05/17 20:54:56 Nathan
|
50 |
|
|
// Changed email address to opencores.org
|
51 |
|
|
//
|
52 |
|
|
// Revision 1.1 2008/07/22 20:28:31 Nathan
|
53 |
|
|
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
|
54 |
|
|
//
|
55 |
|
|
// Revision 1.7 2008/07/11 08:13:29 Nathan
|
56 |
|
|
// Latch opcode on posedge, like other signals. This fixes a problem
|
57 |
|
|
// when the module is used with a Xilinx BSCAN TAP. Added signals to
|
58 |
|
|
// allow modules to inhibit latching of a new active module by the top
|
59 |
|
|
// module. This allows the sub-modules to force the top level module
|
60 |
|
|
// to ignore the command present in the input shift register after e.g.
|
61 |
|
|
// a burst read.
|
62 |
|
|
//
|
63 |
|
|
|
64 |
|
|
|
65 |
32 |
nyawn |
`include "adbg_defines.v"
|
66 |
3 |
nyawn |
`include "adbg_or1k_defines.v"
|
67 |
|
|
|
68 |
|
|
// Module interface
|
69 |
|
|
module adbg_or1k_module (
|
70 |
|
|
// JTAG signals
|
71 |
|
|
tck_i,
|
72 |
|
|
module_tdo_o,
|
73 |
|
|
tdi_i,
|
74 |
|
|
|
75 |
|
|
// TAP states
|
76 |
|
|
capture_dr_i,
|
77 |
|
|
shift_dr_i,
|
78 |
|
|
update_dr_i,
|
79 |
|
|
|
80 |
|
|
data_register_i, // the data register is at top level, shared between all modules
|
81 |
|
|
module_select_i,
|
82 |
|
|
top_inhibit_o,
|
83 |
|
|
rst_i,
|
84 |
|
|
|
85 |
|
|
// Interfate to the OR1K debug unit
|
86 |
|
|
cpu_clk_i,
|
87 |
|
|
cpu_addr_o,
|
88 |
|
|
cpu_data_i,
|
89 |
|
|
cpu_data_o,
|
90 |
|
|
cpu_bp_i,
|
91 |
|
|
cpu_stall_o,
|
92 |
|
|
cpu_stb_o,
|
93 |
|
|
cpu_we_o,
|
94 |
|
|
cpu_ack_i,
|
95 |
|
|
cpu_rst_o
|
96 |
|
|
);
|
97 |
|
|
|
98 |
|
|
// JTAG signals
|
99 |
|
|
input tck_i;
|
100 |
|
|
output module_tdo_o;
|
101 |
|
|
input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
|
102 |
|
|
|
103 |
|
|
// TAP states
|
104 |
|
|
input capture_dr_i;
|
105 |
|
|
input shift_dr_i;
|
106 |
|
|
input update_dr_i;
|
107 |
|
|
|
108 |
|
|
input [52:0] data_register_i;
|
109 |
|
|
input module_select_i;
|
110 |
|
|
output top_inhibit_o;
|
111 |
|
|
input rst_i;
|
112 |
|
|
|
113 |
42 |
nyawn |
// Interface to OR1200 debug unit
|
114 |
3 |
nyawn |
input cpu_clk_i; // 'bus' style interface to SPRs
|
115 |
|
|
output [31:0] cpu_addr_o;
|
116 |
|
|
input [31:0] cpu_data_i;
|
117 |
|
|
output [31:0] cpu_data_o;
|
118 |
|
|
output cpu_stb_o;
|
119 |
|
|
output cpu_we_o;
|
120 |
|
|
input cpu_ack_i;
|
121 |
|
|
output cpu_rst_o; // control lines
|
122 |
|
|
input cpu_bp_i;
|
123 |
|
|
output cpu_stall_o;
|
124 |
|
|
|
125 |
|
|
// Declare inputs / outputs as wires / registers
|
126 |
|
|
reg module_tdo_o;
|
127 |
|
|
reg top_inhibit_o;
|
128 |
|
|
|
129 |
|
|
|
130 |
|
|
// Registers to hold state etc.
|
131 |
|
|
reg [31:0] address_counter; // Holds address for next Wishbone access
|
132 |
|
|
reg [5:0] bit_count; // How many bits have been shifted in/out
|
133 |
|
|
reg [15:0] word_count; // bytes remaining in current burst command
|
134 |
|
|
reg [3:0] operation; // holds the current command (rd/wr, word size)
|
135 |
|
|
reg [31:0] data_out_shift_reg; // parallel-load output shift register
|
136 |
|
|
reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select; // Holds index of currently selected register
|
137 |
|
|
wire [1:0] internal_reg_status; // Holds CPU stall and reset status - signal is output of separate module
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
// Control signals for the various counters / registers / state machines
|
141 |
|
|
reg addr_sel; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count
|
142 |
|
|
reg addr_ct_en; // Enable signal for address counter register
|
143 |
|
|
reg op_reg_en; // Enable signal for 'operation' register
|
144 |
|
|
reg bit_ct_en; // enable bit counter
|
145 |
|
|
reg bit_ct_rst; // reset (zero) bit count register
|
146 |
|
|
reg word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
|
147 |
|
|
reg word_ct_en; // Enable byte counter register
|
148 |
|
|
reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg
|
149 |
|
|
reg out_reg_shift_en; // Enable shift of data_out_shift_reg
|
150 |
|
|
reg out_reg_data_sel; // 0 = BIU data, 1 = internal register data
|
151 |
|
|
reg [1:0] tdo_output_sel; // Selects signal to send to TDO. 0 = ready bit, 1 = output register, 2 = CRC match, 3 = CRC shift reg.
|
152 |
|
|
reg biu_strobe; // Indicates that the bus unit should latch data and start a transaction
|
153 |
|
|
reg crc_clr; // resets CRC module
|
154 |
|
|
reg crc_en; // does 1-bit iteration in CRC module
|
155 |
|
|
reg crc_in_sel; // selects incoming write data (=0) or outgoing read data (=1)as input to CRC module
|
156 |
|
|
reg crc_shift_en; // CRC reg is also it's own output shift register; this enables a shift
|
157 |
|
|
reg regsel_ld_en; // Reg. select register load enable
|
158 |
|
|
reg intreg_ld_en; // load enable for internal registers
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
// Status signals
|
162 |
|
|
wire word_count_zero; // true when byte counter is zero
|
163 |
|
|
wire bit_count_max; // true when bit counter is equal to current word size
|
164 |
|
|
wire module_cmd; // inverse of MSB of data_register_i. 1 means current cmd not for top level (but is for us)
|
165 |
|
|
wire biu_ready; // indicates that the BIU has finished the last command
|
166 |
|
|
wire burst_instruction; // True when the input_data_i reg has a valid burst instruction for this module
|
167 |
|
|
wire intreg_instruction; // True when the input_data_i reg has a valid internal register instruction
|
168 |
|
|
wire intreg_write; // True when the input_data_i reg has an internal register write op
|
169 |
|
|
wire rd_op; // True when operation in the opcode reg is a read, false when a write
|
170 |
|
|
wire crc_match; // indicates whether data_register_i matches computed CRC
|
171 |
|
|
wire bit_count_32; // true when bit count register == 32, for CRC after burst writes
|
172 |
|
|
|
173 |
|
|
// Intermediate signals
|
174 |
|
|
wire [5:0] word_size_bits; // 8,16, or 32. Decoded from 'operation'
|
175 |
|
|
wire [2:0] address_increment; // How much to add to the address counter each iteration
|
176 |
|
|
wire [32:0] incremented_address; // value of address counter plus 'word_size'
|
177 |
|
|
wire [31:0] data_to_addr_counter; // output of the mux in front of the address counter inputs
|
178 |
|
|
wire [15:0] data_to_word_counter; // output of the mux in front of the byte counter input
|
179 |
|
|
wire [15:0] decremented_word_count;
|
180 |
|
|
wire [31:0] address_data_in; // from data_register_i
|
181 |
|
|
wire [15:0] count_data_in; // from data_register_i
|
182 |
|
|
wire [3:0] operation_in; // from data_register_i
|
183 |
|
|
wire [31:0] data_to_biu; // from data_register_i
|
184 |
|
|
wire [31:0] data_from_biu; // to data_out_shift_register
|
185 |
|
|
wire [31:0] crc_data_out; // output of CRC module, to output shift register
|
186 |
|
|
wire crc_data_in; // input to CRC module, either data_register_i[52] or data_out_shift_reg[0]
|
187 |
|
|
wire crc_serial_out;
|
188 |
|
|
wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data; // from data_register_i, input to internal register select register
|
189 |
|
|
wire [31:0] out_reg_data; // parallel input to the output shift register
|
190 |
|
|
reg [31:0] data_from_internal_reg; // data from internal reg. MUX to output shift register
|
191 |
|
|
wire status_reg_wr;
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
/////////////////////////////////////////////////
|
195 |
|
|
// Combinatorial assignments
|
196 |
|
|
|
197 |
|
|
assign module_cmd = ~(data_register_i[52]);
|
198 |
|
|
assign operation_in = data_register_i[51:48];
|
199 |
|
|
assign address_data_in = data_register_i[47:16];
|
200 |
|
|
assign count_data_in = data_register_i[15:0];
|
201 |
32 |
nyawn |
`ifdef ADBG_USE_HISPEED
|
202 |
|
|
assign data_to_biu = {tdi_i,data_register_i[52:22]};
|
203 |
|
|
`else
|
204 |
3 |
nyawn |
assign data_to_biu = data_register_i[52:21];
|
205 |
32 |
nyawn |
`endif
|
206 |
3 |
nyawn |
assign reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];
|
207 |
|
|
|
208 |
|
|
////////////////////////////////////////////////
|
209 |
|
|
// Operation decoder
|
210 |
|
|
|
211 |
|
|
// These are only used before the operation is latched, so decode them from operation_in
|
212 |
|
|
assign burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);
|
213 |
|
|
assign intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));
|
214 |
|
|
assign intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);
|
215 |
|
|
|
216 |
|
|
// These are constant, the CPU module only does 32-bit accesses
|
217 |
|
|
assign word_size_bits = 5'd31; // Bits is actually bits-1, to make the FSM easier
|
218 |
|
|
assign address_increment = 3'd1; // This is only used to increment the address. SPRs are word-addressed.
|
219 |
|
|
|
220 |
|
|
// This is the only thing that actually needs to be saved and 'decoded' from the latched opcode
|
221 |
|
|
// It goes to the BIU each time a transaction is started.
|
222 |
|
|
assign rd_op = operation[2];
|
223 |
|
|
|
224 |
|
|
|
225 |
|
|
////////////////////////////////////////////////
|
226 |
|
|
// Module-internal register select register (no, that's not redundant.)
|
227 |
|
|
// Also internal register output MUX
|
228 |
|
|
|
229 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
230 |
|
|
begin
|
231 |
|
|
if(rst_i) internal_register_select = 1'h0;
|
232 |
|
|
else if(regsel_ld_en) internal_register_select = reg_select_data;
|
233 |
|
|
end
|
234 |
|
|
|
235 |
|
|
// This is completely unnecessary here, since the module has only 1 internal
|
236 |
|
|
// register. However, to make the module expandable, it is included anyway.
|
237 |
|
|
always @ (internal_register_select or internal_reg_status)
|
238 |
|
|
begin
|
239 |
|
|
case(internal_register_select)
|
240 |
|
|
`DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30'h0, internal_reg_status};
|
241 |
|
|
default: data_from_internal_reg = {30'h0, internal_reg_status};
|
242 |
|
|
endcase
|
243 |
|
|
end
|
244 |
|
|
|
245 |
|
|
|
246 |
|
|
|
247 |
|
|
////////////////////////////////////////////////////////////////////
|
248 |
|
|
// Module-internal registers
|
249 |
|
|
// These have generic read/write/select code, but
|
250 |
|
|
// individual registers may have special behavior, defined here.
|
251 |
|
|
|
252 |
|
|
// This is the status register, which holds the reset and stall states.
|
253 |
|
|
|
254 |
|
|
assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS));
|
255 |
|
|
|
256 |
|
|
adbg_or1k_status_reg or1k_statusreg_i (
|
257 |
|
|
.data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]),
|
258 |
|
|
.we_i(status_reg_wr),
|
259 |
|
|
.tck_i(tck_i),
|
260 |
|
|
.bp_i(cpu_bp_i),
|
261 |
|
|
.rst_i(rst_i),
|
262 |
|
|
.cpu_clk_i(cpu_clk_i),
|
263 |
|
|
.ctrl_reg_o(internal_reg_status),
|
264 |
|
|
.cpu_stall_o(cpu_stall_o),
|
265 |
|
|
.cpu_rst_o(cpu_rst_o)
|
266 |
|
|
);
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
///////////////////////////////////////////////
|
270 |
|
|
// Address counter
|
271 |
|
|
|
272 |
|
|
assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in;
|
273 |
|
|
assign incremented_address = address_counter + address_increment;
|
274 |
|
|
|
275 |
|
|
// Technically, since this data (sometimes) comes from the input shift reg, we should latch on
|
276 |
|
|
// negedge, per the JTAG spec. But that makes things difficult when incrementing.
|
277 |
|
|
always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
|
278 |
|
|
begin
|
279 |
|
|
if(rst_i)
|
280 |
|
|
address_counter <= 32'h0;
|
281 |
|
|
else if(addr_ct_en)
|
282 |
|
|
address_counter <= data_to_addr_counter;
|
283 |
|
|
end
|
284 |
|
|
|
285 |
|
|
////////////////////////////////////////
|
286 |
|
|
// Opcode latch
|
287 |
|
|
|
288 |
|
|
always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
|
289 |
|
|
begin
|
290 |
|
|
if(rst_i)
|
291 |
|
|
operation <= 4'h0;
|
292 |
|
|
else if(op_reg_en)
|
293 |
|
|
operation <= operation_in;
|
294 |
|
|
end
|
295 |
|
|
|
296 |
|
|
//////////////////////////////////////
|
297 |
|
|
// Bit counter
|
298 |
|
|
|
299 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
300 |
|
|
begin
|
301 |
|
|
|
302 |
|
|
if(rst_i) bit_count <= 6'h0;
|
303 |
|
|
else if(bit_ct_rst) bit_count <= 6'h0;
|
304 |
|
|
else if(bit_ct_en) bit_count <= bit_count + 6'h1;
|
305 |
|
|
|
306 |
|
|
end
|
307 |
|
|
|
308 |
|
|
assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ;
|
309 |
|
|
assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0;
|
310 |
|
|
|
311 |
|
|
////////////////////////////////////////
|
312 |
|
|
// Word counter
|
313 |
|
|
|
314 |
|
|
assign data_to_word_counter = (word_ct_sel) ? decremented_word_count : count_data_in;
|
315 |
|
|
assign decremented_word_count = word_count - 16'h1;
|
316 |
|
|
|
317 |
|
|
// Technically, since this data (sometimes) comes from the input shift reg, we should latch on
|
318 |
|
|
// negedge, per the JTAG spec. But that makes things difficult when incrementing.
|
319 |
|
|
always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
|
320 |
|
|
begin
|
321 |
|
|
if(rst_i)
|
322 |
|
|
word_count <= 16'h0;
|
323 |
|
|
else if(word_ct_en)
|
324 |
|
|
word_count <= data_to_word_counter;
|
325 |
|
|
end
|
326 |
|
|
|
327 |
|
|
assign word_count_zero = (word_count == 16'h0);
|
328 |
|
|
|
329 |
|
|
/////////////////////////////////////////////////////
|
330 |
|
|
// Output register and TDO output MUX
|
331 |
|
|
|
332 |
|
|
assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : data_from_biu;
|
333 |
|
|
|
334 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
335 |
|
|
begin
|
336 |
|
|
if(rst_i) data_out_shift_reg <= 32'h0;
|
337 |
|
|
else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
|
338 |
|
|
else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[31:1]};
|
339 |
|
|
end
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out)
|
343 |
|
|
begin
|
344 |
|
|
if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready;
|
345 |
|
|
else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0];
|
346 |
|
|
else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match;
|
347 |
|
|
else module_tdo_o <= crc_serial_out;
|
348 |
|
|
end
|
349 |
|
|
|
350 |
|
|
////////////////////////////////////////
|
351 |
|
|
// Bus Interface Unit (to OR1K SPR bus)
|
352 |
|
|
// It is assumed that the BIU has internal registers, and will
|
353 |
|
|
// latch address, operation, and write data on rising clock edge
|
354 |
|
|
// when strobe is asserted
|
355 |
|
|
|
356 |
|
|
adbg_or1k_biu or1k_biu_i (
|
357 |
|
|
// Debug interface signals
|
358 |
|
|
.tck_i (tck_i),
|
359 |
|
|
.rst_i (rst_i),
|
360 |
|
|
.data_i (data_to_biu),
|
361 |
|
|
.data_o (data_from_biu),
|
362 |
|
|
.addr_i (address_counter),
|
363 |
|
|
.strobe_i (biu_strobe),
|
364 |
|
|
.rd_wrn_i (rd_op), // If 0, then write op
|
365 |
|
|
.rdy_o (biu_ready),
|
366 |
|
|
// This bus has no error signal
|
367 |
|
|
|
368 |
|
|
// OR1K SPR bus signals
|
369 |
|
|
.cpu_clk_i(cpu_clk_i),
|
370 |
|
|
.cpu_addr_o(cpu_addr_o),
|
371 |
|
|
.cpu_data_i(cpu_data_i),
|
372 |
|
|
.cpu_data_o(cpu_data_o),
|
373 |
|
|
.cpu_stb_o(cpu_stb_o),
|
374 |
|
|
.cpu_we_o(cpu_we_o),
|
375 |
|
|
.cpu_ack_i(cpu_ack_i)
|
376 |
|
|
);
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
/////////////////////////////////////
|
381 |
|
|
// CRC module
|
382 |
|
|
|
383 |
|
|
assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0]; // MUX, write or read data
|
384 |
|
|
|
385 |
|
|
adbg_crc32 or1k_crc_i
|
386 |
|
|
(
|
387 |
|
|
.clk(tck_i),
|
388 |
|
|
.data(crc_data_in),
|
389 |
|
|
.enable(crc_en),
|
390 |
|
|
.shift(crc_shift_en),
|
391 |
|
|
.clr(crc_clr),
|
392 |
|
|
.rst(rst_i),
|
393 |
|
|
.crc_out(crc_data_out),
|
394 |
|
|
.serial_out(crc_serial_out)
|
395 |
|
|
);
|
396 |
|
|
|
397 |
|
|
assign crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0;
|
398 |
|
|
|
399 |
|
|
////////////////////////////////////////
|
400 |
|
|
// Control FSM
|
401 |
|
|
|
402 |
|
|
// Definition of machine state values.
|
403 |
|
|
// Don't worry too much about the state encoding, the synthesis tool
|
404 |
|
|
// will probably re-encode it anyway.
|
405 |
|
|
|
406 |
|
|
`define STATE_idle 4'h0
|
407 |
|
|
`define STATE_Rbegin 4'h1
|
408 |
|
|
`define STATE_Rready 4'h2
|
409 |
|
|
`define STATE_Rstatus 4'h3
|
410 |
|
|
`define STATE_Rburst 4'h4
|
411 |
|
|
`define STATE_Wready 4'h5
|
412 |
|
|
`define STATE_Wwait 4'h6
|
413 |
|
|
`define STATE_Wburst 4'h7
|
414 |
|
|
`define STATE_Wstatus 4'h8
|
415 |
|
|
`define STATE_Rcrc 4'h9
|
416 |
|
|
`define STATE_Wcrc 4'ha
|
417 |
|
|
`define STATE_Wmatch 4'hb
|
418 |
|
|
|
419 |
|
|
reg [3:0] module_state; // FSM state
|
420 |
|
|
reg [3:0] module_next_state; // combinatorial signal, not actually a register
|
421 |
|
|
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
// sequential part of the FSM
|
425 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
426 |
|
|
begin
|
427 |
|
|
if(rst_i)
|
428 |
|
|
module_state <= `STATE_idle;
|
429 |
|
|
else
|
430 |
|
|
module_state <= module_next_state;
|
431 |
|
|
end
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
// Determination of next state; purely combinatorial
|
435 |
|
|
always @ (module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
|
436 |
|
|
or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready
|
437 |
|
|
or module_cmd or intreg_write or decremented_word_count or burst_instruction)
|
438 |
|
|
begin
|
439 |
|
|
case(module_state)
|
440 |
|
|
`STATE_idle:
|
441 |
|
|
begin
|
442 |
|
|
if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin;
|
443 |
|
|
else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready;
|
444 |
|
|
else module_next_state <= `STATE_idle;
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
`STATE_Rbegin:
|
448 |
|
|
begin
|
449 |
|
|
if(word_count_zero) module_next_state <= `STATE_idle; // set up a burst of size 0, illegal.
|
450 |
|
|
else module_next_state <= `STATE_Rready;
|
451 |
|
|
end
|
452 |
|
|
`STATE_Rready:
|
453 |
|
|
begin
|
454 |
|
|
if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus;
|
455 |
|
|
else module_next_state <= `STATE_Rready;
|
456 |
|
|
end
|
457 |
|
|
`STATE_Rstatus:
|
458 |
|
|
begin
|
459 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
460 |
|
|
else if (biu_ready) module_next_state <= `STATE_Rburst;
|
461 |
|
|
else module_next_state <= `STATE_Rstatus;
|
462 |
|
|
end
|
463 |
|
|
`STATE_Rburst:
|
464 |
|
|
begin
|
465 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
466 |
|
|
else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
|
467 |
32 |
nyawn |
`ifndef ADBG_USE_HISPEED
|
468 |
3 |
nyawn |
else if(bit_count_max) module_next_state <= `STATE_Rstatus;
|
469 |
32 |
nyawn |
`endif
|
470 |
3 |
nyawn |
else module_next_state <= `STATE_Rburst;
|
471 |
|
|
end
|
472 |
|
|
`STATE_Rcrc:
|
473 |
|
|
begin
|
474 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
475 |
|
|
// This doubles as the 'recovery' state, so stay here until update_dr_i.
|
476 |
|
|
else module_next_state <= `STATE_Rcrc;
|
477 |
|
|
end
|
478 |
|
|
|
479 |
|
|
`STATE_Wready:
|
480 |
|
|
begin
|
481 |
|
|
if(word_count_zero) module_next_state <= `STATE_idle;
|
482 |
|
|
else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait;
|
483 |
|
|
else module_next_state <= `STATE_Wready;
|
484 |
|
|
end
|
485 |
|
|
`STATE_Wwait:
|
486 |
|
|
begin
|
487 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
488 |
|
|
else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst; // Got a start bit
|
489 |
|
|
else module_next_state <= `STATE_Wwait;
|
490 |
|
|
end
|
491 |
|
|
`STATE_Wburst:
|
492 |
|
|
begin
|
493 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
494 |
32 |
nyawn |
else if(bit_count_max)
|
495 |
|
|
begin
|
496 |
|
|
`ifdef ADBG_USE_HISPEED
|
497 |
|
|
if(word_count_zero) module_next_state <= `STATE_Wcrc;
|
498 |
|
|
else module_next_state <= `STATE_Wburst;
|
499 |
|
|
`else
|
500 |
|
|
module_next_state <= `STATE_Wstatus;
|
501 |
|
|
`endif
|
502 |
|
|
end
|
503 |
3 |
nyawn |
else module_next_state <= `STATE_Wburst;
|
504 |
|
|
end
|
505 |
|
|
`STATE_Wstatus:
|
506 |
|
|
begin
|
507 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
508 |
|
|
else if(word_count_zero) module_next_state <= `STATE_Wcrc;
|
509 |
|
|
// can't wait until bus ready if multiple devices in chain...
|
510 |
|
|
// Would have to read postfix_bits, then send another start bit and push it through
|
511 |
|
|
// prefix_bits...potentially very inefficient.
|
512 |
|
|
else module_next_state <= `STATE_Wburst;
|
513 |
|
|
end
|
514 |
|
|
|
515 |
|
|
`STATE_Wcrc:
|
516 |
|
|
begin
|
517 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
518 |
|
|
else if(bit_count_32) module_next_state <= `STATE_Wmatch;
|
519 |
|
|
else module_next_state <= `STATE_Wcrc;
|
520 |
|
|
end
|
521 |
|
|
|
522 |
|
|
`STATE_Wmatch:
|
523 |
|
|
begin
|
524 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
525 |
|
|
// This doubles as our recovery state, stay here until update_dr_i
|
526 |
|
|
else module_next_state <= `STATE_Wmatch;
|
527 |
|
|
end
|
528 |
|
|
|
529 |
|
|
default: module_next_state <= `STATE_idle; // shouldn't actually happen...
|
530 |
|
|
endcase
|
531 |
|
|
end
|
532 |
|
|
|
533 |
|
|
|
534 |
|
|
// Outputs of state machine, pure combinatorial
|
535 |
|
|
always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
|
536 |
|
|
or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction
|
537 |
|
|
or module_cmd or intreg_write or decremented_word_count)
|
538 |
|
|
begin
|
539 |
|
|
// Default everything to 0, keeps the case statement simple
|
540 |
|
|
addr_sel <= 1'b1; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count
|
541 |
|
|
addr_ct_en <= 1'b0; // Enable signal for address counter register
|
542 |
|
|
op_reg_en <= 1'b0; // Enable signal for 'operation' register
|
543 |
|
|
bit_ct_en <= 1'b0; // enable bit counter
|
544 |
|
|
bit_ct_rst <= 1'b0; // reset (zero) bit count register
|
545 |
|
|
word_ct_sel <= 1'b1; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
|
546 |
|
|
word_ct_en <= 1'b0; // Enable byte counter register
|
547 |
|
|
out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg
|
548 |
|
|
out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg
|
549 |
|
|
tdo_output_sel <= 2'b1; // 1 = data reg, 0 = biu_ready, 2 = crc_match, 3 = CRC data
|
550 |
|
|
biu_strobe <= 1'b0;
|
551 |
|
|
crc_clr <= 1'b0;
|
552 |
|
|
crc_en <= 1'b0; // add the input bit to the CRC calculation
|
553 |
|
|
crc_in_sel <= 1'b0; // 0 = tdo, 1 = tdi
|
554 |
|
|
crc_shift_en <= 1'b0;
|
555 |
|
|
out_reg_data_sel <= 1'b1; // 0 = BIU data, 1 = internal register data
|
556 |
|
|
regsel_ld_en <= 1'b0;
|
557 |
|
|
intreg_ld_en <= 1'b0;
|
558 |
|
|
top_inhibit_o <= 1'b0; // Don't disable the top-level module in the default case
|
559 |
|
|
|
560 |
|
|
case(module_state)
|
561 |
|
|
`STATE_idle:
|
562 |
|
|
begin
|
563 |
|
|
addr_sel <= 1'b0;
|
564 |
|
|
word_ct_sel <= 1'b0;
|
565 |
|
|
|
566 |
|
|
// Operations for internal registers - stay in idle state
|
567 |
|
|
if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1; // For module regs
|
568 |
|
|
if(module_select_i & capture_dr_i)
|
569 |
|
|
begin
|
570 |
|
|
out_reg_data_sel <= 1'b1; // select internal register data
|
571 |
|
|
out_reg_ld_en <= 1'b1; // For module regs
|
572 |
|
|
end
|
573 |
|
|
if(module_select_i & module_cmd & update_dr_i) begin
|
574 |
|
|
if(intreg_instruction) regsel_ld_en <= 1'b1; // For module regs
|
575 |
|
|
if(intreg_write) intreg_ld_en <= 1'b1; // For module regs
|
576 |
|
|
end
|
577 |
|
|
|
578 |
|
|
// Burst operations
|
579 |
|
|
if(module_next_state != `STATE_idle) begin // Do the same to receive read or write opcode
|
580 |
|
|
addr_ct_en <= 1'b1;
|
581 |
|
|
op_reg_en <= 1'b1;
|
582 |
|
|
bit_ct_rst <= 1'b1;
|
583 |
|
|
word_ct_en <= 1'b1;
|
584 |
|
|
crc_clr <= 1'b1;
|
585 |
|
|
end
|
586 |
|
|
end
|
587 |
|
|
|
588 |
|
|
`STATE_Rbegin:
|
589 |
|
|
begin
|
590 |
|
|
if(!word_count_zero) begin // Start a biu read transaction
|
591 |
|
|
biu_strobe <= 1'b1;
|
592 |
|
|
addr_sel <= 1'b1;
|
593 |
|
|
addr_ct_en <= 1'b1;
|
594 |
|
|
end
|
595 |
|
|
end
|
596 |
|
|
|
597 |
|
|
`STATE_Rready:
|
598 |
|
|
; // Just a wait state
|
599 |
|
|
|
600 |
|
|
`STATE_Rstatus:
|
601 |
|
|
begin
|
602 |
|
|
tdo_output_sel <= 2'h0;
|
603 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
604 |
|
|
|
605 |
32 |
nyawn |
if (module_next_state == `STATE_Rburst)
|
606 |
|
|
begin
|
607 |
|
|
out_reg_data_sel <= 1'b0; // select BIU data
|
608 |
|
|
out_reg_ld_en <= 1'b1;
|
609 |
|
|
bit_ct_rst <= 1'b1;
|
610 |
|
|
word_ct_sel <= 1'b1;
|
611 |
|
|
word_ct_en <= 1'b1;
|
612 |
|
|
if(!(decremented_word_count == 0) && !word_count_zero) // Start a biu read transaction
|
613 |
|
|
begin
|
614 |
|
|
biu_strobe <= 1'b1;
|
615 |
|
|
addr_sel <= 1'b1;
|
616 |
|
|
addr_ct_en <= 1'b1;
|
617 |
|
|
end
|
618 |
3 |
nyawn |
end
|
619 |
|
|
end
|
620 |
|
|
|
621 |
|
|
`STATE_Rburst:
|
622 |
|
|
begin
|
623 |
|
|
tdo_output_sel <= 2'h1;
|
624 |
|
|
out_reg_shift_en <= 1'b1;
|
625 |
|
|
bit_ct_en <= 1'b1;
|
626 |
|
|
crc_en <= 1'b1;
|
627 |
|
|
crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo)
|
628 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
629 |
32 |
nyawn |
|
630 |
|
|
`ifdef ADBG_USE_HISPEED
|
631 |
|
|
if(bit_count_max)
|
632 |
|
|
begin
|
633 |
|
|
out_reg_data_sel <= 1'b0; // select BIU data
|
634 |
|
|
out_reg_ld_en <= 1'b1;
|
635 |
|
|
bit_ct_rst <= 1'b1;
|
636 |
|
|
word_ct_sel <= 1'b1;
|
637 |
|
|
word_ct_en <= 1'b1;
|
638 |
|
|
if(!(decremented_word_count == 0) && !word_count_zero) // Start a biu read transaction
|
639 |
|
|
begin
|
640 |
|
|
biu_strobe <= 1'b1;
|
641 |
|
|
addr_sel <= 1'b1;
|
642 |
|
|
addr_ct_en <= 1'b1;
|
643 |
|
|
end
|
644 |
|
|
end
|
645 |
|
|
`endif
|
646 |
3 |
nyawn |
end
|
647 |
|
|
|
648 |
|
|
`STATE_Rcrc:
|
649 |
|
|
begin
|
650 |
|
|
// Just shift out the data, don't bother counting, we don't move on until update_dr_i
|
651 |
|
|
tdo_output_sel <= 2'h3;
|
652 |
|
|
crc_shift_en <= 1'b1;
|
653 |
|
|
top_inhibit_o <= 1'b1;
|
654 |
|
|
end
|
655 |
|
|
|
656 |
|
|
`STATE_Wready:
|
657 |
|
|
; // Just a wait state
|
658 |
|
|
|
659 |
|
|
`STATE_Wwait:
|
660 |
|
|
begin
|
661 |
|
|
tdo_output_sel <= 2'h1;
|
662 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
663 |
|
|
if(module_next_state == `STATE_Wburst) begin
|
664 |
|
|
bit_ct_en <= 1'b1;
|
665 |
|
|
word_ct_sel <= 1'b1; // Pre-decrement the byte count
|
666 |
|
|
word_ct_en <= 1'b1;
|
667 |
|
|
crc_en <= 1'b1; // CRC gets tdi_i, which is 1 cycle ahead of data_register_i, so we need the bit there now in the CRC
|
668 |
|
|
crc_in_sel <= 1'b1; // read data from tdi_i
|
669 |
|
|
end
|
670 |
|
|
end
|
671 |
|
|
|
672 |
|
|
`STATE_Wburst:
|
673 |
|
|
begin
|
674 |
|
|
bit_ct_en <= 1'b1;
|
675 |
|
|
tdo_output_sel <= 2'h1;
|
676 |
|
|
crc_en <= 1'b1;
|
677 |
|
|
crc_in_sel <= 1'b1; // read data from tdi_i
|
678 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
679 |
32 |
nyawn |
|
680 |
|
|
`ifdef ADBG_USE_HISPEED
|
681 |
|
|
// It would be better to do this in STATE_Wstatus, but we don't use that state
|
682 |
|
|
// if ADBG_USE_HISPEED is defined.
|
683 |
|
|
if(bit_count_max)
|
684 |
|
|
begin
|
685 |
|
|
bit_ct_rst <= 1'b1; // Zero the bit count
|
686 |
|
|
// start transaction. Can't do this here if not hispeed, biu_ready
|
687 |
|
|
// is the status bit, and it's 0 if we start a transaction here.
|
688 |
|
|
biu_strobe <= 1'b1; // Start a BIU transaction
|
689 |
|
|
addr_ct_en <= 1'b1; // Increment thte address counter
|
690 |
|
|
// Also can't dec the byte count yet unless hispeed,
|
691 |
|
|
// that would skip the last word.
|
692 |
|
|
word_ct_sel <= 1'b1; // Decrement the byte count
|
693 |
|
|
word_ct_en <= 1'b1;
|
694 |
|
|
end
|
695 |
|
|
`endif
|
696 |
3 |
nyawn |
end
|
697 |
|
|
|
698 |
|
|
`STATE_Wstatus:
|
699 |
|
|
begin
|
700 |
|
|
tdo_output_sel <= 2'h0; // Send the status bit to TDO
|
701 |
|
|
// start transaction
|
702 |
|
|
biu_strobe <= 1'b1; // Start a BIU transaction
|
703 |
|
|
word_ct_sel <= 1'b1; // Decrement the byte count
|
704 |
|
|
word_ct_en <= 1'b1;
|
705 |
|
|
bit_ct_rst <= 1'b1; // Zero the bit count
|
706 |
|
|
addr_ct_en <= 1'b1; // Increment thte address counter
|
707 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
708 |
|
|
end
|
709 |
|
|
|
710 |
|
|
`STATE_Wcrc:
|
711 |
|
|
begin
|
712 |
|
|
bit_ct_en <= 1'b1;
|
713 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
714 |
|
|
if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2; // This is when the 'match' bit is actually read
|
715 |
|
|
end
|
716 |
|
|
|
717 |
|
|
`STATE_Wmatch:
|
718 |
|
|
begin
|
719 |
|
|
tdo_output_sel <= 2'h2;
|
720 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
721 |
|
|
end
|
722 |
|
|
|
723 |
|
|
default: ;
|
724 |
|
|
endcase
|
725 |
|
|
end
|
726 |
|
|
|
727 |
|
|
|
728 |
|
|
endmodule
|
729 |
|
|
|