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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_status_reg.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_or1k_status_reg.v                                      ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2008 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_or1k_status_reg.v,v $
// Revision 1.1  2008/07/22 20:28:31  Nathan
// Changed names of all files and modules (prefixed an a, for advanced).  Cleanup, indenting.  No functional changes.
//
// Revision 1.3  2008/07/06 20:02:54  Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with 
// Quartus II 7.0).  Ran through dos2unix.
//
// Revision 1.2  2008/06/26 20:52:32  Nathan
// OR1K module tested and working.  Added copyright / license info 
// to _define files.  Other cleanup.
//
//
//
//
 
`include "adbg_or1k_defines.v"
 
module adbg_or1k_status_reg  (
                              data_i,
                              we_i,
                              tck_i,
                              bp_i,
                              rst_i,
                              cpu_clk_i,
                              ctrl_reg_o,
                              cpu_stall_o,
                              cpu_rst_o
                              );
 
 
   input  [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
   input                               we_i;
   input                               tck_i;
   input                               bp_i;
   input                               rst_i;
   input                               cpu_clk_i;
 
   output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
   output                              cpu_stall_o;
   output                              cpu_rst_o;
 
   reg                                 cpu_reset;
   wire [2:1]                          cpu_op_out;
 
   reg                                 stall_bp, stall_bp_csff, stall_bp_tck;
   reg                                 stall_reg, stall_reg_csff, stall_reg_cpu;
   reg                                 cpu_reset_csff;
   reg                                 cpu_rst_o;
 
 
 
   // Breakpoint is latched and synchronized. Stall is set and latched.
   // This is done in the CPU clock domain, because the JTAG clock (TCK) is
   // irregular.  By only allowing bp_i to set (but not reset) the stall_bp
   // signal, we insure that the CPU will remain in the stalled state until
   // the debug host can read the state.
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if(rst_i)
          stall_bp <= #1 1'b0;
        else if(bp_i)
          stall_bp <= #1 1'b1;
        else if(stall_reg_cpu)
          stall_bp <= #1 1'b0;
     end
 
 
   // Synchronizing
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             stall_bp_csff <= #1 1'b0;
             stall_bp_tck  <= #1 1'b0;
          end
        else
          begin
             stall_bp_csff <= #1 stall_bp;
             stall_bp_tck  <= #1 stall_bp_csff;
          end
     end
 
 
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             stall_reg_csff <= #1 1'b0;
             stall_reg_cpu  <= #1 1'b0;
          end
        else
          begin
             stall_reg_csff <= #1 stall_reg;
             stall_reg_cpu  <= #1 stall_reg_csff;
          end
     end
 
   // bp_i forces a stall immediately on a breakpoint
   // stall_bp holds the stall until the debug host acts
   // stall_reg_cpu allows the debug host to control a stall.
   assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
   // Writing data to the control registers (stall)
   // This can be set either by the debug host, or by
   // a CPU breakpoint.  It can only be cleared by the host.
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          stall_reg <= #1 1'b0;
        else if (stall_bp_tck)
          stall_reg <= #1 1'b1;
        else if (we_i)
          stall_reg <= #1 data_i[0];
     end
 
 
   // Writing data to the control registers (reset)
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          cpu_reset  <= #1 1'b0;
        else if(we_i)
          cpu_reset  <= #1 data_i[1];
     end
 
 
   // Synchronizing signals from registers
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             cpu_reset_csff      <= #1 1'b0;
             cpu_rst_o           <= #1 1'b0;
          end
        else
          begin
             cpu_reset_csff      <= #1 cpu_reset;
             cpu_rst_o           <= #1 cpu_reset_csff;
          end
     end
 
 
 
   // Value for read back
   assign ctrl_reg_o = {cpu_reset, stall_reg};
 
 
endmodule
 

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_or1k_status_reg.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Igor Mohor (igorm@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 - 2008 Authors ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39			`//`
40			`// CVS Revision History`
41			`//`
42			`// $Log: adbg_or1k_status_reg.v,v $`
43			`// Revision 1.1 2008/07/22 20:28:31 Nathan`
44			`// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.`
45			`//`
46			`// Revision 1.3 2008/07/06 20:02:54 Nathan`
47			`// Fixes for synthesis with Xilinx ISE (also synthesizable with`
48			`// Quartus II 7.0). Ran through dos2unix.`
49			`//`
50			`// Revision 1.2 2008/06/26 20:52:32 Nathan`
51			`// OR1K module tested and working. Added copyright / license info`
52			`// to _define files. Other cleanup.`
53			`//`
54			`//`
55			`//`
56			`//`
57
58			`include "adbg_or1k_defines.v"
59
60			`module adbg_or1k_status_reg (`
61			`data_i,`
62			`we_i,`
63			`tck_i,`
64			`bp_i,`
65			`rst_i,`
66			`cpu_clk_i,`
67			`ctrl_reg_o,`
68			`cpu_stall_o,`
69			`cpu_rst_o`
70			`);`
71
72
73			input [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
74			`input we_i;`
75			`input tck_i;`
76			`input bp_i;`
77			`input rst_i;`
78			`input cpu_clk_i;`
79
80			output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
81			`output cpu_stall_o;`
82			`output cpu_rst_o;`
83
84			`reg cpu_reset;`
85			`wire [2:1] cpu_op_out;`
86
87			`reg stall_bp, stall_bp_csff, stall_bp_tck;`
88			`reg stall_reg, stall_reg_csff, stall_reg_cpu;`
89			`reg cpu_reset_csff;`
90			`reg cpu_rst_o;`
91
92
93
94			`// Breakpoint is latched and synchronized. Stall is set and latched.`
95			`// This is done in the CPU clock domain, because the JTAG clock (TCK) is`
96			`// irregular. By only allowing bp_i to set (but not reset) the stall_bp`
97			`// signal, we insure that the CPU will remain in the stalled state until`
98			`// the debug host can read the state.`
99			`always @ (posedge cpu_clk_i or posedge rst_i)`
100			`begin`
101			`if(rst_i)`
102			`stall_bp <= #1 1'b0;`
103			`else if(bp_i)`
104			`stall_bp <= #1 1'b1;`
105			`else if(stall_reg_cpu)`
106			`stall_bp <= #1 1'b0;`
107			`end`
108
109
110			`// Synchronizing`
111			`always @ (posedge tck_i or posedge rst_i)`
112			`begin`
113			`if (rst_i)`
114			`begin`
115			`stall_bp_csff <= #1 1'b0;`
116			`stall_bp_tck <= #1 1'b0;`
117			`end`
118			`else`
119			`begin`
120			`stall_bp_csff <= #1 stall_bp;`
121			`stall_bp_tck <= #1 stall_bp_csff;`
122			`end`
123			`end`
124
125
126			`always @ (posedge cpu_clk_i or posedge rst_i)`
127			`begin`
128			`if (rst_i)`
129			`begin`
130			`stall_reg_csff <= #1 1'b0;`
131			`stall_reg_cpu <= #1 1'b0;`
132			`end`
133			`else`
134			`begin`
135			`stall_reg_csff <= #1 stall_reg;`
136			`stall_reg_cpu <= #1 stall_reg_csff;`
137			`end`
138			`end`
139
140			`// bp_i forces a stall immediately on a breakpoint`
141			`// stall_bp holds the stall until the debug host acts`
142			`// stall_reg_cpu allows the debug host to control a stall.`
143			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
144
145
146			`// Writing data to the control registers (stall)`
147			`// This can be set either by the debug host, or by`
148			`// a CPU breakpoint. It can only be cleared by the host.`
149			`always @ (posedge tck_i or posedge rst_i)`
150			`begin`
151			`if (rst_i)`
152			`stall_reg <= #1 1'b0;`
153			`else if (stall_bp_tck)`
154			`stall_reg <= #1 1'b1;`
155			`else if (we_i)`
156			`stall_reg <= #1 data_i[0];`
157			`end`
158
159
160			`// Writing data to the control registers (reset)`
161			`always @ (posedge tck_i or posedge rst_i)`
162			`begin`
163			`if (rst_i)`
164			`cpu_reset <= #1 1'b0;`
165			`else if(we_i)`
166			`cpu_reset <= #1 data_i[1];`
167			`end`
168
169
170			`// Synchronizing signals from registers`
171			`always @ (posedge cpu_clk_i or posedge rst_i)`
172			`begin`
173			`if (rst_i)`
174			`begin`
175			`cpu_reset_csff <= #1 1'b0;`
176			`cpu_rst_o <= #1 1'b0;`
177			`end`
178			`else`
179			`begin`
180			`cpu_reset_csff <= #1 cpu_reset;`
181			`cpu_rst_o <= #1 cpu_reset_csff;`
182			`end`
183			`end`
184
185
186
187			`// Value for read back`
188			`assign ctrl_reg_o = {cpu_reset, stall_reg};`
189
190
191			`endmodule`
192

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_status_reg.v] - Blame information for rev 3