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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the jtag.pdf     ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2008 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_top.v,v $
// Revision 1.4  2009/05/17 20:54:38  Nathan
// Changed email address to opencores.org
//
// Revision 1.3  2008/06/18 18:45:07  Nathan
// Improved reset slightly.  Cleanup.
//
//
// Revision 1.2 2008/05/14 13:13:24 Nathan
// Rewrote TAP FSM in canonical form, for readability.  Switched
// from one-hot to binary encoding.  Made reset signal active-
// low, per JTAG spec.  Removed FF chain for 5 TMS reset - reset
// done in Test Logic Reset mode.  Added test_logic_reset_o and
// run_test_idle_o signals.  Removed double registers from IR data
// path.  Unified the registers at the output of each data register
// to a single shared FF.
//
// Revision 1.6  2004/01/27 10:00:33  mohor
// Unused registers removed.
//
// Revision 1.5  2004/01/18 09:27:39  simons
// Blocking non blocking assignmenst fixed.
//
// Revision 1.4  2004/01/17 17:37:44  mohor
// capture_dr_o added to ports.
//
// Revision 1.3  2004/01/14 13:50:56  mohor
// 5 consecutive TMS=1 causes reset of TAP.
//
// Revision 1.2  2004/01/08 10:29:44  mohor
// Control signals for tdo_pad_o mux are changed to negedge.
//
// Revision 1.1  2003/12/23 14:52:14  mohor
// Directory structure changed. New version of TAP.
//
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trstn_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                                test_logic_reset_o,
                                run_test_idle_o,
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trstn_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  test_logic_reset_o;
output  run_test_idle_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Wires which depend on the state of the TAP FSM
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
 
// Wires which depend on the current value in the IR
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
 
// TDO and enable
reg     tdo_pad_o;
reg     tdo_padoe_o;
 
assign tdo_o = tdi_pad_i;
 
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
// Definition of machine state values.  We could one-hot encode this, and use 16
// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle    4'hC
`define STATE_select_dr_scan   4'h7
`define STATE_capture_dr       4'h6
`define STATE_shift_dr         4'h2
`define STATE_exit1_dr         4'h1
`define STATE_pause_dr         4'h3
`define STATE_exit2_dr         4'h0
`define STATE_update_dr        4'h5
`define STATE_select_ir_scan   4'h4
`define STATE_capture_ir       4'hE
`define STATE_shift_ir         4'hA
`define STATE_exit1_ir         4'h9
`define STATE_pause_ir         4'hB
`define STATE_exit2_ir         4'h8
`define STATE_update_ir        4'hD
 
reg [3:0] TAP_state = `STATE_test_logic_reset;  // current state of the TAP controller
reg [3:0] next_TAP_state;  // state TAP will take at next rising TCK, combinational signal
 
// sequential part of the FSM
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
        if(trstn_pad_i == 0)
                TAP_state = `STATE_test_logic_reset;
        else
                TAP_state = next_TAP_state;
end
 
 
// Determination of next state; purely combinatorial
always @ (TAP_state or tms_pad_i)
begin
        case(TAP_state)
                `STATE_test_logic_reset:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_run_test_idle:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_dr_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
                        else next_TAP_state = `STATE_capture_dr;
                        end
                `STATE_capture_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_shift_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_exit1_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_pause_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_exit2_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_update_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_ir_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_capture_ir;
                        end
                `STATE_capture_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_shift_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_exit1_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_pause_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_exit2_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_update_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                default: next_TAP_state = `STATE_test_logic_reset;  // can't actually happen
        endcase
end
 
 
// Outputs of state machine, pure combinatorial
always @ (TAP_state)
begin
        // Default everything to 0, keeps the case statement simple
        test_logic_reset = 1'b0;
        run_test_idle = 1'b0;
        select_dr_scan = 1'b0;
        capture_dr = 1'b0;
        shift_dr = 1'b0;
        exit1_dr = 1'b0;
        pause_dr = 1'b0;
        exit2_dr = 1'b0;
        update_dr = 1'b0;
        select_ir_scan = 1'b0;
        capture_ir = 1'b0;
        shift_ir = 1'b0;
        exit1_ir = 1'b0;
        pause_ir = 1'b0;
        exit2_ir = 1'b0;
        update_ir = 1'b0;
 
        case(TAP_state)
                `STATE_test_logic_reset: test_logic_reset = 1'b1;
                `STATE_run_test_idle:    run_test_idle = 1'b1;
                `STATE_select_dr_scan:   select_dr_scan = 1'b1;
                `STATE_capture_dr:       capture_dr = 1'b1;
                `STATE_shift_dr:         shift_dr = 1'b1;
                `STATE_exit1_dr:         exit1_dr = 1'b1;
                `STATE_pause_dr:         pause_dr = 1'b1;
                `STATE_exit2_dr:         exit2_dr = 1'b1;
                `STATE_update_dr:        update_dr = 1'b1;
                `STATE_select_ir_scan:   select_ir_scan = 1'b1;
                `STATE_capture_ir:       capture_ir = 1'b1;
                `STATE_shift_ir:         shift_ir = 1'b1;
                `STATE_exit1_ir:         exit1_ir = 1'b1;
                `STATE_pause_ir:         pause_ir = 1'b1;
                `STATE_exit2_ir:         exit2_ir = 1'b1;
                `STATE_update_ir:        update_ir = 1'b1;
                default: ;
        endcase
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir; //, latched_jtag_ir_neg;
wire                  instruction_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if (test_logic_reset == 1)
        jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
assign instruction_tdo = jtag_ir[0];  // This is latched on a negative TCK edge after the output MUX
 
// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if (test_logic_reset)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
wire        idcode_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    idcode_reg <=#1 `IDCODE_VALUE;   // IDCODE selected after reset
  else if (test_logic_reset)
    idcode_reg <=#1 `IDCODE_VALUE;   // IDCODE selected after reset
  else if(idcode_select & capture_dr)
    idcode_reg <= #1 `IDCODE_VALUE;
  else if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
 
end
 
assign idcode_tdo = idcode_reg[0];   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
wire  bypassed_tdo;
reg   bypass_reg;  // This is a 1-bit register
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if (trstn_pad_i == 0)
     bypass_reg <= #1 1'b0;
  else if (test_logic_reset == 1)
     bypass_reg <= #1 1'b0;
  else if (bypass_select & capture_dr)
    bypass_reg<=#1 1'b0;
  else if(bypass_select & shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
assign bypassed_tdo = bypass_reg;   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting active data register                                                *
*                                                                                 *
**********************************************************************************/
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
reg tdo_mux_out;  // really just a wire
 
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or bypassed_tdo or
                        bs_chain_tdi_i)
begin
  if(shift_ir)
    tdo_mux_out = instruction_tdo;
  else
    begin
      case(latched_jtag_ir)    // synthesis parallel_case
        `IDCODE:            tdo_mux_out = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_mux_out = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_mux_out = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_mux_out = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_mux_out = mbist_tdi_i;      // Mbist test
        default:            tdo_mux_out = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// TDO changes state at negative edge of TCK
always @ (negedge tck_pad_i)
begin
        tdo_pad_o = tdo_mux_out;
end
 
 
// Tristate control for tdo_pad_o pin
always @ (posedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr;
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Igor Mohor (igorm@opencores.org) ////`
10			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the jtag.pdf ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2008 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: tap_top.v,v $`
46			`// Revision 1.4 2009/05/17 20:54:38 Nathan`
47			`// Changed email address to opencores.org`
48			`//`
49			`// Revision 1.3 2008/06/18 18:45:07 Nathan`
50			`// Improved reset slightly. Cleanup.`
51			`//`
52			`//`
53			`// Revision 1.2 2008/05/14 13:13:24 Nathan`
54			`// Rewrote TAP FSM in canonical form, for readability. Switched`
55			`// from one-hot to binary encoding. Made reset signal active-`
56			`// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset`
57			`// done in Test Logic Reset mode. Added test_logic_reset_o and`
58			`// run_test_idle_o signals. Removed double registers from IR data`
59			`// path. Unified the registers at the output of each data register`
60			`// to a single shared FF.`
61			`//`
62			`// Revision 1.6 2004/01/27 10:00:33 mohor`
63			`// Unused registers removed.`
64			`//`
65			`// Revision 1.5 2004/01/18 09:27:39 simons`
66			`// Blocking non blocking assignmenst fixed.`
67			`//`
68			`// Revision 1.4 2004/01/17 17:37:44 mohor`
69			`// capture_dr_o added to ports.`
70			`//`
71			`// Revision 1.3 2004/01/14 13:50:56 mohor`
72			`// 5 consecutive TMS=1 causes reset of TAP.`
73			`//`
74			`// Revision 1.2 2004/01/08 10:29:44 mohor`
75			`// Control signals for tdo_pad_o mux are changed to negedge.`
76			`//`
77			`// Revision 1.1 2003/12/23 14:52:14 mohor`
78			`// Directory structure changed. New version of TAP.`
79			`//`
80			`// Revision 1.10 2003/10/23 18:08:01 mohor`
81			`// MBIST chain connection fixed.`
82			`//`
83			`// Revision 1.9 2003/10/23 16:17:02 mohor`
84			`// CRC logic changed.`
85			`//`
86			`// Revision 1.8 2003/10/21 09:48:31 simons`
87			`// Mbist support added.`
88			`//`
89			`// Revision 1.7 2002/11/06 14:30:10 mohor`
90			`// Trst active high. Inverted on higher layer.`
91			`//`
92			`// Revision 1.6 2002/04/22 12:55:56 mohor`
93			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
94			`//`
95			`// Revision 1.5 2002/03/26 14:23:38 mohor`
96			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
97			`//`
98			`// Revision 1.4 2002/03/25 13:16:15 mohor`
99			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
100			`// not named correctly.`
101			`//`
102			`// Revision 1.3 2002/03/12 14:30:05 mohor`
103			`// Few outputs for boundary scan chain added.`
104			`//`
105			`// Revision 1.2 2002/03/12 10:31:53 mohor`
106			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
107			`// contains only tap state machine and related logic. dbg_top contains all`
108			`// logic necessery for debugging.`
109			`//`
110			`// Revision 1.1 2002/03/08 15:28:16 mohor`
111			`// Structure changed. Hooks for jtag chain added.`
112			`//`
113			`//`
114			`//`
115			`//`
116
117			`include "tap_defines.v"
118
119			`// Top module`
120			`module tap_top(`
121			`// JTAG pads`
122			`tms_pad_i,`
123			`tck_pad_i,`
124			`trstn_pad_i,`
125			`tdi_pad_i,`
126			`tdo_pad_o,`
127			`tdo_padoe_o,`
128
129			`// TAP states`
130			`test_logic_reset_o,`
131			`run_test_idle_o,`
132			`shift_dr_o,`
133			`pause_dr_o,`
134			`update_dr_o,`
135			`capture_dr_o,`
136
137			`// Select signals for boundary scan or mbist`
138			`extest_select_o,`
139			`sample_preload_select_o,`
140			`mbist_select_o,`
141			`debug_select_o,`
142
143			`// TDO signal that is connected to TDI of sub-modules.`
144			`tdo_o,`
145
146			`// TDI signals from sub-modules`
147			`debug_tdi_i, // from debug module`
148			`bs_chain_tdi_i, // from Boundary Scan Chain`
149			`mbist_tdi_i // from Mbist Chain`
150			`);`
151
152
153			`// JTAG pins`
154			`input tms_pad_i; // JTAG test mode select pad`
155			`input tck_pad_i; // JTAG test clock pad`
156			`input trstn_pad_i; // JTAG test reset pad`
157			`input tdi_pad_i; // JTAG test data input pad`
158			`output tdo_pad_o; // JTAG test data output pad`
159			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
160
161			`// TAP states`
162			`output test_logic_reset_o;`
163			`output run_test_idle_o;`
164			`output shift_dr_o;`
165			`output pause_dr_o;`
166			`output update_dr_o;`
167			`output capture_dr_o;`
168
169			`// Select signals for boundary scan or mbist`
170			`output extest_select_o;`
171			`output sample_preload_select_o;`
172			`output mbist_select_o;`
173			`output debug_select_o;`
174
175			`// TDO signal that is connected to TDI of sub-modules.`
176			`output tdo_o;`
177
178			`// TDI signals from sub-modules`
179			`input debug_tdi_i; // from debug module`
180			`input bs_chain_tdi_i; // from Boundary Scan Chain`
181			`input mbist_tdi_i; // from Mbist Chain`
182
183			`// Wires which depend on the state of the TAP FSM`
184			`reg test_logic_reset;`
185			`reg run_test_idle;`
186			`reg select_dr_scan;`
187			`reg capture_dr;`
188			`reg shift_dr;`
189			`reg exit1_dr;`
190			`reg pause_dr;`
191			`reg exit2_dr;`
192			`reg update_dr;`
193			`reg select_ir_scan;`
194			`reg capture_ir;`
195			`reg shift_ir;`
196			`reg exit1_ir;`
197			`reg pause_ir;`
198			`reg exit2_ir;`
199			`reg update_ir;`
200
201			`// Wires which depend on the current value in the IR`
202			`reg extest_select;`
203			`reg sample_preload_select;`
204			`reg idcode_select;`
205			`reg mbist_select;`
206			`reg debug_select;`
207			`reg bypass_select;`
208
209			`// TDO and enable`
210			`reg tdo_pad_o;`
211			`reg tdo_padoe_o;`
212
213			`assign tdo_o = tdi_pad_i;`
214
215			`assign test_logic_reset_o = test_logic_reset;`
216			`assign run_test_idle_o = run_test_idle;`
217			`assign shift_dr_o = shift_dr;`
218			`assign pause_dr_o = pause_dr;`
219			`assign update_dr_o = update_dr;`
220			`assign capture_dr_o = capture_dr;`
221
222			`assign extest_select_o = extest_select;`
223			`assign sample_preload_select_o = sample_preload_select;`
224			`assign mbist_select_o = mbist_select;`
225			`assign debug_select_o = debug_select;`
226
227
228			`/**********************************************************************************`
229			`* *`
230			`* TAP State Machine: Fully JTAG compliant *`
231			`* *`
232			`**********************************************************************************/`
233			`// Definition of machine state values. We could one-hot encode this, and use 16`
234			`// registers, but this uses binary encoding for the minimum of 4 DFF's instead.`
235			`define STATE_test_logic_reset 4'hF
236			`define STATE_run_test_idle 4'hC
237			`define STATE_select_dr_scan 4'h7
238			`define STATE_capture_dr 4'h6
239			`define STATE_shift_dr 4'h2
240			`define STATE_exit1_dr 4'h1
241			`define STATE_pause_dr 4'h3
242			`define STATE_exit2_dr 4'h0
243			`define STATE_update_dr 4'h5
244			`define STATE_select_ir_scan 4'h4
245			`define STATE_capture_ir 4'hE
246			`define STATE_shift_ir 4'hA
247			`define STATE_exit1_ir 4'h9
248			`define STATE_pause_ir 4'hB
249			`define STATE_exit2_ir 4'h8
250			`define STATE_update_ir 4'hD
251
252			reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
253			`reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal`
254
255			`// sequential part of the FSM`
256			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
257			`begin`
258			`if(trstn_pad_i == 0)`
259			TAP_state = `STATE_test_logic_reset;
260			`else`
261			`TAP_state = next_TAP_state;`
262			`end`
263
264
265			`// Determination of next state; purely combinatorial`
266			`always @ (TAP_state or tms_pad_i)`
267			`begin`
268			`case(TAP_state)`
269			`STATE_test_logic_reset:
270			`begin`
271			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
272			else next_TAP_state = `STATE_run_test_idle;
273			`end`
274			`STATE_run_test_idle:
275			`begin`
276			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
277			else next_TAP_state = `STATE_run_test_idle;
278			`end`
279			`STATE_select_dr_scan:
280			`begin`
281			if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
282			else next_TAP_state = `STATE_capture_dr;
283			`end`
284			`STATE_capture_dr:
285			`begin`
286			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
287			else next_TAP_state = `STATE_shift_dr;
288			`end`
289			`STATE_shift_dr:
290			`begin`
291			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
292			else next_TAP_state = `STATE_shift_dr;
293			`end`
294			`STATE_exit1_dr:
295			`begin`
296			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
297			else next_TAP_state = `STATE_pause_dr;
298			`end`
299			`STATE_pause_dr:
300			`begin`
301			if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
302			else next_TAP_state = `STATE_pause_dr;
303			`end`
304			`STATE_exit2_dr:
305			`begin`
306			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
307			else next_TAP_state = `STATE_shift_dr;
308			`end`
309			`STATE_update_dr:
310			`begin`
311			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
312			else next_TAP_state = `STATE_run_test_idle;
313			`end`
314			`STATE_select_ir_scan:
315			`begin`
316			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
317			else next_TAP_state = `STATE_capture_ir;
318			`end`
319			`STATE_capture_ir:
320			`begin`
321			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
322			else next_TAP_state = `STATE_shift_ir;
323			`end`
324			`STATE_shift_ir:
325			`begin`
326			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
327			else next_TAP_state = `STATE_shift_ir;
328			`end`
329			`STATE_exit1_ir:
330			`begin`
331			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
332			else next_TAP_state = `STATE_pause_ir;
333			`end`
334			`STATE_pause_ir:
335			`begin`
336			if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
337			else next_TAP_state = `STATE_pause_ir;
338			`end`
339			`STATE_exit2_ir:
340			`begin`
341			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
342			else next_TAP_state = `STATE_shift_ir;
343			`end`
344			`STATE_update_ir:
345			`begin`
346			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
347			else next_TAP_state = `STATE_run_test_idle;
348			`end`
349			default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
350			`endcase`
351			`end`
352
353
354			`// Outputs of state machine, pure combinatorial`
355			`always @ (TAP_state)`
356			`begin`
357			`// Default everything to 0, keeps the case statement simple`
358			`test_logic_reset = 1'b0;`
359			`run_test_idle = 1'b0;`
360			`select_dr_scan = 1'b0;`
361			`capture_dr = 1'b0;`
362			`shift_dr = 1'b0;`
363			`exit1_dr = 1'b0;`
364			`pause_dr = 1'b0;`
365			`exit2_dr = 1'b0;`
366			`update_dr = 1'b0;`
367			`select_ir_scan = 1'b0;`
368			`capture_ir = 1'b0;`
369			`shift_ir = 1'b0;`
370			`exit1_ir = 1'b0;`
371			`pause_ir = 1'b0;`
372			`exit2_ir = 1'b0;`
373			`update_ir = 1'b0;`
374
375			`case(TAP_state)`
376			`STATE_test_logic_reset: test_logic_reset = 1'b1;
377			`STATE_run_test_idle: run_test_idle = 1'b1;
378			`STATE_select_dr_scan: select_dr_scan = 1'b1;
379			`STATE_capture_dr: capture_dr = 1'b1;
380			`STATE_shift_dr: shift_dr = 1'b1;
381			`STATE_exit1_dr: exit1_dr = 1'b1;
382			`STATE_pause_dr: pause_dr = 1'b1;
383			`STATE_exit2_dr: exit2_dr = 1'b1;
384			`STATE_update_dr: update_dr = 1'b1;
385			`STATE_select_ir_scan: select_ir_scan = 1'b1;
386			`STATE_capture_ir: capture_ir = 1'b1;
387			`STATE_shift_ir: shift_ir = 1'b1;
388			`STATE_exit1_ir: exit1_ir = 1'b1;
389			`STATE_pause_ir: pause_ir = 1'b1;
390			`STATE_exit2_ir: exit2_ir = 1'b1;
391			`STATE_update_ir: update_ir = 1'b1;
392			`default: ;`
393			`endcase`
394			`end`
395
396			`/**********************************************************************************`
397			`* *`
398			`* End: TAP State Machine *`
399			`* *`
400			`**********************************************************************************/`
401
402
403
404			`/**********************************************************************************`
405			`* *`
406			`* jtag_ir: JTAG Instruction Register *`
407			`* *`
408			`**********************************************************************************/`
409			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
410			reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
411			`wire instruction_tdo;`
412
413			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
414			`begin`
415			`if(trstn_pad_i == 0)`
416			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
417			`else if (test_logic_reset == 1)`
418			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
419			`else if(capture_ir)`
420			`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
421			`else if(shift_ir)`
422			jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
423			`end`
424
425			`assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX`
426
427			`// Updating jtag_ir (Instruction Register)`
428			`// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1`
429			`always @ (negedge tck_pad_i or negedge trstn_pad_i)`
430			`begin`
431			`if(trstn_pad_i == 0)`
432			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
433			`else if (test_logic_reset)`
434			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
435			`else if(update_ir)`
436			`latched_jtag_ir <=#1 jtag_ir;`
437			`end`
438
439			`/**********************************************************************************`
440			`* *`
441			`* End: jtag_ir *`
442			`* *`
443			`**********************************************************************************/`
444
445
446
447			`/**********************************************************************************`
448			`* *`
449			`* idcode logic *`
450			`* *`
451			`**********************************************************************************/`
452			`reg [31:0] idcode_reg;`
453			`wire idcode_tdo;`
454
455			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
456			`begin`
457			`if(trstn_pad_i == 0)`
458			idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
459			`else if (test_logic_reset)`
460			idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
461			`else if(idcode_select & capture_dr)`
462			idcode_reg <= #1 `IDCODE_VALUE;
463			`else if(idcode_select & shift_dr)`
464			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
465
466			`end`
467
468			`assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX`
469
470			`/**********************************************************************************`
471			`* *`
472			`* End: idcode logic *`
473			`* *`
474			`**********************************************************************************/`
475
476
477			`/**********************************************************************************`
478			`* *`
479			`* Bypass logic *`
480			`* *`
481			`**********************************************************************************/`
482			`wire bypassed_tdo;`
483			`reg bypass_reg; // This is a 1-bit register`
484
485			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
486			`begin`
487			`if (trstn_pad_i == 0)`
488			`bypass_reg <= #1 1'b0;`
489			`else if (test_logic_reset == 1)`
490			`bypass_reg <= #1 1'b0;`
491			`else if (bypass_select & capture_dr)`
492			`bypass_reg<=#1 1'b0;`
493			`else if(bypass_select & shift_dr)`
494			`bypass_reg<=#1 tdi_pad_i;`
495			`end`
496
497			`assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX`
498
499			`/**********************************************************************************`
500			`* *`
501			`* End: Bypass logic *`
502			`* *`
503			`**********************************************************************************/`
504
505
506			`/**********************************************************************************`
507			`* *`
508			`* Selecting active data register *`
509			`* *`
510			`**********************************************************************************/`
511			`always @ (latched_jtag_ir)`
512			`begin`
513			`extest_select = 1'b0;`
514			`sample_preload_select = 1'b0;`
515			`idcode_select = 1'b0;`
516			`mbist_select = 1'b0;`
517			`debug_select = 1'b0;`
518			`bypass_select = 1'b0;`
519
520			`case(latched_jtag_ir) /* synthesis parallel_case */`
521			`EXTEST: extest_select = 1'b1; // External test
522			`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
523			`IDCODE: idcode_select = 1'b1; // ID Code
524			`MBIST: mbist_select = 1'b1; // Mbist test
525			`DEBUG: debug_select = 1'b1; // Debug
526			`BYPASS: bypass_select = 1'b1; // BYPASS
527			`default: bypass_select = 1'b1; // BYPASS`
528			`endcase`
529			`end`
530
531
532			`/**********************************************************************************`
533			`* *`
534			`* Multiplexing TDO data *`
535			`* *`
536			`**********************************************************************************/`
537			`reg tdo_mux_out; // really just a wire`
538
539			`always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or`
540			`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or bypassed_tdo or`
541			`bs_chain_tdi_i)`
542			`begin`
543			`if(shift_ir)`
544			`tdo_mux_out = instruction_tdo;`
545			`else`
546			`begin`
547			`case(latched_jtag_ir) // synthesis parallel_case`
548			`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
549			`DEBUG: tdo_mux_out = debug_tdi_i; // Debug
550			`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdi_i; // Sampling/Preloading
551			`EXTEST: tdo_mux_out = bs_chain_tdi_i; // External test
552			`MBIST: tdo_mux_out = mbist_tdi_i; // Mbist test
553			`default: tdo_mux_out = bypassed_tdo; // BYPASS instruction`
554			`endcase`
555			`end`
556			`end`
557
558
559			`// TDO changes state at negative edge of TCK`
560			`always @ (negedge tck_pad_i)`
561			`begin`
562			`tdo_pad_o = tdo_mux_out;`
563			`end`
564
565
566			`// Tristate control for tdo_pad_o pin`
567			`always @ (posedge tck_pad_i)`
568			`begin`
569			`tdo_padoe_o <= #1 shift_ir \| shift_dr;`
570			`end`
571			`/**********************************************************************************`
572			`* *`
573			`* End: Multiplexing TDO data *`
574			`* *`
575			`**********************************************************************************/`
576
577			`endmodule`