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nyawn |
/* adv_dbg_commands.c -- JTAG protocol bridge between GDB and Advanced debug module.
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nyawn |
Copyright (C) 2008-2010 Nathan Yawn, nyawn@opencores.net
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14 |
nyawn |
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This file contains functions which perform high-level transactions
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on a JTAG chain and debug unit, such as setting a value in the TAP IR
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or doing a burst write through the wishbone module of the debug unit.
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It uses the protocol for the Advanced Debug Interface (adv_dbg_if).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h> // for malloc()
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#include <unistd.h> // for exit()
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nyawn |
#include <string.h> // for memcpy()
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nyawn |
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#include "chain_commands.h"
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#include "adv_dbg_commands.h" // hardware-specific defines for the debug module
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#include "cable_common.h" // low-level JTAG IO routines
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#include "errcodes.h"
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nyawn |
#include "utilities.h"
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nyawn |
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#define debug(...) //fprintf(stderr, __VA_ARGS__ )
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// How many '0' status bits to get during a burst read
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// before giving up
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#define MAX_READ_STATUS_WAIT 100
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// Currently selected internal register in each module
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// - cuts down on unnecessary transfers
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int current_reg_idx[DBG_MAX_MODULES];
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nyawn |
// Scratchpad I/O buffers
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static char *input_scratchpad = NULL;
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static char *output_scratchpad = NULL;
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static int input_scratchpad_size = 0;
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static int output_scratchpad_size = 0;
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nyawn |
// Prototypes for local functions
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uint32_t adbg_compute_crc(uint32_t crc_in, uint32_t data_in, int length_bits);
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////////////////////////////////////////////////////////////////////////
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// Helper functions
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uint32_t adbg_compute_crc(uint32_t crc_in, uint32_t data_in, int length_bits)
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{
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int i;
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unsigned int d, c;
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uint32_t crc_out = crc_in;
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for(i = 0; i < length_bits; i = i+1)
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{
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d = ((data_in >> i) & 0x1) ? 0xffffffff : 0;
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c = (crc_out & 0x1) ? 0xffffffff : 0;
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crc_out = crc_out >> 1;
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crc_out = crc_out ^ ((d ^ c) & ADBG_CRC_POLY);
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}
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return crc_out;
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}
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//////////////////////////////////////////////////////////////////
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// Functions which operate on the advanced debug unit
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/* Selects one of the modules in the debug unit (e.g. wishbone unit, CPU0, etc.)
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*/
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int adbg_select_module(int chain)
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{
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uint32_t data;
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int err = APP_ERR_NONE;
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if (current_chain == chain)
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return err;
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current_chain = -1;
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desired_chain = chain;
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// MSB of the data out must be set to 1, indicating a module select command
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data = chain | (1<<DBG_MODULE_SELECT_REG_SIZE);
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debug("select module %i\n", chain);
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err |= tap_set_shift_dr(); /* SHIFT_DR */
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/* write data, EXIT1_DR */
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err |= jtag_write_stream(&data, 3, 1); // When TMS is set (last parameter), DR length is also adjusted; EXIT1_DR
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// *** If 'valid module selected' feedback is ever added, test it here
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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current_chain = chain;
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if(err)
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printf("Error %s selecting active debug module\n", get_err_string(err));
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return err;
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}
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// Set the index of the desired register in the currently selected module
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// 1 bit module select command
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// 4 bits opcode
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// n bits index
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// Make sure the corrent module/chain is selected before calling this
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int adbg_select_ctrl_reg(unsigned long regidx)
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{
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uint32_t data;
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int index_len = 0;
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uint32_t opcode;
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int err = APP_ERR_NONE;
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if(err |= adbg_select_module(desired_chain))
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return err;
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debug("selreg %ld\n", regidx);
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// If this reg is already selected, don't do a JTAG transaction
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if(current_reg_idx[current_chain] == regidx)
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return APP_ERR_NONE;
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switch(current_chain) {
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case DC_WISHBONE:
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index_len = DBG_WB_REG_SEL_LEN;
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opcode = DBG_WB_CMD_IREG_SEL;
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break;
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case DC_CPU0:
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index_len = DBG_CPU0_REG_SEL_LEN;
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opcode = DBG_CPU0_CMD_IREG_SEL;
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break;
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case DC_CPU1:
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index_len = DBG_CPU1_REG_SEL_LEN;
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opcode = DBG_CPU1_CMD_IREG_SEL;
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break;
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default:
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printf("ERROR! Illegal debug chain selected while selecting control register!\n");
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return 1;
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}
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// Set up the data.
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data = (opcode & ~(1<<DBG_WB_OPCODE_LEN)) << index_len; // MSB must be 0 to access modules
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data |= regidx;
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debug("Selreg: data is 0x%lX (opcode = 0x%lX)\n", data,opcode);
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err |= tap_set_shift_dr(); /* SHIFT_DR */
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/* write data, EXIT1_DR */
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err |= jtag_write_stream(&data, 5+index_len, 1);
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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/* reset retry counter */
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retry_ok();
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current_reg_idx[current_chain] = regidx;
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if(err)
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printf("Error %s selecting control register %ld in module %i\n", get_err_string(err), regidx, current_chain);
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return err;
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}
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/* Sends out a generic command to the selected debug unit module, LSB first. Fields are:
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* MSB: 1-bit module command
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* 4-bit opcode
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* m-bit register index
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* n-bit data (LSB)
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* Note that in the data array, the LSB of data[0] will be sent first,
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* (and become the LSB of the command)
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* up through the MSB of data[0], then the LSB of data[1], etc.
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*/
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int adbg_ctrl_write(unsigned long regidx, uint32_t *cmd_data, int length_bits) {
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uint32_t data;
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int index_len = 0;
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uint32_t opcode;
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int err = APP_ERR_NONE;
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if(err |= adbg_select_module(desired_chain))
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return err;
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debug("ctrl wr idx %ld dat 0x%lX\n", regidx, cmd_data[0]);
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switch(current_chain) {
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case DC_WISHBONE:
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index_len = DBG_WB_REG_SEL_LEN;
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opcode = DBG_WB_CMD_IREG_WR;
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break;
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case DC_CPU0:
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index_len = DBG_CPU0_REG_SEL_LEN;
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opcode = DBG_CPU0_CMD_IREG_WR;
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break;
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case DC_CPU1:
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index_len = DBG_CPU1_REG_SEL_LEN;
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opcode = DBG_CPU1_CMD_IREG_WR;
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break;
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default:
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printf("ERROR! Illegal debug chain selected (%i) while doing control write!\n", current_chain);
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return 1;
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}
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// Set up the data. We cheat a bit here, by using 2 stream writes.
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data = (opcode & ~(1<<DBG_WB_OPCODE_LEN)) << index_len; // MSB must be 0 to access modules
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data |= regidx;
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err |= tap_set_shift_dr(); /* SHIFT_DR */
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/* write data, EXIT1_DR */
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err |= jtag_write_stream(cmd_data, length_bits, 0);
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err |= jtag_write_stream(&data, 5+index_len, 1);
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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/* reset retry counter */
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retry_ok();
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current_reg_idx[current_chain] = regidx;
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if(err)
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printf("Error %s writing control register %ld in module %i\n", get_err_string(err), regidx, current_chain);
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return err;
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}
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/* reads control register (internal to the debug unit)
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* Currently only 1 register in the CPU module, so no register select
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*/
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int adbg_ctrl_read(unsigned long regidx, uint32_t *data, int databits) {
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uint32_t outdata[4] = {0,0,0,0}; // *** We assume no more than 128 databits
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int opcode;
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int opcode_len;
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int err = APP_ERR_NONE;
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248 |
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if(err |= adbg_select_module(desired_chain))
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return err;
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if(err |= adbg_select_ctrl_reg(regidx))
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return err;
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debug("ctrl rd idx %ld\n", regidx);
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256 |
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// There is no 'read' command, We write a NOP to read
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switch(current_chain) {
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case DC_WISHBONE:
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opcode = DBG_WB_CMD_NOP;
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opcode_len = DBG_WB_OPCODE_LEN;
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break;
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case DC_CPU0:
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opcode = DBG_CPU0_CMD_NOP;
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opcode_len = DBG_CPU0_OPCODE_LEN;
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break;
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case DC_CPU1:
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opcode = DBG_CPU1_CMD_NOP;
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opcode_len = DBG_CPU1_OPCODE_LEN;
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break;
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271 |
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default:
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printf("ERROR! Illegal debug chain selected while doing control read!\n");
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273 |
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return 1;
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274 |
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}
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275 |
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276 |
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outdata[0] = opcode & ~(0x1 << opcode_len); // Zero MSB = op for module, not top-level debug unit
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277 |
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278 |
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err |= tap_set_shift_dr(); /* SHIFT_DR */
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279 |
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280 |
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// We cheat a bit here by using two stream operations.
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281 |
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// First we burn the postfix bits and read the desired data, then we push a NOP
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282 |
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// into position through the prefix bits. We may be able to combine the two and save
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283 |
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// some cycles, but that way leads to madness.
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284 |
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err |= jtag_read_write_stream(outdata, data, databits, 1, 0); // adjust for prefix bits
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285 |
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err |= jtag_write_stream(outdata, opcode_len+1, 1); // adjust for postfix bits, Set TMS: EXIT1_DR
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286 |
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287 |
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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288 |
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289 |
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/* reset retry counter */
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290 |
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retry_ok();
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291 |
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292 |
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if(err)
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293 |
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printf("Error %s reading control register %ld in module %i\n", get_err_string(err), regidx, current_chain);
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294 |
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295 |
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return err;
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296 |
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}
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297 |
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298 |
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299 |
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/* sends out a burst command to the selected module in the debug unit (MSB to LSB):
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300 |
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* 1-bit module command
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301 |
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* 4-bit opcode
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302 |
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* 32-bit address
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303 |
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* 16-bit length (of the burst, in words)
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304 |
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*/
|
305 |
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int adbg_burst_command(unsigned int opcode, unsigned long address, int length_words) {
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306 |
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uint32_t data[2];
|
307 |
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int err = APP_ERR_NONE;
|
308 |
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|
309 |
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if(err |= adbg_select_module(desired_chain))
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310 |
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return err;
|
311 |
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|
312 |
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debug("burst op %i adr 0x%lX len %i\n", opcode, address, length_words);
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313 |
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314 |
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// Set up the data
|
315 |
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data[0] = length_words | (address << 16);
|
316 |
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data[1] = ((address >> 16) | ((opcode & 0xf) << 16)) & ~(0x1<<20); // MSB must be 0 to access modules
|
317 |
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|
318 |
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err |= tap_set_shift_dr(); /* SHIFT_DR */
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319 |
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|
320 |
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/* write data, EXIT1_DR */
|
321 |
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err |= jtag_write_stream(data, 53, 1); // When TMS is set (last parameter), DR length is also adjusted; EXIT1_DR
|
322 |
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|
323 |
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
|
324 |
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|
325 |
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/* reset retry counter */
|
326 |
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retry_ok();
|
327 |
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|
328 |
|
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if(err)
|
329 |
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printf("Error %s sending burst command to module %i\n", get_err_string(err), desired_chain);
|
330 |
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|
331 |
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return err;
|
332 |
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}
|
333 |
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|
334 |
|
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// Set up and execute a burst read from a contiguous block of addresses.
|
335 |
|
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// Note that there is a minor weakness in the CRC algorithm in case of retries:
|
336 |
|
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// the CRC is only checked for the final burst read. Thus, if errors/partial retries
|
337 |
|
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// break up a transfer into multiple bursts, only the last burst will be CRC protected.
|
338 |
|
|
#define MAX_BUS_ERRORS 10
|
339 |
|
|
int adbg_wb_burst_read(int word_size_bytes, int word_count, unsigned long start_address, void *data)
|
340 |
|
|
{
|
341 |
|
|
unsigned char opcode;
|
342 |
|
|
uint8_t status;
|
343 |
|
|
unsigned long instream;
|
344 |
|
|
int i, j;
|
345 |
|
|
uint32_t crc_calc;
|
346 |
|
|
uint32_t crc_read;
|
347 |
|
|
unsigned char word_size_bits;
|
348 |
|
|
uint32_t out_data = 0;
|
349 |
51 |
nyawn |
uint32_t in_data = 0;
|
350 |
14 |
nyawn |
unsigned long addr;
|
351 |
|
|
uint32_t err_data[2];
|
352 |
|
|
int bus_error_retries = 0;
|
353 |
|
|
int err = APP_ERR_NONE;
|
354 |
|
|
|
355 |
51 |
nyawn |
// Silence GCC
|
356 |
|
|
(void)in_data;
|
357 |
|
|
(void)out_data;
|
358 |
|
|
|
359 |
55 |
nyawn |
debug("Doing burst read, word size %d, word count %d, start address 0x%lX\n", word_size_bytes, word_count, start_address);
|
360 |
14 |
nyawn |
|
361 |
|
|
if(word_count <= 0) {
|
362 |
|
|
debug("Ignoring illegal read burst length (%d)\n", word_count);
|
363 |
|
|
return 0;
|
364 |
|
|
}
|
365 |
|
|
|
366 |
|
|
instream = 0;
|
367 |
|
|
word_size_bits = word_size_bytes << 3;
|
368 |
|
|
|
369 |
|
|
// Select the appropriate opcode
|
370 |
|
|
switch(current_chain) {
|
371 |
|
|
case DC_WISHBONE:
|
372 |
|
|
if (word_size_bytes == 1) opcode = DBG_WB_CMD_BREAD8;
|
373 |
|
|
else if(word_size_bytes == 2) opcode = DBG_WB_CMD_BREAD16;
|
374 |
|
|
else if(word_size_bytes == 4) opcode = DBG_WB_CMD_BREAD32;
|
375 |
|
|
else {
|
376 |
55 |
nyawn |
printf("Tried burst read with invalid word size (%0x), defaulting to 4-byte words\n", word_size_bytes);
|
377 |
14 |
nyawn |
opcode = DBG_WB_CMD_BREAD32;
|
378 |
|
|
}
|
379 |
|
|
break;
|
380 |
|
|
case DC_CPU0:
|
381 |
|
|
if(word_size_bytes == 4) opcode = DBG_CPU0_CMD_BREAD32;
|
382 |
|
|
else {
|
383 |
55 |
nyawn |
printf("Tried burst read with invalid word size (%0x), defaulting to 4-byte words\n", word_size_bytes);
|
384 |
14 |
nyawn |
opcode = DBG_CPU0_CMD_BREAD32;
|
385 |
|
|
}
|
386 |
|
|
break;
|
387 |
|
|
case DC_CPU1:
|
388 |
|
|
if(word_size_bytes == 4) opcode = DBG_CPU1_CMD_BREAD32;
|
389 |
|
|
else {
|
390 |
55 |
nyawn |
printf("Tried burst read with invalid word size (%0x), defaulting to 4-byte words\n", word_size_bytes);
|
391 |
14 |
nyawn |
opcode = DBG_CPU0_CMD_BREAD32;
|
392 |
|
|
}
|
393 |
|
|
break;
|
394 |
|
|
default:
|
395 |
|
|
printf("ERROR! Illegal debug chain selected while doing burst read!\n");
|
396 |
|
|
return 1;
|
397 |
|
|
}
|
398 |
|
|
|
399 |
|
|
wb_burst_read_retry_full:
|
400 |
|
|
i = 0;
|
401 |
|
|
addr = start_address;
|
402 |
|
|
wb_burst_read_retry_partial:
|
403 |
|
|
crc_calc = 0xffffffff;
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
// Send the BURST READ command, returns TAP to idle state
|
407 |
|
|
if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
|
408 |
|
|
return err;
|
409 |
|
|
|
410 |
32 |
nyawn |
// This is a kludge to work around oddities in the Xilinx BSCAN_* devices, and the
|
411 |
14 |
nyawn |
// adv_dbg_if state machine. The debug FSM needs 1 TCK between UPDATE_DR above, and
|
412 |
|
|
// the CAPTURE_DR below, and the BSCAN_* won't provide it. So, we force it, by putting the TAP
|
413 |
|
|
// in BYPASS, which makes the debug_select line inactive, which is AND'ed with the TCK line (in the xilinx_internal_jtag module),
|
414 |
|
|
// which forces it low. Then we re-enable USER1/debug_select to make TCK high. One TCK
|
415 |
|
|
// event, the hard way.
|
416 |
|
|
if(global_xilinx_bscan) {
|
417 |
|
|
err |= tap_set_ir(0xFFFFFFFF);
|
418 |
|
|
err |= tap_enable_debug_module();
|
419 |
|
|
}
|
420 |
|
|
|
421 |
|
|
// Get us back to shift_dr mode to read a burst
|
422 |
|
|
err |= tap_set_shift_dr();
|
423 |
|
|
|
424 |
|
|
// We do not adjust for the DR length here. BYPASS regs are loaded with 0,
|
425 |
|
|
// and the debug unit waits for a '1' status bit before beginning to read data.
|
426 |
32 |
nyawn |
|
427 |
|
|
#ifdef ADBG_OPT_HISPEED
|
428 |
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
429 |
|
|
status = 0;
|
430 |
|
|
j = 0;
|
431 |
|
|
while(!status) { // Status indicates whether there is a word available to read. Wait until it returns true.
|
432 |
|
|
err |= jtag_read_write_bit(0, &status);
|
433 |
|
|
j++;
|
434 |
|
|
// If max count exceeded, retry
|
435 |
|
|
if(j > MAX_READ_STATUS_WAIT) {
|
436 |
|
|
printf("Burst read timed out.\n");
|
437 |
|
|
if(!retry_do()) {
|
438 |
|
|
printf("Retry count exceeded in burst read!\n");
|
439 |
|
|
return err|APP_ERR_MAX_RETRY;
|
440 |
|
|
}
|
441 |
|
|
err = APP_ERR_NONE; // on retry, errors cleared
|
442 |
|
|
goto wb_burst_read_retry_full;
|
443 |
|
|
}
|
444 |
|
|
}
|
445 |
|
|
|
446 |
|
|
// Check we have enough space for the (zero) output data
|
447 |
42 |
nyawn |
int total_size_bytes = (word_count*word_size_bytes)+4;
|
448 |
|
|
err |= check_buffer_size(&input_scratchpad, &input_scratchpad_size, total_size_bytes);
|
449 |
|
|
err |= check_buffer_size(&output_scratchpad, &output_scratchpad_size, total_size_bytes);
|
450 |
|
|
if(err != APP_ERR_NONE) return err;
|
451 |
|
|
memset(output_scratchpad, 0, total_size_bytes);
|
452 |
32 |
nyawn |
|
453 |
42 |
nyawn |
// Get the data in one shot, including the CRC. This requires two memcpy(), which take time,
|
454 |
|
|
// but it's still faster than an added USB transaction (assuming a USB cable).
|
455 |
|
|
err |= jtag_read_write_stream((uint32_t *)output_scratchpad, (uint32_t *)input_scratchpad, (total_size_bytes*8), 0, 1);
|
456 |
|
|
memcpy(data, input_scratchpad, (word_count*word_size_bytes));
|
457 |
|
|
memcpy(&crc_read, &input_scratchpad[(word_count*word_size_bytes)], 4);
|
458 |
32 |
nyawn |
for(i = 0; i < (word_count*word_size_bytes); i++)
|
459 |
|
|
{
|
460 |
|
|
crc_calc = adbg_compute_crc(crc_calc, ((uint8_t *)data)[i], 8);
|
461 |
|
|
}
|
462 |
42 |
nyawn |
|
463 |
32 |
nyawn |
#else
|
464 |
|
|
|
465 |
14 |
nyawn |
// Repeat for each word: wait until ready = 1, then read word_size_bits bits.
|
466 |
|
|
for(; i < word_count; i++)
|
467 |
|
|
{
|
468 |
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
469 |
|
|
status = 0;
|
470 |
|
|
j = 0;
|
471 |
|
|
while(!status) { // Status indicates whether there is a word available to read. Wait until it returns true.
|
472 |
|
|
err |= jtag_read_write_bit(0, &status);
|
473 |
|
|
j++;
|
474 |
|
|
// If max count exceeded, retry starting with the failure address
|
475 |
|
|
if(j > MAX_READ_STATUS_WAIT) {
|
476 |
|
|
printf("Burst read timed out.\n");
|
477 |
|
|
if(!retry_do()) {
|
478 |
|
|
printf("Retry count exceeded in burst read!\n");
|
479 |
|
|
return err|APP_ERR_MAX_RETRY;
|
480 |
|
|
}
|
481 |
|
|
err = APP_ERR_NONE; // on retry, errors cleared
|
482 |
|
|
addr = start_address + (i*word_size_bytes);
|
483 |
|
|
goto wb_burst_read_retry_partial;
|
484 |
|
|
}
|
485 |
|
|
}
|
486 |
|
|
|
487 |
|
|
if(j > 1) { // It's actually normal for the first read of a burst to take 2 tries, even with a fast WB clock - 3 with a Xilinx BSCAN
|
488 |
|
|
debug("Took %0d tries before good status bit during burst read", j);
|
489 |
|
|
}
|
490 |
|
|
|
491 |
|
|
// Get one word of data
|
492 |
|
|
err |= jtag_read_write_stream(&out_data, &in_data, word_size_bits, 0, 0);
|
493 |
|
|
debug("Read 0x%0lx", in_data);
|
494 |
|
|
|
495 |
|
|
if(err) { // Break and retry as soon as possible on error
|
496 |
|
|
printf("Error %s during burst read.\n", get_err_string(err));
|
497 |
|
|
if(!retry_do()) {
|
498 |
|
|
printf("Retry count exceeded in burst read!\n");
|
499 |
|
|
return err|APP_ERR_MAX_RETRY;
|
500 |
|
|
}
|
501 |
|
|
err = APP_ERR_NONE; // on retry, errors cleared
|
502 |
|
|
addr = start_address + (i*word_size_bytes);
|
503 |
|
|
goto wb_burst_read_retry_partial;
|
504 |
|
|
}
|
505 |
|
|
|
506 |
|
|
crc_calc = adbg_compute_crc(crc_calc, in_data, word_size_bits);
|
507 |
|
|
|
508 |
|
|
if(word_size_bytes == 1) ((unsigned char *)data)[i] = in_data & 0xFF;
|
509 |
|
|
else if(word_size_bytes == 2) ((unsigned short *)data)[i] = in_data & 0xFFFF;
|
510 |
|
|
else ((unsigned long *)data)[i] = in_data;
|
511 |
|
|
}
|
512 |
|
|
|
513 |
|
|
// All bus data was read. Read the data CRC from the debug module.
|
514 |
|
|
err |= jtag_read_write_stream(&out_data, &crc_read, 32, 0, 1);
|
515 |
|
|
|
516 |
42 |
nyawn |
#endif
|
517 |
|
|
|
518 |
14 |
nyawn |
err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
|
519 |
|
|
|
520 |
|
|
if(crc_calc != crc_read) {
|
521 |
|
|
printf("CRC ERROR! Computed 0x%x, read CRC 0x%x\n", crc_calc, crc_read);
|
522 |
|
|
if(!retry_do()) {
|
523 |
|
|
printf("Retry count exceeded! Abort!\n\n");
|
524 |
|
|
return err|APP_ERR_CRC;
|
525 |
|
|
}
|
526 |
|
|
goto wb_burst_read_retry_full;
|
527 |
|
|
}
|
528 |
55 |
nyawn |
else debug("CRC OK!\n");
|
529 |
14 |
nyawn |
|
530 |
|
|
|
531 |
|
|
// Now, read the error register, and retry/recompute as necessary.
|
532 |
|
|
if(current_chain == DC_WISHBONE)
|
533 |
|
|
{
|
534 |
|
|
err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 1); // First, just get 1 bit...read address only if necessary,
|
535 |
|
|
if(err_data[0] & 0x1) { // Then we have a problem.
|
536 |
|
|
err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 33);
|
537 |
|
|
addr = (err_data[0] >> 1) | (err_data[1] << 31);
|
538 |
|
|
i = (addr - start_address) / word_size_bytes;
|
539 |
|
|
printf("ERROR! WB bus error during burst read, address 0x%lX (index 0x%X), retrying!\n", addr, i);
|
540 |
|
|
bus_error_retries++;
|
541 |
|
|
if(bus_error_retries > MAX_BUS_ERRORS) {
|
542 |
|
|
printf("Max WB bus errors reached during burst read\n");
|
543 |
|
|
return err|APP_ERR_MAX_BUS_ERR;
|
544 |
|
|
}
|
545 |
|
|
// Don't call retry_do(), a JTAG reset won't help a WB bus error
|
546 |
|
|
err_data[0] = 1;
|
547 |
|
|
err |= adbg_ctrl_write(DBG_WB_REG_ERROR, err_data, 1); // Write 1 bit, to reset the error register,
|
548 |
|
|
goto wb_burst_read_retry_partial;
|
549 |
|
|
}
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
retry_ok();
|
553 |
|
|
return err;
|
554 |
|
|
}
|
555 |
|
|
|
556 |
|
|
// Set up and execute a burst write to a contiguous set of addresses
|
557 |
|
|
int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address)
|
558 |
|
|
{
|
559 |
|
|
unsigned char opcode;
|
560 |
|
|
uint32_t datawords[2] = {0,0};
|
561 |
|
|
int i;
|
562 |
|
|
uint32_t crc_calc;
|
563 |
|
|
uint32_t crc_match;
|
564 |
|
|
unsigned int word_size_bits;
|
565 |
|
|
unsigned long addr;
|
566 |
|
|
int bus_error_retries = 0;
|
567 |
|
|
uint32_t err_data[2];
|
568 |
|
|
int loopct, successes;
|
569 |
32 |
nyawn |
#ifndef ADBG_OPT_HISPEED
|
570 |
|
|
uint8_t status;
|
571 |
|
|
uint32_t statuswords[2] = {0,0};
|
572 |
|
|
int first_status_loop = 1;
|
573 |
|
|
#endif
|
574 |
14 |
nyawn |
int err = APP_ERR_NONE;
|
575 |
|
|
|
576 |
32 |
nyawn |
debug("Doing burst write, word size %d, word count %d, start address 0x%lx\n", word_size_bytes, word_count, start_address);
|
577 |
14 |
nyawn |
word_size_bits = word_size_bytes << 3;
|
578 |
|
|
|
579 |
|
|
if(word_count <= 0) {
|
580 |
|
|
printf("Ignoring illegal burst write size (%d)\n", word_count);
|
581 |
|
|
return 0;
|
582 |
|
|
}
|
583 |
|
|
|
584 |
|
|
// Select the appropriate opcode
|
585 |
|
|
switch(current_chain) {
|
586 |
|
|
case DC_WISHBONE:
|
587 |
|
|
if (word_size_bytes == 1) opcode = DBG_WB_CMD_BWRITE8;
|
588 |
|
|
else if(word_size_bytes == 2) opcode = DBG_WB_CMD_BWRITE16;
|
589 |
|
|
else if(word_size_bytes == 4) opcode = DBG_WB_CMD_BWRITE32;
|
590 |
|
|
else {
|
591 |
|
|
printf("Tried WB burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
592 |
|
|
opcode = DBG_WB_CMD_BWRITE32;
|
593 |
|
|
}
|
594 |
|
|
break;
|
595 |
|
|
case DC_CPU0:
|
596 |
|
|
if(word_size_bytes == 4) opcode = DBG_CPU0_CMD_BWRITE32;
|
597 |
|
|
else {
|
598 |
|
|
printf("Tried CPU0 burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
599 |
|
|
opcode = DBG_CPU0_CMD_BWRITE32;
|
600 |
|
|
}
|
601 |
|
|
break;
|
602 |
|
|
case DC_CPU1:
|
603 |
|
|
if(word_size_bytes == 4) opcode = DBG_CPU1_CMD_BWRITE32;
|
604 |
|
|
else {
|
605 |
|
|
printf("Tried CPU1 burst write with invalid word size (%0X), defaulting to 4-byte words", word_size_bytes);
|
606 |
|
|
opcode = DBG_CPU0_CMD_BWRITE32;
|
607 |
|
|
}
|
608 |
|
|
break;
|
609 |
|
|
default:
|
610 |
|
|
printf("ERROR! Illegal debug chain selected while doing burst WRITE!\n");
|
611 |
|
|
return 1;
|
612 |
|
|
}
|
613 |
|
|
|
614 |
32 |
nyawn |
#ifndef ADBG_OPT_HISPEED
|
615 |
14 |
nyawn |
// Compute which loop iteration in which to expect the first status bit
|
616 |
|
|
first_status_loop = 1 + ((global_DR_prefix_bits + global_DR_postfix_bits)/(word_size_bits+1));
|
617 |
32 |
nyawn |
#endif
|
618 |
14 |
nyawn |
|
619 |
|
|
wb_burst_write_retry_full:
|
620 |
|
|
i = 0;
|
621 |
|
|
addr = start_address;
|
622 |
|
|
wb_burst_write_retry_partial:
|
623 |
|
|
crc_calc = 0xffffffff;
|
624 |
|
|
successes = 0;
|
625 |
|
|
|
626 |
|
|
|
627 |
|
|
// Send burst command, return to idle state
|
628 |
|
|
if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
|
629 |
|
|
return err;
|
630 |
|
|
|
631 |
|
|
// Get us back to shift_dr mode to write a burst
|
632 |
|
|
err |= tap_set_shift_dr();
|
633 |
|
|
|
634 |
|
|
// Write a start bit (a 1) so it knows when to start counting
|
635 |
|
|
err |= jtag_write_bit(TDO);
|
636 |
|
|
|
637 |
32 |
nyawn |
#ifdef ADBG_OPT_HISPEED
|
638 |
|
|
// If compiled for "hi-speed" mode, we don't read a status bit after every
|
639 |
|
|
// word written. This saves a lot of complication!
|
640 |
42 |
nyawn |
// We send the CRC at the same time, so we have to compute it first.
|
641 |
|
|
for(loopct = 0; loopct < word_count; loopct++) {
|
642 |
|
|
if(word_size_bytes == 4) datawords[0] = ((unsigned long *)data)[loopct];
|
643 |
|
|
else if(word_size_bytes == 2) datawords[0] = ((unsigned short *)data)[loopct];
|
644 |
|
|
else datawords[0] = ((unsigned char *)data)[loopct];
|
645 |
|
|
crc_calc = adbg_compute_crc(crc_calc, datawords[0], word_size_bits);
|
646 |
|
|
}
|
647 |
32 |
nyawn |
|
648 |
42 |
nyawn |
int total_size_bytes = (word_count * word_size_bytes) + 4;
|
649 |
|
|
err |= check_buffer_size(&output_scratchpad, &output_scratchpad_size, total_size_bytes);
|
650 |
|
|
if(err != APP_ERR_NONE) return err;
|
651 |
|
|
|
652 |
|
|
memcpy(output_scratchpad, data, (word_count * word_size_bytes));
|
653 |
|
|
memcpy(&output_scratchpad[(word_count*word_size_bytes)], &crc_calc, 4);
|
654 |
|
|
|
655 |
|
|
err |= jtag_write_stream((uint32_t *) output_scratchpad, total_size_bytes*8, 0); // Write data
|
656 |
|
|
|
657 |
|
|
#else
|
658 |
|
|
|
659 |
|
|
// Or, repeat...
|
660 |
14 |
nyawn |
for(loopct = 0; i < word_count; i++,loopct++) // loopct only used to check status...
|
661 |
|
|
{
|
662 |
|
|
// Write word_size_bytes*8 bits, then get 1 status bit
|
663 |
|
|
if(word_size_bytes == 4) datawords[0] = ((unsigned long *)data)[i];
|
664 |
|
|
else if(word_size_bytes == 2) datawords[0] = ((unsigned short *)data)[i];
|
665 |
|
|
else datawords[0] = ((unsigned char *)data)[i];
|
666 |
|
|
|
667 |
|
|
crc_calc = adbg_compute_crc(crc_calc, datawords[0], word_size_bits);
|
668 |
|
|
|
669 |
|
|
// This is an optimization
|
670 |
|
|
if((global_DR_prefix_bits + global_DR_postfix_bits) == 0) {
|
671 |
32 |
nyawn |
//#endif
|
672 |
14 |
nyawn |
err |= jtag_write_stream(datawords, word_size_bits, 0); // Write data
|
673 |
32 |
nyawn |
//#ifndef ADBG_OPT_HISPEED
|
674 |
14 |
nyawn |
err |= jtag_read_write_bit(0, &status); // Read status bit
|
675 |
|
|
if(!status) {
|
676 |
|
|
addr = start_address + (i*word_size_bytes);
|
677 |
|
|
printf("Write before bus ready, retrying (idx %i, addr 0x%08lX).\n", i, addr);
|
678 |
|
|
if(!retry_do()) { printf("Retry count exceeded! Abort!\n\n"); exit(1);}
|
679 |
|
|
// Don't bother going to TAP idle state, we're about to reset the TAP
|
680 |
|
|
goto wb_burst_write_retry_partial;
|
681 |
|
|
}
|
682 |
|
|
}
|
683 |
|
|
else { // This is slower (for a USB cable anyway), because a read takes 1 more USB transaction than a write.
|
684 |
|
|
err |= jtag_read_write_stream(datawords, statuswords, word_size_bits+1, 0, 0);
|
685 |
|
|
debug("St. 0x%08lX 0x%08lX\n", statuswords[0], statuswords[1]);
|
686 |
|
|
status = (statuswords[0] || statuswords[1]);
|
687 |
|
|
if(loopct > first_status_loop) {
|
688 |
|
|
if(status) successes++;
|
689 |
|
|
else {
|
690 |
|
|
i = successes;
|
691 |
|
|
addr = start_address + (i*word_size_bytes);
|
692 |
|
|
printf("Write before bus ready, retrying (idx %i, addr 0x%08lX).\n", i, addr);
|
693 |
|
|
if(!retry_do()) { printf("Retry count exceeded! Abort!\n\n"); exit(1);}
|
694 |
|
|
// Don't bother going to TAP idle state, we're about to reset the TAP
|
695 |
|
|
goto wb_burst_write_retry_partial;
|
696 |
|
|
}
|
697 |
|
|
}
|
698 |
|
|
}
|
699 |
|
|
|
700 |
|
|
if(err) {
|
701 |
32 |
nyawn |
printf("Error %s during burst write, retrying.\n", get_err_string(err));
|
702 |
14 |
nyawn |
if(!retry_do()) {
|
703 |
|
|
printf("Retry count exceeded!\n");
|
704 |
|
|
return err|APP_ERR_MAX_RETRY;
|
705 |
|
|
}
|
706 |
|
|
err = APP_ERR_NONE;
|
707 |
|
|
addr = start_address + (i*word_size_bytes);
|
708 |
|
|
// Don't bother going to TAP idle state, we're about to reset the TAP
|
709 |
|
|
goto wb_burst_write_retry_partial;
|
710 |
|
|
}
|
711 |
|
|
|
712 |
|
|
debug("Wrote 0x%0lx", datawords[0]);
|
713 |
|
|
}
|
714 |
|
|
|
715 |
32 |
nyawn |
// *** If this is a multi-device chain (and we're not in hi-speed mode), at least one status bit will be lost.
|
716 |
14 |
nyawn |
// *** If we want to check for it, we'd have to look while sending the CRC, and
|
717 |
|
|
// *** maybe while burning bits to get the match bit. So, for now, there is a
|
718 |
|
|
// *** hole here.
|
719 |
|
|
|
720 |
|
|
// Done sending data, Send the CRC we computed
|
721 |
|
|
err |= jtag_write_stream(&crc_calc, 32, 0);
|
722 |
42 |
nyawn |
|
723 |
|
|
#endif
|
724 |
|
|
|
725 |
14 |
nyawn |
for(i = 0; i < global_DR_prefix_bits; i++) // Push the CRC data all the way to the debug unit
|
726 |
|
|
err |= jtag_write_bit(0); // Can't do this with a stream command without setting TMS on the last bit
|
727 |
|
|
|
728 |
|
|
// Read the 'CRC match' bit, and go to exit1_dr
|
729 |
|
|
// May need to adjust for other devices in chain!
|
730 |
|
|
datawords[0] = 0;
|
731 |
|
|
err |= jtag_read_write_stream(datawords, &crc_match, 1, 1, 0); // set 'adjust' to pull match bit all the way in
|
732 |
|
|
// But don't set TMS above, that would shift prefix bits (again), wasting time.
|
733 |
|
|
err |= jtag_write_bit(TMS); // exit1_dr
|
734 |
|
|
err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
|
735 |
|
|
|
736 |
|
|
if(!crc_match) {
|
737 |
|
|
printf("CRC ERROR! match bit after write is %i (computed CRC 0x%x)", crc_match, crc_calc);
|
738 |
|
|
if(!retry_do()) { printf("Retry count exceeded! Abort!\n\n"); exit(1);}
|
739 |
|
|
goto wb_burst_write_retry_full;
|
740 |
|
|
}
|
741 |
55 |
nyawn |
else debug("CRC OK!\n");
|
742 |
14 |
nyawn |
|
743 |
|
|
|
744 |
|
|
// Now, read the error register and retry/recompute as needed
|
745 |
|
|
if (current_chain == DC_WISHBONE)
|
746 |
|
|
{
|
747 |
|
|
err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 1); // First, just get 1 bit...read address only if necessary
|
748 |
|
|
if(err_data[0] & 0x1) { // Then we have a problem.
|
749 |
|
|
err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 33);
|
750 |
|
|
addr = (err_data[0] >> 1) | (err_data[1] << 31);
|
751 |
|
|
i = (addr - start_address) / word_size_bytes;
|
752 |
|
|
printf("ERROR! WB bus error during burst write, address 0x%lX (index 0x%X), retrying!\n", addr, i);
|
753 |
|
|
bus_error_retries++;
|
754 |
|
|
if(bus_error_retries > MAX_BUS_ERRORS) {
|
755 |
|
|
printf("Max WB bus errors reached!\n");
|
756 |
|
|
return err|APP_ERR_MAX_BUS_ERR;
|
757 |
|
|
}
|
758 |
|
|
// Don't call retry_do(), a JTAG reset won't help a WB bus error
|
759 |
|
|
err |= adbg_ctrl_write(DBG_WB_REG_ERROR, err_data, 1); // Write 1 bit, to reset the error register.
|
760 |
|
|
goto wb_burst_write_retry_partial;
|
761 |
|
|
}
|
762 |
|
|
}
|
763 |
|
|
|
764 |
|
|
retry_ok();
|
765 |
|
|
return err;
|
766 |
|
|
}
|
767 |
42 |
nyawn |
|
768 |
|
|
/*--------------------------------------------------------------------------------------------*/
|
769 |
|
|
|
770 |
|
|
// This does a simultaneous read/write to the JTAG serial port. It will send/receive at most 8 bytes,
|
771 |
|
|
// so data_received must be at least 8 bytes long. It is not guaranteed that all data (or any data)
|
772 |
|
|
// will be sent. On return, bytes_to_send will be set to the number of bytes actually senet.
|
773 |
|
|
|
774 |
|
|
int adbg_jsp_transact(unsigned int *bytes_to_send, const char *data_to_send, unsigned int *bytes_received, char *data_received)
|
775 |
|
|
{
|
776 |
|
|
int err = APP_ERR_NONE;
|
777 |
|
|
unsigned int xmitsize;
|
778 |
|
|
char outdata[10]; // These must 10 bytes: 1 for counts, 8 for data, and 1 (possible) start and end bits
|
779 |
|
|
char indata[10];
|
780 |
|
|
unsigned char stopbit = 0, startbit = 0, wrapbit;
|
781 |
|
|
int bytes_free;
|
782 |
|
|
int i;
|
783 |
|
|
|
784 |
|
|
if(*bytes_to_send > 8)
|
785 |
|
|
xmitsize = 8;
|
786 |
|
|
else
|
787 |
|
|
xmitsize = *bytes_to_send;
|
788 |
|
|
|
789 |
|
|
if(err |= adbg_select_module(desired_chain))
|
790 |
|
|
return err;
|
791 |
|
|
|
792 |
|
|
// Put us in shift_dr mode
|
793 |
|
|
err |= tap_set_shift_dr();
|
794 |
|
|
|
795 |
|
|
// There are two independant compile-time options here, making four different ways to do this transaction.
|
796 |
|
|
// If OPTIMIZE_FOR_USB is not defined, then one byte will be transacted to get the 'bytes available' and
|
797 |
|
|
// 'bytes free' counts, then the minimum number of bytes will be transacted to get all available bytes
|
798 |
|
|
// and put as many bytes as possible. If OPTIMIZE_FOR_USB is defined, then 9 bytes will always be transacted,
|
799 |
|
|
// the JSP will ignore extras, and user code will have to check to see how many bytes were written.
|
800 |
|
|
//
|
801 |
|
|
// if ENABLE_JSP_MULTI is enabled, then a '1' bit will be pre-pended to the data being sent (before the 'count'
|
802 |
|
|
// byte). This is for compatibility with multi-device JTAG chains.
|
803 |
|
|
|
804 |
|
|
#ifdef OPTIMIZE_JSP_FOR_USB
|
805 |
|
|
|
806 |
|
|
// Simplest case: do everything in 1 burst transaction
|
807 |
|
|
memset(outdata, 0, 10); // Clear to act as 'stopbits'. [8] may be overwritten in the following memcpy().
|
808 |
|
|
|
809 |
|
|
#ifdef ENABLE_JSP_MULTI
|
810 |
|
|
|
811 |
|
|
startbit = 1;
|
812 |
|
|
wrapbit = (xmitsize >> 3) & 0x1;
|
813 |
|
|
outdata[0] = (xmitsize << 5) | 0x1; // set the start bit
|
814 |
|
|
|
815 |
|
|
for(i = 0; i < xmitsize; i++) // don't copy off the end of the input array
|
816 |
|
|
{
|
817 |
|
|
outdata[i+1] = (data_to_send[i] << 1) | wrapbit;
|
818 |
|
|
wrapbit = (data_to_send[i] >> 7) & 0x1;
|
819 |
|
|
}
|
820 |
|
|
|
821 |
|
|
if(i < 8)
|
822 |
|
|
outdata[i+1] = wrapbit;
|
823 |
|
|
else
|
824 |
|
|
outdata[9] = wrapbit;
|
825 |
|
|
|
826 |
|
|
// If the last data bit is a '1', then we need to append a '0' so the top-level module
|
827 |
|
|
// won't treat the burst as a 'module select' command.
|
828 |
|
|
if(outdata[9] & 0x01) stopbit = 1;
|
829 |
|
|
else stopbit = 0;
|
830 |
|
|
|
831 |
|
|
#else
|
832 |
|
|
|
833 |
|
|
startbit = 0;
|
834 |
|
|
outdata[0] = 0x0 | (xmitsize << 4); // First byte out has write count in upper nibble
|
835 |
|
|
if (xmitsize > 0) memcpy(&outdata[1], data_to_send, xmitsize);
|
836 |
|
|
|
837 |
|
|
// If the last data bit is a '1', then we need to append a '0' so the top-level module
|
838 |
|
|
// won't treat the burst as a 'module select' command.
|
839 |
|
|
if(outdata[8] & 0x80) stopbit = 1;
|
840 |
|
|
else stopbit = 0;
|
841 |
|
|
|
842 |
|
|
#endif
|
843 |
|
|
|
844 |
|
|
debug("jsp doing 9 bytes, xmitsize %i\n", xmitsize);
|
845 |
|
|
|
846 |
|
|
// 72 bits: 9 bytes * 8 bits
|
847 |
|
|
err |= jtag_read_write_stream((uint32_t *) outdata, (uint32_t *) indata, 72+startbit+stopbit, 1, 1);
|
848 |
|
|
|
849 |
|
|
debug("jsp got remote sizes 0x%X\n", indata[0]);
|
850 |
|
|
|
851 |
|
|
*bytes_received = (indata[0] >> 4) & 0xF; // bytes available is in the upper nibble
|
852 |
|
|
memcpy(data_received, &indata[1], *bytes_received);
|
853 |
|
|
|
854 |
|
|
bytes_free = indata[0] & 0x0F;
|
855 |
|
|
*bytes_to_send = (bytes_free < xmitsize) ? bytes_free : xmitsize;
|
856 |
|
|
|
857 |
|
|
#else // !OPTIMIZE_JSP_FOR_USB
|
858 |
|
|
|
859 |
|
|
#ifdef ENABLE_JSP_MULTI
|
860 |
|
|
indata[0] = indata[1] = 0;
|
861 |
|
|
outdata[1] = (xmitsize >> 3) & 0x1;
|
862 |
|
|
outdata[0] = (xmitsize << 5) | 0x1; // set the start bit
|
863 |
|
|
startbit = 1;
|
864 |
|
|
|
865 |
|
|
#else
|
866 |
|
|
outdata[0] = 0x0 | (xmitsize << 4); // First byte out has write count in upper nibble
|
867 |
|
|
startbit = 0;
|
868 |
|
|
#endif
|
869 |
|
|
|
870 |
|
|
err |= jtag_read_write_stream((uint32_t *) outdata, (uint32_t *) indata, 8+startbit, 1, 0);
|
871 |
|
|
|
872 |
|
|
wrapbit = indata[1] & 0x1; // only used if ENABLE_JSP_MULTI is defined
|
873 |
|
|
bytes_free = indata[0] & 0x0F;
|
874 |
|
|
*bytes_received = (indata[0] >> 4) & 0xF; // bytes available is in the upper nibble
|
875 |
|
|
|
876 |
|
|
// Number of bytes to transact is max(bytes_available, min(bytes_to_send,bytes_free))
|
877 |
|
|
if(bytes_free < xmitsize) xmitsize = bytes_free;
|
878 |
|
|
if((*bytes_received) > xmitsize) xmitsize = *bytes_received;
|
879 |
|
|
|
880 |
|
|
memset(outdata, 0, 10);
|
881 |
|
|
memcpy(outdata, data_to_send, xmitsize); // use larger array in case we need to send stopbit
|
882 |
|
|
|
883 |
|
|
// If the last data bit is a '1', then we need to append a '0' so the top-level module
|
884 |
|
|
// won't treat the burst as a 'module select' command.
|
885 |
|
|
if(xmitsize && (outdata[xmitsize - 1] & 0x80)) stopbit = 2;
|
886 |
|
|
else stopbit = 1;
|
887 |
|
|
|
888 |
|
|
err |= jtag_read_write_stream((uint32_t *) outdata, (uint32_t *) indata, (xmitsize*8)+stopbit, 0, 1);
|
889 |
|
|
|
890 |
|
|
#ifdef ENABLE_JSP_MULTI
|
891 |
|
|
|
892 |
|
|
for(i = 0; i < (*bytes_received); i++)
|
893 |
|
|
{
|
894 |
|
|
data_received[i] = (indata[i] << 1) | wrapbit;
|
895 |
|
|
wrapbit = (indata[i] >> 7) & 0x1;
|
896 |
|
|
}
|
897 |
|
|
#else
|
898 |
|
|
memcpy(data_received, indata, xmitsize);
|
899 |
|
|
#endif
|
900 |
|
|
|
901 |
|
|
if(bytes_free < *bytes_to_send) *bytes_to_send = bytes_free;
|
902 |
|
|
|
903 |
|
|
#endif // !OPTIMIZE_JSP_FOR_USB
|
904 |
|
|
|
905 |
|
|
err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
|
906 |
|
|
|
907 |
|
|
return err;
|
908 |
|
|
}
|