1 |
14 |
nyawn |
|
2 |
|
|
#ifndef _ADV_DBG_COMMANDS_H_
|
3 |
|
|
#define _ADV_DBG_COMMANDS_H_
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
// Definitions for the top-level debug unit. This really just consists
|
7 |
|
|
// of a single register, used to select the active debug module ("chain").
|
8 |
|
|
#define DBG_MODULE_SELECT_REG_SIZE 2
|
9 |
|
|
#define DBG_MAX_MODULES 4 // used to size an array
|
10 |
|
|
|
11 |
|
|
#define DC_WISHBONE 0
|
12 |
|
|
#define DC_CPU0 1
|
13 |
|
|
#define DC_CPU1 2
|
14 |
|
|
|
15 |
|
|
// Polynomial for the CRC calculation
|
16 |
|
|
// Yes, it's backwards. Yes, this is on purpose.
|
17 |
|
|
// The hardware is designed this way to save on logic and routing,
|
18 |
|
|
// and it's really all the same to us here.
|
19 |
|
|
#define ADBG_CRC_POLY 0xedb88320
|
20 |
|
|
|
21 |
|
|
// These are for the internal registers in the Wishbone module
|
22 |
|
|
// The first is the length of the index register,
|
23 |
|
|
// the indexes of the various registers are defined after that
|
24 |
|
|
#define DBG_WB_REG_SEL_LEN 1
|
25 |
|
|
#define DBG_WB_REG_ERROR 0
|
26 |
|
|
|
27 |
|
|
// Opcode definitions for the Wishbone module
|
28 |
|
|
#define DBG_WB_OPCODE_LEN 4
|
29 |
|
|
#define DBG_WB_CMD_NOP 0x0
|
30 |
|
|
#define DBG_WB_CMD_BWRITE8 0x1
|
31 |
|
|
#define DBG_WB_CMD_BWRITE16 0x2
|
32 |
|
|
#define DBG_WB_CMD_BWRITE32 0x3
|
33 |
|
|
#define DBG_WB_CMD_BREAD8 0x5
|
34 |
|
|
#define DBG_WB_CMD_BREAD16 0x6
|
35 |
|
|
#define DBG_WB_CMD_BREAD32 0x7
|
36 |
|
|
#define DBG_WB_CMD_IREG_WR 0x9 // This is both a select and a write
|
37 |
|
|
#define DBG_WB_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
// Internal register definitions for the CPU0 module
|
41 |
|
|
#define DBG_CPU0_REG_SEL_LEN 1
|
42 |
|
|
#define DBG_CPU0_REG_STATUS 0
|
43 |
|
|
|
44 |
|
|
// Opcode definitions for the first CPU module
|
45 |
|
|
#define DBG_CPU0_OPCODE_LEN 4
|
46 |
|
|
#define DBG_CPU0_CMD_NOP 0x0
|
47 |
|
|
#define DBG_CPU0_CMD_BWRITE32 0x3
|
48 |
|
|
#define DBG_CPU0_CMD_BREAD32 0x7
|
49 |
|
|
#define DBG_CPU0_CMD_IREG_WR 0x9 // This is both a select and a write
|
50 |
|
|
#define DBG_CPU0_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
|
51 |
|
|
|
52 |
|
|
// Internal register definitions for the CPU1 module
|
53 |
|
|
#define DBG_CPU1_REG_SEL_LEN 1
|
54 |
|
|
#define DBG_CPU1_REG_STATUS 0
|
55 |
|
|
|
56 |
|
|
// Opcode definitions for the second CPU module
|
57 |
|
|
#define DBG_CPU1_OPCODE_LEN 4
|
58 |
|
|
#define DBG_CPU1_CMD_NOP 0x0
|
59 |
|
|
#define DBG_CPU1_CMD_BWRITE32 0x3
|
60 |
|
|
#define DBG_CPU1_CMD_BREAD32 0x7
|
61 |
|
|
#define DBG_CPU1_CMD_IREG_WR 0x9 // This is both a select and a write
|
62 |
|
|
#define DBG_CPU1_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
|
63 |
|
|
|
64 |
|
|
// API to do transactions on the advanced debug interface
|
65 |
|
|
int adbg_select_module(int chain);
|
66 |
|
|
int adbg_select_ctrl_reg(unsigned long regidx);
|
67 |
|
|
int adbg_ctrl_write(unsigned long regidx, uint32_t *cmd_data, int length_bits);
|
68 |
|
|
int adbg_ctrl_read(unsigned long regidx, uint32_t *data, int databits);
|
69 |
|
|
int adbg_burst_command(unsigned int opcode, unsigned long address, int length_words);
|
70 |
|
|
int adbg_wb_burst_read(int word_size_bytes, int word_count, unsigned long start_address, void *data);
|
71 |
|
|
int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address);
|
72 |
|
|
|
73 |
|
|
#endif
|