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// -*- Mode: Verilog -*-
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// Filename : ae18_core.v
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// Description : PIC18 compatible core.
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Fri Dec 22 16:09:33 2006
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// Last Modified By: Shawn Tan
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// Last Modified On: 2006-12-29
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// Update Count : 0
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// Status : Beta/Stable
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/*
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sybreon |
* $Id: ae18_core.v,v 1.2 2006-12-29 08:17:16 sybreon Exp $
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*
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* DESCRIPTION
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* This core provides a PIC18 software compatible core. It does not provide
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* any of the additional functionality needed to form a full PIC18 micro-
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* controller system. Additional functionality such as I/O devices would
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* need to be integrated with the core. This core provides the necessary
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* signals to wire up WISHBONE compatible devices to it.
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*
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3 |
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* 2006-12-29
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* Fixed minor bug with BCC and TBL instructions.
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*
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* 2006-12-27
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* CVS Checkin
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*/
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module ae18_core (/*AUTOARG*/
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// Outputs
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wb_clk_o, wb_rst_o, iwb_adr_o, iwb_dat_o, iwb_stb_o, iwb_we_o,
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iwb_sel_o, dwb_adr_o, dwb_dat_o, dwb_stb_o, dwb_we_o,
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// Inputs
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iwb_dat_i, iwb_ack_i, dwb_dat_i, dwb_ack_i, int_i, inte_i, clk_i,
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rst_i
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) ;
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// Instruction address bit length
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parameter ISIZ = 20;
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// Data address bit length
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parameter DSIZ = 12;
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// WDT length
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parameter WSIZ = 16;
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// System WB
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output wb_clk_o, wb_rst_o;
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// Instruction WB Bus
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output [ISIZ-1:1] iwb_adr_o;
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output [15:0] iwb_dat_o;
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output iwb_stb_o, iwb_we_o;
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output [1:0] iwb_sel_o;
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input [15:0] iwb_dat_i;
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input iwb_ack_i;
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// Data WB Bus
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output [DSIZ-1:0] dwb_adr_o;
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output [7:0] dwb_dat_o;
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output dwb_stb_o, dwb_we_o;
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input [7:0] dwb_dat_i;
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input dwb_ack_i;
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// System
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input [1:0] int_i;
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input [7:6] inte_i;
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input clk_i, rst_i;
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// Machine Status
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//output [3:0] qena_o;
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//output [1:0] qfsm_o;
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//output [1:0] qmod_o;
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// Special Function Registers
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reg [4:0] rPCU;
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reg [7:0] rPCH,rPCL, rTOSU, rTOSH, rTOSL,
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rPCLATU, rPCLATH,
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rTBLPTRU, rTBLPTRH, rTBLPTRL, rTABLAT,
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rPRODH, rPRODL,
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rFSR0H, rFSR0L, rFSR1H, rFSR1L, rFSR2H, rFSR2L;
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reg rSWDTEN, rSTKFUL, rSTKUNF;
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reg rZ,rOV,rDC,rN,rC;
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reg [5:0] rSTKPTR, rSTKPTR_;
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reg [7:0] rWREG, rWREG_;
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reg [7:0] rBSR, rBSR_;
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reg [4:0] rSTATUS_;
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// Control Word Registers
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reg [1:0] rMXSRC, rMXTGT, rMXDST, rMXBSR, rMXSTK, rMXSHA;
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reg [2:0] rMXSKP, rMXSTA, rMXNPC, rMXBCC;
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reg [3:0] rMXALU, rMXFSR, rMXTBL;
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reg [15:0] rEAPTR;
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// Control Path Registers
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reg rCLRWDT, rRESET, rSLEEP;
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reg rNSKP, rBCC, rSFRSTB;
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reg [7:0] rSFRDAT;
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// Control flags
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/*
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* DESCRIPTION
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* AE18 PLL generator.
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* Clock and reset generation using on chip DCM/PLL.
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*/
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wire clk = clk_i;
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wire xrst = rst_i;
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assign wb_clk_o = clk_i;
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assign wb_rst_o = ~rRESET;
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// WDT
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reg [WSIZ:0] rWDT;
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always @(negedge clk or negedge qrst)
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if (!qrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rWDT <= {(1+(WSIZ)){1'b0}};
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// End of automatics
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end else if (rCLRWDT|rSLEEP) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rWDT <= {(1+(WSIZ)){1'b0}};
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// End of automatics
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end else if (rSWDTEN)
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rWDT <= #1 rWDT + 1;
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// RAND
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reg [7:0] rPRNG;
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always @(negedge clk or negedge xrst)
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if (!xrst)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rPRNG <= 8'h0;
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// End of automatics
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else
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rPRNG <= #1 {rPRNG[6:0], ^{rPRNG[7],rPRNG[5:3]}};
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/*
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* DESCRIPTION
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* AE18 MCU conductor.
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* Determines and generates the control signal for machine states.
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*/
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// State Registers
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parameter [2:0]
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FSM_RUN = 4'h0,
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FSM_ISRL = 4'h1,
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FSM_ISRH = 4'h2,
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FSM_SLEEP = 4'h3;
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parameter [1:0]
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FSM_Q0 = 2'h0,
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FSM_Q1 = 2'h1,
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FSM_Q2 = 2'h2,
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FSM_Q3 = 2'h3;
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reg [3:0] rQCLK;
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reg [1:0] rQCNT;
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reg [1:0] rFSM, rNXT;
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//assign qena_o = rQCLK;
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//assign qfsm_o = rQCNT;
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//assign qmod_o = rFSM;
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wire qrst = rRESET;
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wire xrun = !((iwb_stb_o ^ iwb_ack_i) | (dwb_stb_o ^ dwb_ack_i));
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wire qrun = (rFSM != FSM_SLEEP);
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wire [3:0] qena = rQCLK;
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wire [1:0] qfsm = rQCNT;
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// Interrupt Debounce
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reg [2:0] rINTH,rINTL;
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wire fINTH = (rINTH == 3'o3);
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wire fINTL = (rINTL == 3'o3);
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always @(negedge clk or negedge xrst)
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if (!xrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rINTH <= 3'h0;
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rINTL <= 3'h0;
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// End of automatics
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end else begin
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rINTH <= #1 {rINTH[1:0],int_i[1]};
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rINTL <= #1 {rINTL[1:0],int_i[0]};
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end
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// Control Wires
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wire inth = fINTH;
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wire isrh = inte_i[7] & fINTH;
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wire intl = ~isrh & fINTL;
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wire isrl = intl & inte_i[6];
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// QCLK and QCNT sync
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always @(negedge clk or negedge qrst)
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if (!qrst) begin
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rQCLK <= 4'h8;
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rQCNT <= 2'h3;
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end else if (xrun & qrun) begin
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rQCLK <= #1 {rQCLK[2:0],rQCLK[3]};
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rQCNT <= #1 rQCNT + 2'd1;
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end
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// rINTF Latch
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reg [1:0] rINTF;
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always @(negedge clk or negedge xrst)
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if (!xrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rINTF <= 2'h0;
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// End of automatics
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end else begin
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rINTF <= #1 (^rFSM) ? rFSM :
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(qena[3]) ? 2'b00 :
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rINTF;
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end
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// FSM Sync
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always @(negedge clk or negedge qrst)
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if (!qrst)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rFSM <= 2'h0;
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// End of automatics
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else// if (qena[3])
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rFSM <= #1 rNXT;
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// FSM Logic
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always @(/*AUTOSENSE*/inth or intl or isrh or isrl or rFSM
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or rSLEEP)
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case (rFSM)
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//FSM_RESET: rNXT <= FSM_RUN;
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FSM_ISRH: rNXT <= FSM_RUN;
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FSM_ISRL: rNXT <= FSM_RUN;
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FSM_SLEEP: begin
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if (inth) rNXT <= FSM_ISRH;
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else if (intl) rNXT <= FSM_ISRL;
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//else if (rWDT[WSIZ]) rNXT <= FSM_RUN;
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else rNXT <= FSM_SLEEP;
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end
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default: begin
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if (isrh) rNXT <= FSM_ISRH;
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else if (isrl) rNXT <= FSM_ISRL;
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else if (rSLEEP) rNXT <= FSM_SLEEP;
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else rNXT <= FSM_RUN;
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end
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endcase // case(rFSM)
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/*
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* DESCRIPTION
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* Instruction WB logic
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*/
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// WB Registers
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3 |
sybreon |
reg [23:0] rIWBADR;
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2 |
sybreon |
reg rIWBSTB, rIWBWE;
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reg [1:0] rIWBSEL;
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//reg [15:0] rIDAT;
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assign iwb_adr_o = rIWBADR;
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assign iwb_stb_o = rIWBSTB;
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assign iwb_we_o = rIWBWE;
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assign iwb_dat_o = {rTABLAT,rTABLAT};
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assign iwb_sel_o = rIWBSEL;
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reg [15:0] rIREG, rROMLAT;
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reg [7:0] rILAT;
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reg [ISIZ-2:0] rPCNXT;
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wire [ISIZ-2:0] wPCLAT = {rPCU,rPCH,rPCL[7:1]};
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// IWB ADDR signal
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always @(negedge clk or negedge qrst)
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if (!qrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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3 |
sybreon |
rIWBADR <= 24'h0;
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2 |
sybreon |
// End of automatics
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end else if (qrun)
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case (qfsm)
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FSM_Q3: begin
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case (rINTF)
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FSM_ISRH: rIWBADR <= #1 23'h000004;
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FSM_ISRL: rIWBADR <= #1 23'h00000C;
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default: rIWBADR <= #1 rPCNXT;
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endcase // case(rINTF)
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end
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FSM_Q1: begin
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rIWBADR <= #1 (rMXTBL == MXTBL_NOP) ? rIWBADR : {rTBLPTRU,rTBLPTRH,rTBLPTRL[7:1]};
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end
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endcase // case(qfsm)
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// PC next calculation
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wire [ISIZ-2:0] wPCBCC = (!rNSKP) ? wPCINC :
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(rBCC) ? rIWBADR + {{(ISIZ-8){rIREG[7]}},rIREG[7:0]} : wPCINC;
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wire [ISIZ-2:0] wPCNEAR = (!rNSKP) ? wPCINC : rIWBADR + {{(ISIZ-11){rIREG[10]}},rIREG[10:0]};
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wire [ISIZ-2:0] wPCFAR = (!rNSKP) ? wPCINC : {rROMLAT[11:0],rIREG[7:0]};
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wire [ISIZ-2:0] wPCINC = rIWBADR + 1;
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wire [ISIZ-2:0] wPCSTK = (!rNSKP) ? wPCINC : {rTOSU, rTOSH, rTOSL[7:1]};
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|
|
always @(negedge clk or negedge qrst)
|
| 318 |
|
|
if (!qrst) begin
|
| 319 |
|
|
/*AUTORESET*/
|
| 320 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 321 |
|
|
rPCNXT <= {(1+(ISIZ-2)){1'b0}};
|
| 322 |
|
|
// End of automatics
|
| 323 |
|
|
end else if (qena[1]) begin
|
| 324 |
|
|
case (rMXNPC)
|
| 325 |
|
|
MXNPC_RET: rPCNXT <= #1 wPCSTK;
|
| 326 |
|
|
MXNPC_RESET: rPCNXT <= #1 24'h00;
|
| 327 |
|
|
MXNPC_ISRH: rPCNXT <= #1 24'h08;
|
| 328 |
|
|
MXNPC_ISRL: rPCNXT <= #1 24'h18;
|
| 329 |
|
|
MXNPC_NEAR: rPCNXT <= #1 wPCNEAR;
|
| 330 |
|
|
MXNPC_FAR: rPCNXT <= #1 wPCFAR;
|
| 331 |
|
|
MXNPC_BCC: rPCNXT <= #1 wPCBCC;
|
| 332 |
|
|
default: rPCNXT <= #1 wPCINC;
|
| 333 |
|
|
endcase // case(rMXNPC)
|
| 334 |
|
|
end // if (qena[1])
|
| 335 |
|
|
|
| 336 |
|
|
// ROMLAT + IREG
|
| 337 |
|
|
always @(negedge clk or negedge qrst)
|
| 338 |
|
|
if (!qrst) begin
|
| 339 |
|
|
/*AUTORESET*/
|
| 340 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 341 |
|
|
rILAT <= 8'h0;
|
| 342 |
|
|
rIREG <= 16'h0;
|
| 343 |
|
|
rROMLAT <= 16'h0;
|
| 344 |
|
|
// End of automatics
|
| 345 |
|
|
end else if (qrun) begin
|
| 346 |
|
|
case (qfsm)
|
| 347 |
|
|
FSM_Q0: rROMLAT <= #1 iwb_dat_i;
|
| 348 |
|
|
FSM_Q3: rIREG <= #1 rROMLAT;
|
| 349 |
3 |
sybreon |
FSM_Q2: rILAT <= (rTBLPTRL[0]) ? iwb_dat_i[7:0] : iwb_dat_i[15:8];
|
| 350 |
2 |
sybreon |
endcase // case(qfsm)
|
| 351 |
|
|
end
|
| 352 |
|
|
|
| 353 |
|
|
// IWB STB signal
|
| 354 |
|
|
wire wISTB = (rMXTBL != MXTBL_NOP);
|
| 355 |
|
|
always @(negedge clk or negedge qrst)
|
| 356 |
|
|
if (!qrst)
|
| 357 |
|
|
/*AUTORESET*/
|
| 358 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 359 |
|
|
rIWBSTB <= 1'h0;
|
| 360 |
|
|
// End of automatics
|
| 361 |
|
|
else if (qrun)
|
| 362 |
|
|
case (qfsm)
|
| 363 |
|
|
FSM_Q3: rIWBSTB <= #1 1'b1;
|
| 364 |
|
|
FSM_Q1: rIWBSTB <= #1 wISTB & rNSKP;
|
| 365 |
|
|
default: rIWBSTB <= #1 1'b0;
|
| 366 |
|
|
endcase // case(qfsm)
|
| 367 |
|
|
|
| 368 |
|
|
// IWB WE signal
|
| 369 |
|
|
wire wIWE = (rMXTBL == MXTBL_WT) | (rMXTBL == MXTBL_WTINC) | (rMXTBL == MXTBL_WTDEC) | (rMXTBL == MXTBL_WTPRE);
|
| 370 |
|
|
always @(negedge clk or negedge qrst)
|
| 371 |
|
|
if (!qrst)
|
| 372 |
|
|
/*AUTORESET*/
|
| 373 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 374 |
|
|
rIWBWE <= 1'h0;
|
| 375 |
|
|
// End of automatics
|
| 376 |
|
|
else if (qrun)
|
| 377 |
|
|
case (qfsm)
|
| 378 |
|
|
FSM_Q1: rIWBWE <= #1 wIWE & rNSKP;
|
| 379 |
|
|
default: rIWBWE <= #1 1'b0;
|
| 380 |
|
|
endcase // case(qfsm)
|
| 381 |
|
|
|
| 382 |
|
|
// IWB SEL signal
|
| 383 |
|
|
always @(negedge clk or negedge qrst)
|
| 384 |
|
|
if (!qrst)
|
| 385 |
|
|
/*AUTORESET*/
|
| 386 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 387 |
|
|
rIWBSEL <= 2'h0;
|
| 388 |
|
|
// End of automatics
|
| 389 |
|
|
else if (qrun)
|
| 390 |
|
|
case (qfsm)
|
| 391 |
|
|
FSM_Q3: rIWBSEL <= #1 2'h3;
|
| 392 |
|
|
FSM_Q1: rIWBSEL <= {rTBLPTRL[0],~rTBLPTRL[0]};
|
| 393 |
|
|
default: rIWBSEL <= #1 2'd0;
|
| 394 |
|
|
endcase // case(qfsm)
|
| 395 |
|
|
|
| 396 |
|
|
/*
|
| 397 |
|
|
* DESCRIPTION
|
| 398 |
|
|
* Instruction decode logic
|
| 399 |
|
|
*/
|
| 400 |
|
|
|
| 401 |
|
|
wire [3:0] fOPCH = rROMLAT[15:12];
|
| 402 |
|
|
wire [3:0] fOPCL = rROMLAT[11:8];
|
| 403 |
|
|
wire [7:0] fOPCK = rROMLAT[7:0];
|
| 404 |
|
|
|
| 405 |
|
|
// NIBBLE DECODER
|
| 406 |
|
|
wire fOPC0 = (fOPCH == 4'h0);
|
| 407 |
|
|
wire fOPC1 = (fOPCH == 4'h1);
|
| 408 |
|
|
wire fOPC2 = (fOPCH == 4'h2);
|
| 409 |
|
|
wire fOPC3 = (fOPCH == 4'h3);
|
| 410 |
|
|
wire fOPC4 = (fOPCH == 4'h4);
|
| 411 |
|
|
wire fOPC5 = (fOPCH == 4'h5);
|
| 412 |
|
|
wire fOPC6 = (fOPCH == 4'h6);
|
| 413 |
|
|
wire fOPC7 = (fOPCH == 4'h7);
|
| 414 |
|
|
wire fOPC8 = (fOPCH == 4'h8);
|
| 415 |
|
|
wire fOPC9 = (fOPCH == 4'h9);
|
| 416 |
|
|
wire fOPCA = (fOPCH == 4'hA);
|
| 417 |
|
|
wire fOPCB = (fOPCH == 4'hB);
|
| 418 |
|
|
wire fOPCC = (fOPCH == 4'hC);
|
| 419 |
|
|
wire fOPCD = (fOPCH == 4'hD);
|
| 420 |
|
|
wire fOPCE = (fOPCH == 4'hE);
|
| 421 |
|
|
wire fOPCF = (fOPCH == 4'hF);
|
| 422 |
|
|
wire fOP4G0 = (fOPCL == 4'h0);
|
| 423 |
|
|
wire fOP4G1 = (fOPCL == 4'h1);
|
| 424 |
|
|
wire fOP4G2 = (fOPCL == 4'h2);
|
| 425 |
|
|
wire fOP4G3 = (fOPCL == 4'h3);
|
| 426 |
|
|
wire fOP4G4 = (fOPCL == 4'h4);
|
| 427 |
|
|
wire fOP4G5 = (fOPCL == 4'h5);
|
| 428 |
|
|
wire fOP4G6 = (fOPCL == 4'h6);
|
| 429 |
|
|
wire fOP4G7 = (fOPCL == 4'h7);
|
| 430 |
|
|
wire fOP4G8 = (fOPCL == 4'h8);
|
| 431 |
|
|
wire fOP4G9 = (fOPCL == 4'h9);
|
| 432 |
|
|
wire fOP4GA = (fOPCL == 4'hA);
|
| 433 |
|
|
wire fOP4GB = (fOPCL == 4'hB);
|
| 434 |
|
|
wire fOP4GC = (fOPCL == 4'hC);
|
| 435 |
|
|
wire fOP4GD = (fOPCL == 4'hD);
|
| 436 |
|
|
wire fOP4GE = (fOPCL == 4'hE);
|
| 437 |
|
|
wire fOP4GF = (fOPCL == 4'hF);
|
| 438 |
|
|
wire fOP3G0 = (fOPCL[3:1] == 3'h0);
|
| 439 |
|
|
wire fOP3G1 = (fOPCL[3:1] == 3'h1);
|
| 440 |
|
|
wire fOP3G2 = (fOPCL[3:1] == 3'h2);
|
| 441 |
|
|
wire fOP3G3 = (fOPCL[3:1] == 3'h3);
|
| 442 |
|
|
wire fOP3G4 = (fOPCL[3:1] == 3'h4);
|
| 443 |
|
|
wire fOP3G5 = (fOPCL[3:1] == 3'h5);
|
| 444 |
|
|
wire fOP3G6 = (fOPCL[3:1] == 3'h6);
|
| 445 |
|
|
wire fOP3G7 = (fOPCL[3:1] == 3'h7);
|
| 446 |
|
|
wire fOP2G0 = (fOPCL[3:2] == 2'h0);
|
| 447 |
|
|
wire fOP2G1 = (fOPCL[3:2] == 2'h1);
|
| 448 |
|
|
wire fOP2G2 = (fOPCL[3:2] == 2'h2);
|
| 449 |
|
|
wire fOP2G3 = (fOPCL[3:2] == 2'h3);
|
| 450 |
|
|
wire fOP1G0 = (fOPCL[3] == 1'b0);
|
| 451 |
|
|
wire fOP1G1 = (fOPCL[3] == 1'b1);
|
| 452 |
|
|
|
| 453 |
|
|
// GROUP F
|
| 454 |
|
|
wire fNOPF = fOPCF;
|
| 455 |
|
|
// GROUP E
|
| 456 |
|
|
wire fBZ = fOPCE & fOP4G0;
|
| 457 |
|
|
wire fBNZ = fOPCE & fOP4G1;
|
| 458 |
|
|
wire fBC = fOPCE & fOP4G2;
|
| 459 |
|
|
wire fBNC = fOPCE & fOP4G3;
|
| 460 |
|
|
wire fBOV = fOPCE & fOP4G4;
|
| 461 |
|
|
wire fBNOV = fOPCE & fOP4G5;
|
| 462 |
|
|
wire fBN = fOPCE & fOP4G6;
|
| 463 |
|
|
wire fBNN = fOPCE & fOP4G7;
|
| 464 |
|
|
wire fCALL = fOPCE & fOP3G6;
|
| 465 |
|
|
wire fLFSR = fOPCE & fOP4GE;
|
| 466 |
|
|
wire fGOTO = fOPCE & fOP4GF;
|
| 467 |
|
|
// GROUP D
|
| 468 |
|
|
wire fBRA = fOPCD & fOP1G0;
|
| 469 |
|
|
wire fRCALL = fOPCD & fOP1G1;
|
| 470 |
|
|
// GROUP C
|
| 471 |
|
|
wire fMOVFF = fOPCC;
|
| 472 |
|
|
// GROUP B/A/9/8/7
|
| 473 |
|
|
wire fBTFSC = fOPCB;
|
| 474 |
|
|
wire fBTFSS = fOPCA;
|
| 475 |
|
|
wire fBCF = fOPC9;
|
| 476 |
|
|
wire fBSF = fOPC8;
|
| 477 |
|
|
wire fBTG = fOPC7;
|
| 478 |
|
|
// GROUP 6
|
| 479 |
|
|
wire fCPFSLT = fOPC6 & fOP3G0;
|
| 480 |
|
|
wire fCPFSEQ = fOPC6 & fOP3G1;
|
| 481 |
|
|
wire fCPFSGT = fOPC6 & fOP3G2;
|
| 482 |
|
|
wire fTSTFSZ = fOPC6 & fOP3G3;
|
| 483 |
|
|
wire fSETF = fOPC6 & fOP3G4;
|
| 484 |
|
|
wire fCLRF = fOPC6 & fOP3G5;
|
| 485 |
|
|
wire fNEGF = fOPC6 & fOP3G6;
|
| 486 |
|
|
wire fMOVWF = fOPC6 & fOP3G7;
|
| 487 |
|
|
// GROUP 5
|
| 488 |
|
|
wire fMOVF = fOPC5 & fOP2G0;
|
| 489 |
|
|
wire fSUBFWB = fOPC5 & fOP2G1;
|
| 490 |
|
|
wire fSUBWFB = fOPC5 & fOP2G2;
|
| 491 |
|
|
wire fSUBWF = fOPC5 & fOP2G3;
|
| 492 |
|
|
// GROUP 4
|
| 493 |
|
|
wire fRRNCF = fOPC4 & fOP2G0;
|
| 494 |
|
|
wire fRLNCF = fOPC4 & fOP2G1;
|
| 495 |
|
|
wire fINFSNZ = fOPC4 & fOP2G2;
|
| 496 |
|
|
wire fDCFSNZ = fOPC4 & fOP2G3;
|
| 497 |
|
|
// GROUP 3
|
| 498 |
|
|
wire fRRCF = fOPC3 & fOP2G0;
|
| 499 |
|
|
wire fRLCF = fOPC3 & fOP2G1;
|
| 500 |
|
|
wire fSWAPF = fOPC3 & fOP2G2;
|
| 501 |
|
|
wire fINCFSZ = fOPC3 & fOP2G3;
|
| 502 |
|
|
// GROUP 2
|
| 503 |
|
|
wire fADDWFC = fOPC2 & fOP2G0;
|
| 504 |
|
|
wire fADDWF = fOPC2 & fOP2G1;
|
| 505 |
|
|
wire fINCF = fOPC2 & fOP2G2;
|
| 506 |
|
|
wire fDECFSZ = fOPC2 & fOP2G3;
|
| 507 |
|
|
// GROUP 1
|
| 508 |
|
|
wire fIORWF = fOPC1 & fOP2G0;
|
| 509 |
|
|
wire fANDWF = fOPC1 & fOP2G1;
|
| 510 |
|
|
wire fXORWF = fOPC1 & fOP2G2;
|
| 511 |
|
|
wire fCOMF = fOPC1 & fOP2G3;
|
| 512 |
|
|
// GROUP 0
|
| 513 |
|
|
wire fMISC = fOPC0 & fOP4G0;
|
| 514 |
|
|
wire fMOVLB = fOPC0 & fOP4G1;
|
| 515 |
|
|
wire fMULWF = fOPC0 & fOP3G1;
|
| 516 |
|
|
wire fDECF = fOPC0 & fOP2G1;
|
| 517 |
|
|
wire fSUBLW = fOPC0 & fOP4G8;
|
| 518 |
|
|
wire fIORLW = fOPC0 & fOP4G9;
|
| 519 |
|
|
wire fXORLW = fOPC0 & fOP4GA;
|
| 520 |
|
|
wire fANDLW = fOPC0 & fOP4GB;
|
| 521 |
|
|
wire fRETLW = fOPC0 & fOP4GC;
|
| 522 |
|
|
wire fMULLW = fOPC0 & fOP4GD;
|
| 523 |
|
|
wire fMOVLW = fOPC0 & fOP4GE;
|
| 524 |
|
|
wire fADDLW = fOPC0 & fOP4GF;
|
| 525 |
|
|
// GROUP MISC
|
| 526 |
|
|
wire fNOP0 = fMISC & (fOPCK == 8'h00);
|
| 527 |
|
|
wire fRESET = fMISC & (fOPCK == 8'hFF);
|
| 528 |
|
|
wire fSLEEP = fMISC & (fOPCK == 8'h03);
|
| 529 |
|
|
wire fCLRWDT = fMISC & (fOPCK == 8'h04);
|
| 530 |
|
|
wire fPUSH = fMISC & (fOPCK == 8'h05);
|
| 531 |
|
|
wire fPOP = fMISC & (fOPCK == 8'h06);
|
| 532 |
|
|
wire fDAW = fMISC & (fOPCK == 8'h07);
|
| 533 |
|
|
wire fRETFIE = fMISC & (fOPCK == 8'h10 | fOPCK == 8'h11);
|
| 534 |
|
|
wire fRETURN = fMISC & (fOPCK == 8'h12 | fOPCK == 8'h13);
|
| 535 |
|
|
wire fNOP = fNOP0 | fNOPF;
|
| 536 |
|
|
wire fTBLRDWT = fMISC & (fOPCK[7:3] == 5'h01);
|
| 537 |
|
|
|
| 538 |
|
|
// MX INT
|
| 539 |
|
|
wire fINT = ^rINTF;
|
| 540 |
|
|
|
| 541 |
|
|
// MX_SRC
|
| 542 |
|
|
parameter [1:0]
|
| 543 |
|
|
MXSRC_MASK = 2'h2,
|
| 544 |
|
|
MXSRC_LIT = 2'h3,
|
| 545 |
|
|
MXSRC_WREG = 2'h0,
|
| 546 |
|
|
MXSRC_FILE = 2'h1;
|
| 547 |
|
|
wire [1:0] wMXSRC =
|
| 548 |
|
|
(fMOVLW|fRETLW|fCOMF|
|
| 549 |
|
|
fDECF|fDECFSZ|fDCFSNZ|
|
| 550 |
|
|
fINCF|fINCFSZ|fINFSNZ|
|
| 551 |
|
|
fMOVF|fMOVFF|fMOVWF|
|
| 552 |
|
|
fSETF|fTSTFSZ) ? MXSRC_LIT :
|
| 553 |
|
|
(fBSF|fBTG|fBTFSC|fBTFSS) ? MXSRC_MASK :
|
| 554 |
|
|
(fBCF|fCPFSLT|fSUBFWB) ? MXSRC_FILE :
|
| 555 |
|
|
MXSRC_WREG;
|
| 556 |
|
|
|
| 557 |
|
|
// MX_TGT
|
| 558 |
|
|
parameter [1:0]
|
| 559 |
|
|
MXTGT_MASK = 2'h2,
|
| 560 |
|
|
MXTGT_LIT = 2'h3,
|
| 561 |
|
|
MXTGT_WREG = 2'h0,
|
| 562 |
|
|
MXTGT_FILE = 2'h1;
|
| 563 |
|
|
wire [1:0] wMXTGT =
|
| 564 |
|
|
(fBCF) ? MXTGT_MASK :
|
| 565 |
|
|
(fRETLW|fMOVLW|
|
| 566 |
|
|
fMULLW|
|
| 567 |
|
|
fADDLW|fSUBLW|
|
| 568 |
|
|
fANDLW|fXORLW|fIORLW) ? MXTGT_LIT :
|
| 569 |
|
|
(fBSF|fBTFSC|fBTFSS|fBTG|
|
| 570 |
|
|
fADDWF|fADDWFC|fSUBWF|fSUBWFB|fMULWF|
|
| 571 |
|
|
fMULWF|fSWAPF|
|
| 572 |
|
|
fANDWF|fIORWF|fXORWF|
|
| 573 |
|
|
fCOMF|fMOVF|fMOVFF|
|
| 574 |
|
|
fCPFSEQ|fCPFSGT|fNEGF|
|
| 575 |
|
|
fDECF|fDECFSZ|fDCFSNZ|
|
| 576 |
|
|
fINCF|fINCFSZ|fINFSNZ|
|
| 577 |
|
|
fRLCF|fRLNCF|fRRCF|fRRNCF|
|
| 578 |
|
|
fTSTFSZ) ? MXTGT_FILE :
|
| 579 |
|
|
MXTGT_WREG;
|
| 580 |
|
|
|
| 581 |
|
|
// MX_DST
|
| 582 |
|
|
parameter [1:0]
|
| 583 |
|
|
MXDST_NULL = 2'h0,
|
| 584 |
|
|
MXDST_EXT = 2'h1,
|
| 585 |
|
|
MXDST_WREG = 2'h2,
|
| 586 |
|
|
MXDST_FILE = 2'h3;
|
| 587 |
|
|
wire [1:0] wMXDST =
|
| 588 |
|
|
(fMULWF|fMULLW|fMOVLB|fLFSR|fDAW) ? MXDST_EXT :
|
| 589 |
|
|
(fBCF|fBSF|fBTG|
|
| 590 |
|
|
fCLRF|
|
| 591 |
|
|
fMOVFF|fMOVWF|
|
| 592 |
|
|
fNEGF|fSETF) ? MXDST_FILE :
|
| 593 |
|
|
(fADDLW|fSUBLW|
|
| 594 |
|
|
fANDLW|fIORLW|fXORLW|
|
| 595 |
|
|
fMOVLW|fRETLW) ? MXDST_WREG :
|
| 596 |
|
|
(fADDWF|fADDWFC|
|
| 597 |
|
|
fANDWF|fIORWF|fXORWF|
|
| 598 |
|
|
fMOVF|fSWAPF|fCOMF|
|
| 599 |
|
|
fSUBFWB|fSUBWF|fSUBWFB|
|
| 600 |
|
|
fDECF|fDECFSZ|fDCFSNZ|
|
| 601 |
|
|
fINCF|fINCFSZ|fINFSNZ|
|
| 602 |
|
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1,fOPCL[1]} :
|
| 603 |
|
|
MXDST_NULL;
|
| 604 |
|
|
|
| 605 |
|
|
// MX_ALU
|
| 606 |
|
|
parameter [3:0]
|
| 607 |
|
|
MXALU_XOR = 4'h0,
|
| 608 |
|
|
MXALU_IOR = 4'h1,
|
| 609 |
|
|
MXALU_AND = 4'h2,
|
| 610 |
|
|
MXALU_SWAP = 4'h3,
|
| 611 |
|
|
MXALU_ADD = 4'h4,
|
| 612 |
|
|
MXALU_ADDC = 4'h5,
|
| 613 |
|
|
MXALU_SUB = 4'h6,
|
| 614 |
|
|
MXALU_SUBC = 4'h7,
|
| 615 |
|
|
MXALU_RLNC = 4'h8,
|
| 616 |
|
|
MXALU_RLC = 4'h9,
|
| 617 |
|
|
MXALU_RRNC = 4'hA,
|
| 618 |
|
|
MXALU_RRC = 4'hB,
|
| 619 |
|
|
MXALU_NEG = 4'hC,
|
| 620 |
|
|
// EXTRA
|
| 621 |
|
|
MXALU_MOVLB = 4'hC,
|
| 622 |
|
|
MXALU_DAW = 4'hD,
|
| 623 |
|
|
MXALU_LFSR = 4'hE,
|
| 624 |
|
|
MXALU_MUL = 4'hF;
|
| 625 |
|
|
wire [3:0] wMXALU =
|
| 626 |
|
|
(fDAW) ? MXALU_DAW :
|
| 627 |
|
|
(fMOVLB) ? MXALU_MOVLB :
|
| 628 |
|
|
(fLFSR) ? MXALU_LFSR :
|
| 629 |
|
|
(fMULLW|fMULWF) ? MXALU_MUL :
|
| 630 |
|
|
(fNEGF) ? MXALU_NEG :
|
| 631 |
|
|
(fADDLW|fADDWF|
|
| 632 |
|
|
fDECF|fDECFSZ|fDCFSNZ) ? MXALU_ADD :
|
| 633 |
|
|
(fSUBLW|fSUBWF|
|
| 634 |
|
|
fCPFSEQ|fCPFSGT|fCPFSLT|
|
| 635 |
|
|
fINCF|fINCFSZ|fINFSNZ) ? MXALU_SUB :
|
| 636 |
|
|
(fSUBWFB|fSUBFWB) ? MXALU_SUBC :
|
| 637 |
|
|
(fADDWFC) ? MXALU_ADDC :
|
| 638 |
|
|
(fRRCF) ? MXALU_RRC :
|
| 639 |
|
|
(fRRNCF) ? MXALU_RRNC :
|
| 640 |
|
|
(fRLCF) ? MXALU_RLC :
|
| 641 |
|
|
(fRLNCF) ? MXALU_RLNC :
|
| 642 |
|
|
(fSWAPF) ? MXALU_SWAP :
|
| 643 |
|
|
(fSETF|fIORWF|fIORLW|fBSF) ? MXALU_IOR :
|
| 644 |
|
|
(fBCF|fANDWF|fANDLW|
|
| 645 |
|
|
fRETLW|fBTFSS|fBTFSC|fTSTFSZ|
|
| 646 |
|
|
fMOVF|fMOVFF|fMOVWF|fMOVLW) ? MXALU_AND :
|
| 647 |
|
|
MXALU_XOR;
|
| 648 |
|
|
|
| 649 |
|
|
// MX_BSR
|
| 650 |
|
|
parameter [1:0]
|
| 651 |
|
|
MXBSR_BSR = 2'o3,
|
| 652 |
|
|
MXBSR_BSA = 2'o2,
|
| 653 |
|
|
MXBSR_LIT = 2'o1,
|
| 654 |
|
|
MXBSR_NUL = 2'o0;
|
| 655 |
|
|
wire [1:0] wMXBSR =
|
| 656 |
|
|
(fMOVFF) ? MXBSR_LIT :
|
| 657 |
|
|
(fBCF|fBSF|fBTG|fBTFSS|fBTFSC|
|
| 658 |
|
|
fANDWF|fIORWF|fXORWF|fCOMF|
|
| 659 |
|
|
fADDWF|fADDWFC|fSUBWF|fSUBWFB|fSUBFWB|fMULWF|
|
| 660 |
|
|
fCLRF|fMOVF|fMOVWF|fSETF|fSWAPF|
|
| 661 |
|
|
fCPFSEQ|fCPFSGT|fCPFSLT|fTSTFSZ|
|
| 662 |
|
|
fINCF|fINCFSZ|fINFSNZ|fDECF|fDECFSZ|fDCFSNZ|
|
| 663 |
|
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1, fOPCL[0]} :
|
| 664 |
|
|
MXBSR_NUL;
|
| 665 |
|
|
|
| 666 |
|
|
// MX_SKP
|
| 667 |
|
|
parameter [2:0]
|
| 668 |
|
|
MXSKP_SZ = 3'o1,
|
| 669 |
|
|
MXSKP_SNZ = 3'o2,
|
| 670 |
|
|
MXSKP_SNC = 3'o3,
|
| 671 |
|
|
MXSKP_SU = 3'o4,
|
| 672 |
|
|
MXSKP_SCC = 3'o7,
|
| 673 |
|
|
MXSKP_NON = 3'o0;
|
| 674 |
|
|
wire [2:0] wMXSKP =
|
| 675 |
|
|
(fTSTFSZ|fINCFSZ|fDECFSZ|fCPFSEQ|fBTFSC) ? MXSKP_SZ :
|
| 676 |
|
|
(fINFSNZ|fDCFSNZ|fBTFSS) ? MXSKP_SNZ :
|
| 677 |
|
|
(fCPFSGT|fCPFSLT) ? MXSKP_SNC :
|
| 678 |
|
|
(fBC|fBNC|fBZ|fBNZ|fBN|fBNN|fBOV|fBNOV) ? MXSKP_SCC :
|
| 679 |
|
|
(fBRA|fCALL|fRCALL|fGOTO|fRETFIE|fRETURN|fRETLW) ? MXSKP_SU :
|
| 680 |
|
|
MXSKP_NON;
|
| 681 |
|
|
|
| 682 |
|
|
// NPC_MX
|
| 683 |
|
|
parameter [2:0]
|
| 684 |
|
|
MXNPC_FAR = 3'o3,
|
| 685 |
|
|
MXNPC_NEAR = 3'o2,
|
| 686 |
|
|
MXNPC_BCC = 3'o7,
|
| 687 |
|
|
MXNPC_RET = 3'o1,
|
| 688 |
|
|
MXNPC_RESET = 3'o4,
|
| 689 |
|
|
MXNPC_ISRH = 3'o5,
|
| 690 |
|
|
MXNPC_ISRL = 3'o6,
|
| 691 |
|
|
MXNPC_INC = 3'o0;
|
| 692 |
|
|
wire [2:0] wMXNPC =
|
| 693 |
|
|
(fBC|fBNC|fBN|fBNN|fBOV|fBNOV|fBZ|fBNZ) ? MXNPC_BCC :
|
| 694 |
|
|
(fBRA|fRCALL) ? MXNPC_NEAR :
|
| 695 |
|
|
(fCALL|fGOTO) ? MXNPC_FAR :
|
| 696 |
|
|
(fRETFIE|fRETURN|fRETLW) ? MXNPC_RET :
|
| 697 |
|
|
MXNPC_INC;
|
| 698 |
|
|
|
| 699 |
|
|
// MX_STA
|
| 700 |
|
|
parameter [2:0]
|
| 701 |
|
|
MXSTA_ALL = 3'o7,
|
| 702 |
|
|
MXSTA_CZN = 3'o1,
|
| 703 |
|
|
MXSTA_ZN = 3'o2,
|
| 704 |
|
|
MXSTA_Z = 3'o3,
|
| 705 |
|
|
MXSTA_C = 3'o4,
|
| 706 |
|
|
MXSTA_NONE = 3'o0;
|
| 707 |
|
|
wire [2:0] wMXSTA =
|
| 708 |
|
|
(fADDLW|fADDWF|fADDWFC|
|
| 709 |
|
|
fSUBLW|fSUBWF|fSUBWFB|fSUBFWB|
|
| 710 |
|
|
fDECF|fINCF|fNEGF) ? MXSTA_ALL :
|
| 711 |
|
|
(fRRCF|fRLCF) ? MXSTA_CZN :
|
| 712 |
|
|
(fRRNCF|fRLNCF|
|
| 713 |
|
|
fMOVF|fCOMF|
|
| 714 |
|
|
fIORWF|fANDWF|fXORWF|fIORLW|fANDLW|fXORLW) ? MXSTA_ZN :
|
| 715 |
|
|
(fDAW) ? MXSTA_C :
|
| 716 |
|
|
(fCLRF) ? MXSTA_Z :
|
| 717 |
|
|
MXSTA_NONE;
|
| 718 |
|
|
|
| 719 |
|
|
// BCC_MX
|
| 720 |
|
|
parameter [2:0]
|
| 721 |
|
|
MXBCC_BZ = 3'o0,
|
| 722 |
|
|
MXBCC_BNZ = 3'o1,
|
| 723 |
|
|
MXBCC_BC = 3'o2,
|
| 724 |
|
|
MXBCC_BNC = 3'o3,
|
| 725 |
|
|
MXBCC_BOV = 3'o4,
|
| 726 |
|
|
MXBCC_BNOV = 3'o5,
|
| 727 |
|
|
MXBCC_BN = 3'o6,
|
| 728 |
|
|
MXBCC_BNN = 3'o7;
|
| 729 |
|
|
wire [2:0] wMXBCC = fOPCL[2:0];
|
| 730 |
|
|
|
| 731 |
|
|
// STK_MX
|
| 732 |
|
|
parameter [1:0]
|
| 733 |
|
|
MXSTK_PUSH = 2'o2,
|
| 734 |
|
|
MXSTK_POP = 2'o1,
|
| 735 |
|
|
MXSTK_NONE = 2'o0;
|
| 736 |
|
|
wire [1:0] wMXSTK =
|
| 737 |
|
|
(fRETFIE|fRETLW|fRETURN|fPOP) ? MXSTK_POP :
|
| 738 |
|
|
(fCALL|fRCALL|fPUSH|fINT) ? MXSTK_PUSH :
|
| 739 |
|
|
MXSTK_NONE;
|
| 740 |
|
|
|
| 741 |
|
|
// SHADOW MX
|
| 742 |
|
|
parameter [1:0]
|
| 743 |
|
|
MXSHA_CALL = 2'o2,
|
| 744 |
|
|
MXSHA_RET = 2'o1,
|
| 745 |
|
|
MXSHA_NONE = 2'o0;
|
| 746 |
|
|
|
| 747 |
|
|
wire [1:0] wMXSHA =
|
| 748 |
|
|
(fCALL) ? {fOPCL[0] ,1'b0} :
|
| 749 |
|
|
(fINT) ? {MXSHA_CALL} :
|
| 750 |
|
|
(fRETURN|fRETFIE) ? {1'b0,fOPCK[0]} :
|
| 751 |
|
|
1'b0;
|
| 752 |
|
|
|
| 753 |
|
|
// TBLRD/TBLWT MX
|
| 754 |
|
|
parameter [3:0]
|
| 755 |
|
|
MXTBL_RD = 4'h8,
|
| 756 |
|
|
MXTBL_RDINC = 4'h9,
|
| 757 |
|
|
MXTBL_RDDEC = 4'hA,
|
| 758 |
|
|
MXTBL_RDPRE = 4'hB,
|
| 759 |
|
|
MXTBL_WT = 4'hC,
|
| 760 |
|
|
MXTBL_WTINC = 4'hD,
|
| 761 |
|
|
MXTBL_WTDEC = 4'hE,
|
| 762 |
|
|
MXTBL_WTPRE = 4'hF,
|
| 763 |
|
|
MXTBL_NOP = 4'h0;
|
| 764 |
|
|
wire [3:0] wMXTBL =
|
| 765 |
|
|
(fTBLRDWT) ? fOPCK[3:0] :
|
| 766 |
|
|
MXTBL_NOP;
|
| 767 |
|
|
|
| 768 |
|
|
// FSR DECODER
|
| 769 |
|
|
parameter [15:0]
|
| 770 |
|
|
aPLUSW2 = 16'hFFDB,
|
| 771 |
|
|
aPREINC2 = 16'hFFDC,
|
| 772 |
|
|
aPOSTDEC2 = 16'hFFDD,
|
| 773 |
|
|
aPOSTINC2 = 16'hFFDE,
|
| 774 |
|
|
aINDF2 = 16'hFFDF,
|
| 775 |
|
|
aPLUSW1 = 16'hFFE3,
|
| 776 |
|
|
aPREINC1 = 16'hFFE4,
|
| 777 |
|
|
aPOSTDEC1 = 16'hFFE5,
|
| 778 |
|
|
aPOSTINC1 = 16'hFFE6,
|
| 779 |
|
|
aINDF1 = 16'hFFE7,
|
| 780 |
|
|
aPLUSW0 = 16'hFFEB,
|
| 781 |
|
|
aPREINC0 = 16'hFFEC,
|
| 782 |
|
|
aPOSTDEC0 = 16'hFFED,
|
| 783 |
|
|
aPOSTINC0 = 16'hFFEE,
|
| 784 |
|
|
aINDF0 = 16'hFFEF;
|
| 785 |
|
|
|
| 786 |
|
|
wire fGFF = (rEAPTR[15:6] == 10'h3FF);
|
| 787 |
|
|
wire fGFSR0 = (rEAPTR[5:3] == 3'o5);
|
| 788 |
|
|
wire fGFSR1 = (rEAPTR[5:3] == 3'o4);
|
| 789 |
|
|
wire fGFSR2 = (rEAPTR[5:3] == 3'o3);
|
| 790 |
|
|
wire fGPLUSW = (rEAPTR[2:0] == 3'o3);
|
| 791 |
|
|
wire fGPREINC = (rEAPTR[2:0] == 3'o4);
|
| 792 |
|
|
wire fGPOSTDEC = (rEAPTR[2:0] == 3'o5);
|
| 793 |
|
|
wire fGPOSTINC = (rEAPTR[2:0] == 3'o6);
|
| 794 |
|
|
wire fGINDF = (rEAPTR[2:0] == 3'o7);
|
| 795 |
|
|
|
| 796 |
|
|
wire fPLUSW2 = fGFF & fGFSR2 & fGPLUSW;
|
| 797 |
|
|
wire fPREINC2 = fGFF & fGFSR2 & fGPREINC;
|
| 798 |
|
|
wire fPOSTDEC2 = fGFF & fGFSR2 & fGPOSTDEC;
|
| 799 |
|
|
wire fPOSTINC2 = fGFF & fGFSR2 & fGPOSTINC;
|
| 800 |
|
|
wire fINDF2 = fGFF & fGFSR2 & fGINDF;
|
| 801 |
|
|
wire fPLUSW1 = fGFF & fGFSR1 & fGPLUSW;
|
| 802 |
|
|
wire fPREINC1 = fGFF & fGFSR1 & fGPREINC;
|
| 803 |
|
|
wire fPOSTDEC1 = fGFF & fGFSR1 & fGPOSTDEC;
|
| 804 |
|
|
wire fPOSTINC1 = fGFF & fGFSR1 & fGPOSTINC;
|
| 805 |
|
|
wire fINDF1 = fGFF & fGFSR1 & fGINDF;
|
| 806 |
|
|
wire fPLUSW0 = fGFF & fGFSR0 & fGPLUSW;
|
| 807 |
|
|
wire fPREINC0 = fGFF & fGFSR0 & fGPREINC;
|
| 808 |
|
|
wire fPOSTDEC0 = fGFF & fGFSR0 & fGPOSTDEC;
|
| 809 |
|
|
wire fPOSTINC0 = fGFF & fGFSR0 & fGPOSTINC;
|
| 810 |
|
|
wire fINDF0 = fGFF & fGFSR0 & fGINDF;
|
| 811 |
|
|
|
| 812 |
|
|
parameter [3:0]
|
| 813 |
|
|
MXFSR_INDF2 = 4'hF,
|
| 814 |
|
|
MXFSR_POSTINC2 = 4'hE,
|
| 815 |
|
|
MXFSR_POSTDEC2 = 4'hD,
|
| 816 |
|
|
MXFSR_PREINC2 = 4'hC,
|
| 817 |
|
|
MXFSR_PLUSW2 = 4'hB,
|
| 818 |
|
|
MXFSR_INDF1 = 4'hA,
|
| 819 |
|
|
MXFSR_POSTINC1 = 4'h9,
|
| 820 |
|
|
MXFSR_POSTDEC1 = 4'h8,
|
| 821 |
|
|
MXFSR_PREINC1 = 4'h7,
|
| 822 |
|
|
MXFSR_PLUSW1 = 4'h6,
|
| 823 |
|
|
MXFSR_INDF0 = 4'h5,
|
| 824 |
|
|
MXFSR_POSTINC0 = 4'h4,
|
| 825 |
|
|
MXFSR_POSTDEC0 = 4'h3,
|
| 826 |
|
|
MXFSR_PREINC0 = 4'h2,
|
| 827 |
|
|
MXFSR_PLUSW0 = 4'h1,
|
| 828 |
|
|
MXFSR_NORM = 4'h0;
|
| 829 |
|
|
|
| 830 |
|
|
wire [3:0] wMXFSR =
|
| 831 |
|
|
(fINDF0) ? MXFSR_INDF0 :
|
| 832 |
|
|
(fPLUSW0) ? MXFSR_PLUSW0 :
|
| 833 |
|
|
(fPREINC0) ? MXFSR_PREINC0 :
|
| 834 |
|
|
(fPOSTINC0) ? MXFSR_POSTINC0 :
|
| 835 |
|
|
(fPOSTDEC0) ? MXFSR_POSTDEC0 :
|
| 836 |
|
|
(fINDF1) ? MXFSR_INDF1 :
|
| 837 |
|
|
(fPLUSW1) ? MXFSR_PLUSW1 :
|
| 838 |
|
|
(fPREINC1) ? MXFSR_PREINC1 :
|
| 839 |
|
|
(fPOSTINC1) ? MXFSR_POSTINC1 :
|
| 840 |
|
|
(fPOSTDEC1) ? MXFSR_POSTDEC1 :
|
| 841 |
|
|
(fINDF2) ? MXFSR_INDF2 :
|
| 842 |
|
|
(fPLUSW2) ? MXFSR_PLUSW2 :
|
| 843 |
|
|
(fPREINC2) ? MXFSR_PREINC2 :
|
| 844 |
|
|
(fPOSTINC2) ? MXFSR_POSTINC2 :
|
| 845 |
|
|
(fPOSTDEC2) ? MXFSR_POSTDEC2 :
|
| 846 |
|
|
MXFSR_NORM;
|
| 847 |
|
|
|
| 848 |
|
|
always @(negedge clk or negedge qrst)
|
| 849 |
|
|
if (!qrst)
|
| 850 |
|
|
/*AUTORESET*/
|
| 851 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 852 |
|
|
rMXBSR <= 2'h0;
|
| 853 |
|
|
// End of automatics
|
| 854 |
|
|
else if (qena[1])
|
| 855 |
|
|
rMXBSR <= #1 wMXBSR;
|
| 856 |
|
|
|
| 857 |
|
|
// Control Word
|
| 858 |
|
|
always @(negedge clk or negedge qrst)
|
| 859 |
|
|
if (!qrst) begin
|
| 860 |
|
|
/*AUTORESET*/
|
| 861 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 862 |
|
|
rMXALU <= 4'h0;
|
| 863 |
|
|
rMXBCC <= 3'h0;
|
| 864 |
|
|
rMXDST <= 2'h0;
|
| 865 |
|
|
rMXFSR <= 4'h0;
|
| 866 |
|
|
rMXNPC <= 3'h0;
|
| 867 |
|
|
rMXSHA <= 2'h0;
|
| 868 |
|
|
rMXSKP <= 3'h0;
|
| 869 |
|
|
rMXSRC <= 2'h0;
|
| 870 |
|
|
rMXSTA <= 3'h0;
|
| 871 |
|
|
rMXSTK <= 2'h0;
|
| 872 |
|
|
rMXTBL <= 4'h0;
|
| 873 |
|
|
rMXTGT <= 2'h0;
|
| 874 |
|
|
// End of automatics
|
| 875 |
|
|
end else if (qena[3]) begin // if (!qrst)
|
| 876 |
|
|
rMXTGT <= #1 wMXTGT;
|
| 877 |
|
|
rMXSRC <= #1 wMXSRC;
|
| 878 |
|
|
rMXALU <= #1 wMXALU;
|
| 879 |
|
|
rMXNPC <= #1 wMXNPC;
|
| 880 |
|
|
rMXDST <= #1 wMXDST;
|
| 881 |
|
|
rMXSTA <= #1 wMXSTA;
|
| 882 |
|
|
rMXSKP <= #1 wMXSKP;
|
| 883 |
|
|
rMXBCC <= #1 wMXBCC;
|
| 884 |
|
|
rMXSTK <= #1 wMXSTK;
|
| 885 |
|
|
rMXFSR <= #1 wMXFSR;
|
| 886 |
|
|
rMXSHA <= #1 wMXSHA;
|
| 887 |
|
|
rMXTBL <= #1 wMXTBL;
|
| 888 |
|
|
end // if (qena[3])
|
| 889 |
|
|
|
| 890 |
|
|
/*
|
| 891 |
|
|
* DESCRIPTION
|
| 892 |
|
|
* EA pre calculation
|
| 893 |
|
|
*/
|
| 894 |
|
|
|
| 895 |
|
|
wire [15:0] wFILEBSR = {rBSR, rROMLAT[7:0]};
|
| 896 |
|
|
wire [15:0] wFILEBSA = { {(8){rROMLAT[7]}}, rROMLAT[7:0]};
|
| 897 |
|
|
wire [15:0] wFILELIT = {rBSR[7:4],rROMLAT[11:0]};
|
| 898 |
|
|
//wire [DSIZ-1:0] wFILEBSR = {rBSR, rROMLAT[7:0]};
|
| 899 |
|
|
//wire [DSIZ-1:0] wFILEBSA = { {(8){rROMLAT[7]}}, rROMLAT[7:0]};
|
| 900 |
|
|
//wire [DSIZ-1:0] wFILELIT = {rROMLAT[11:0]};
|
| 901 |
|
|
always @(negedge clk or negedge qrst)
|
| 902 |
|
|
if (!qrst) begin
|
| 903 |
|
|
/*AUTORESET*/
|
| 904 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 905 |
|
|
rEAPTR <= 16'h0;
|
| 906 |
|
|
// End of automatics
|
| 907 |
|
|
end else if (qena[2]) begin
|
| 908 |
|
|
case (rMXBSR)
|
| 909 |
|
|
MXBSR_BSR: rEAPTR <= #1 wFILEBSR;
|
| 910 |
|
|
MXBSR_BSA: rEAPTR <= #1 wFILEBSA;
|
| 911 |
|
|
MXBSR_LIT: rEAPTR <= #1 wFILELIT;
|
| 912 |
|
|
default: rEAPTR <= #1 rEAPTR;
|
| 913 |
|
|
endcase // case(rMXBSR)
|
| 914 |
|
|
end
|
| 915 |
|
|
|
| 916 |
|
|
/*
|
| 917 |
|
|
* DESCRIPTION
|
| 918 |
|
|
* Arithmetic Shift Logic Unit
|
| 919 |
|
|
*/
|
| 920 |
|
|
|
| 921 |
|
|
// BITMASK
|
| 922 |
|
|
reg [7:0] rMASK;
|
| 923 |
|
|
wire [7:0] wMASK =
|
| 924 |
|
|
(fOP3G0) ? 8'h01 :
|
| 925 |
|
|
(fOP3G1) ? 8'h02 :
|
| 926 |
|
|
(fOP3G2) ? 8'h04 :
|
| 927 |
|
|
(fOP3G3) ? 8'h08 :
|
| 928 |
|
|
(fOP3G4) ? 8'h10 :
|
| 929 |
|
|
(fOP3G5) ? 8'h20 :
|
| 930 |
|
|
(fOP3G6) ? 8'h40 :
|
| 931 |
|
|
8'h80;
|
| 932 |
|
|
always @(negedge clk or negedge qrst)
|
| 933 |
|
|
if (!qrst)
|
| 934 |
|
|
/*AUTORESET*/
|
| 935 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 936 |
|
|
rMASK <= 8'h0;
|
| 937 |
|
|
// End of automatics
|
| 938 |
|
|
else if (qena[2] & rNSKP)
|
| 939 |
|
|
rMASK <= #1 wMASK;
|
| 940 |
|
|
|
| 941 |
|
|
|
| 942 |
|
|
// SRC and TGT
|
| 943 |
|
|
reg [7:0] rSRC, rTGT;
|
| 944 |
|
|
always @(negedge clk or negedge qrst)
|
| 945 |
|
|
if (!qrst) begin
|
| 946 |
|
|
/*AUTORESET*/
|
| 947 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 948 |
|
|
rSRC <= 8'h0;
|
| 949 |
|
|
rTGT <= 8'h0;
|
| 950 |
|
|
// End of automatics
|
| 951 |
|
|
end else if (qena[1] & rNSKP) begin
|
| 952 |
|
|
case (rMXSRC)
|
| 953 |
|
|
MXSRC_FILE: rSRC <= #1 (rSFRSTB) ? rSFRDAT : dwb_dat_i;
|
| 954 |
|
|
//MXSRC_FILE: rSRC <= #1 dwb_dat_i;
|
| 955 |
|
|
MXSRC_MASK: rSRC <= #1 rMASK;
|
| 956 |
|
|
MXSRC_LIT: rSRC <= #1 8'hFF;
|
| 957 |
|
|
default: rSRC <= #1 rWREG;
|
| 958 |
|
|
endcase // case(rMXSRC)
|
| 959 |
|
|
|
| 960 |
|
|
case (rMXTGT)
|
| 961 |
|
|
MXTGT_MASK: rTGT <= #1 ~rMASK;
|
| 962 |
|
|
MXTGT_FILE: rTGT <= #1 (rSFRSTB) ? rSFRDAT : dwb_dat_i;
|
| 963 |
|
|
//MXTGT_FILE: rTGT <= #1 dwb_dat_i;
|
| 964 |
|
|
MXTGT_LIT: rTGT <= #1 rIREG[7:0];
|
| 965 |
|
|
default: rTGT <= #1 rWREG;
|
| 966 |
|
|
endcase // case(rMXTGT)
|
| 967 |
|
|
end // if (qena[1] & rNSKP)
|
| 968 |
|
|
|
| 969 |
|
|
// ALU Operations
|
| 970 |
|
|
wire [8:0] wADD = (rSRC + rTGT);
|
| 971 |
|
|
wire [8:0] wADDC = wADD + rC;
|
| 972 |
|
|
wire [8:0] wSUB = (rTGT - rSRC);
|
| 973 |
|
|
wire [8:0] wSUBC = wSUB - ~rC;
|
| 974 |
|
|
|
| 975 |
|
|
wire [8:0] wNEG = (0 - rTGT);
|
| 976 |
|
|
|
| 977 |
|
|
wire [8:0] wRRC = {rTGT[0],rC,rTGT[7:1]};
|
| 978 |
|
|
wire [8:0] wRLC = {rTGT[7:0],rC};
|
| 979 |
|
|
wire [8:0] wRRNC = {1'b0,rTGT[0],rTGT[7:1]};
|
| 980 |
|
|
wire [8:0] wRLNC = {1'b0,rTGT[6:0],rTGT[7]};
|
| 981 |
|
|
|
| 982 |
|
|
wire [8:0] wAND = {1'b0, rSRC & rTGT};
|
| 983 |
|
|
wire [8:0] wIOR = {1'b0, rSRC | rTGT};
|
| 984 |
|
|
wire [8:0] wXOR = {1'b0, rSRC ^ rTGT};
|
| 985 |
|
|
wire [8:0] wSWAP = {1'b0, rTGT[3:0], rTGT[7:4]};
|
| 986 |
|
|
|
| 987 |
|
|
// RESULT register
|
| 988 |
|
|
reg [7:0] rRESULT;
|
| 989 |
|
|
always @(negedge clk or negedge qrst)
|
| 990 |
|
|
if (!qrst) begin
|
| 991 |
|
|
/*AUTORESET*/
|
| 992 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 993 |
|
|
rRESULT <= 8'h0;
|
| 994 |
|
|
// End of automatics
|
| 995 |
|
|
end else if (qena[2] & rNSKP) begin
|
| 996 |
|
|
case (rMXALU)
|
| 997 |
|
|
default: rRESULT <= #1 wXOR;
|
| 998 |
|
|
MXALU_AND: rRESULT <= #1 wAND;
|
| 999 |
|
|
MXALU_IOR: rRESULT <= #1 wIOR;
|
| 1000 |
|
|
MXALU_SWAP: rRESULT <= #1 wSWAP;
|
| 1001 |
|
|
MXALU_RRC: rRESULT <= #1 wRRC;
|
| 1002 |
|
|
MXALU_RLC: rRESULT <= #1 wRLC;
|
| 1003 |
|
|
MXALU_RRNC: rRESULT <= #1 wRRNC;
|
| 1004 |
|
|
MXALU_RLNC: rRESULT <= #1 wRLNC;
|
| 1005 |
|
|
MXALU_ADD: rRESULT <= #1 wADD;
|
| 1006 |
|
|
MXALU_ADDC: rRESULT <= #1 wADDC;
|
| 1007 |
|
|
MXALU_SUB: rRESULT <= #1 wSUB;
|
| 1008 |
|
|
MXALU_SUBC: rRESULT <= #1 wSUBC;
|
| 1009 |
|
|
MXALU_NEG: rRESULT <= #1 wNEG;
|
| 1010 |
|
|
endcase // case(rMXALU)
|
| 1011 |
|
|
end // if (qena[2] & rNSKP)
|
| 1012 |
|
|
|
| 1013 |
|
|
// C register
|
| 1014 |
|
|
reg rC_;
|
| 1015 |
|
|
always @(negedge clk or negedge qrst)
|
| 1016 |
|
|
if (!qrst)
|
| 1017 |
|
|
/*AUTORESET*/
|
| 1018 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1019 |
|
|
rC_ <= 1'h0;
|
| 1020 |
|
|
// End of automatics
|
| 1021 |
|
|
else if (qena[2] & rNSKP)
|
| 1022 |
|
|
case (rMXALU)
|
| 1023 |
|
|
MXALU_ADD: rC_ <= #1 wADD[8];
|
| 1024 |
|
|
MXALU_ADDC: rC_ <= #1 wADDC[8];
|
| 1025 |
|
|
MXALU_SUB: rC_ <= #1 wSUB[8];
|
| 1026 |
|
|
MXALU_SUBC: rC_ <= #1 wSUBC[8];
|
| 1027 |
|
|
MXALU_RRC: rC_ <= #1 wRRC[8];
|
| 1028 |
|
|
MXALU_RLC: rC_ <= #1 wRLC[8];
|
| 1029 |
|
|
MXALU_NEG: rC_ <= #1 wNEG[8];
|
| 1030 |
|
|
default: rC_ <= #1 rC;
|
| 1031 |
|
|
endcase // case(rMXALU)
|
| 1032 |
|
|
|
| 1033 |
|
|
wire wC, wZ, wN, wOV, wDC;
|
| 1034 |
|
|
assign wN = rRESULT[7];
|
| 1035 |
|
|
assign wOV = ~(rSRC[7] ^ rTGT[7]) & (rRESULT[7] ^ rSRC[7]);
|
| 1036 |
|
|
assign wZ = (rRESULT == 8'h00);
|
| 1037 |
|
|
assign wDC = rRESULT[4];
|
| 1038 |
|
|
assign wC = rC_;
|
| 1039 |
|
|
|
| 1040 |
|
|
/*
|
| 1041 |
|
|
* DESCRIPTION
|
| 1042 |
|
|
* Other Execution Units
|
| 1043 |
|
|
*/
|
| 1044 |
|
|
|
| 1045 |
|
|
// SPECIAL OPERATION
|
| 1046 |
|
|
reg rCLRWDT_, rSLEEP_;
|
| 1047 |
|
|
always @(negedge clk or negedge qrst)
|
| 1048 |
|
|
if (!qrst) begin
|
| 1049 |
|
|
/*AUTORESET*/
|
| 1050 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1051 |
|
|
rCLRWDT <= 1'h0;
|
| 1052 |
|
|
rCLRWDT_ <= 1'h0;
|
| 1053 |
|
|
rSLEEP <= 1'h0;
|
| 1054 |
|
|
rSLEEP_ <= 1'h0;
|
| 1055 |
|
|
// End of automatics
|
| 1056 |
|
|
end else begin
|
| 1057 |
|
|
//rCLRWDT <= #1 (rCLRWDT_ & rNSKP);
|
| 1058 |
|
|
//rSLEEP <= #1 (rSLEEP_ & rNSKP);
|
| 1059 |
|
|
rCLRWDT <= #1 (rCLRWDT_ & rNSKP & qena[3]);
|
| 1060 |
|
|
rSLEEP <= #1 (rSLEEP_ & rNSKP & qena[3]);
|
| 1061 |
|
|
|
| 1062 |
|
|
rCLRWDT_ <= #1 (qena[3]) ? fCLRWDT : rCLRWDT_;
|
| 1063 |
|
|
rSLEEP_ <= #1 (qena[3]) ? fSLEEP : rSLEEP_;
|
| 1064 |
|
|
end
|
| 1065 |
|
|
|
| 1066 |
|
|
reg rRESET_;
|
| 1067 |
|
|
always @(negedge clk or negedge xrst)
|
| 1068 |
|
|
if (!xrst) begin
|
| 1069 |
|
|
/*AUTORESET*/
|
| 1070 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1071 |
|
|
rRESET <= 1'h0;
|
| 1072 |
|
|
rRESET_ <= 1'h0;
|
| 1073 |
|
|
// End of automatics
|
| 1074 |
|
|
end else begin
|
| 1075 |
|
|
rRESET_ <= #1 ~(fRESET | rWDT[WSIZ]);
|
| 1076 |
|
|
rRESET <= #1 rRESET_;
|
| 1077 |
|
|
end
|
| 1078 |
|
|
|
| 1079 |
|
|
// BCC Checker
|
| 1080 |
|
|
always @(negedge clk or negedge qrst)
|
| 1081 |
|
|
if (!qrst) begin
|
| 1082 |
|
|
/*AUTORESET*/
|
| 1083 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1084 |
|
|
rBCC <= 1'h0;
|
| 1085 |
|
|
// End of automatics
|
| 1086 |
3 |
sybreon |
end else if (qena[0]) begin
|
| 1087 |
2 |
sybreon |
case (rMXBCC)
|
| 1088 |
3 |
sybreon |
MXBCC_BZ: rBCC <= #1 rZ;
|
| 1089 |
2 |
sybreon |
MXBCC_BNZ: rBCC <= #1 ~rZ;
|
| 1090 |
|
|
MXBCC_BC: rBCC <= #1 rC;
|
| 1091 |
|
|
MXBCC_BNC: rBCC <= #1 ~rC;
|
| 1092 |
|
|
MXBCC_BOV: rBCC <= #1 rOV;
|
| 1093 |
|
|
MXBCC_BNOV: rBCC <= #1 ~rOV;
|
| 1094 |
|
|
MXBCC_BN: rBCC <= #1 rN;
|
| 1095 |
|
|
MXBCC_BNN: rBCC <= #1 ~rN;
|
| 1096 |
3 |
sybreon |
endcase // case(rMXBCC)
|
| 1097 |
|
|
end
|
| 1098 |
2 |
sybreon |
|
| 1099 |
|
|
// SKIP register
|
| 1100 |
|
|
wire wSKP =
|
| 1101 |
|
|
(rMXSKP == MXSKP_SZ) ? wZ :
|
| 1102 |
|
|
(rMXSKP == MXSKP_SNZ) ? ~wZ :
|
| 1103 |
|
|
(rMXSKP == MXSKP_SNC) ? ~wC :
|
| 1104 |
|
|
(rMXSKP == MXSKP_SCC) ? rBCC :
|
| 1105 |
|
|
(rMXSKP == MXSKP_SU) ? 1'b1 :
|
| 1106 |
|
|
1'b0;
|
| 1107 |
|
|
always @(negedge clk or negedge qrst)
|
| 1108 |
|
|
if (!qrst)
|
| 1109 |
|
|
rNSKP <= 1'h1;
|
| 1110 |
|
|
else if (qena[3])
|
| 1111 |
|
|
rNSKP <= #1 (rNSKP) ? ~wSKP : 1'b1;
|
| 1112 |
|
|
|
| 1113 |
|
|
// STACK
|
| 1114 |
|
|
wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
|
| 1115 |
|
|
wire [ISIZ-1:0] wSTKR;
|
| 1116 |
|
|
wire wSTKE = (qena[1]);
|
| 1117 |
|
|
|
| 1118 |
|
|
ae18_aram #(ISIZ,5)
|
| 1119 |
|
|
stack (
|
| 1120 |
|
|
.wdat(wSTKW), .rdat(wSTKR),
|
| 1121 |
|
|
.radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
|
| 1122 |
|
|
.we(wSTKE),
|
| 1123 |
|
|
// Inputs
|
| 1124 |
3 |
sybreon |
.clk (clk));
|
| 1125 |
2 |
sybreon |
|
| 1126 |
|
|
/*
|
| 1127 |
|
|
* DESCRIPTION
|
| 1128 |
|
|
* Data WB logic
|
| 1129 |
|
|
*/
|
| 1130 |
|
|
|
| 1131 |
|
|
reg [15:0] rDWBADR;
|
| 1132 |
|
|
reg rDWBSTB, rDWBWE;
|
| 1133 |
|
|
|
| 1134 |
|
|
assign dwb_adr_o = rDWBADR;
|
| 1135 |
|
|
assign dwb_stb_o = rDWBSTB;
|
| 1136 |
|
|
assign dwb_we_o = rDWBWE;
|
| 1137 |
|
|
assign dwb_dat_o = rRESULT;
|
| 1138 |
|
|
|
| 1139 |
|
|
// DWB ADR signal
|
| 1140 |
|
|
wire [DSIZ-1:0] wFSRINC0 = {rFSR0H,rFSR0L} + 1;
|
| 1141 |
|
|
wire [DSIZ-1:0] wFSRINC1 = {rFSR1H,rFSR1L} + 1;
|
| 1142 |
|
|
wire [DSIZ-1:0] wFSRINC2 = {rFSR2H,rFSR2L} + 1;
|
| 1143 |
|
|
wire [DSIZ-1:0] wFSRPLUSW0 = {rFSR0H,rFSR0L} + rWREG;
|
| 1144 |
|
|
wire [DSIZ-1:0] wFSRPLUSW1 = {rFSR1H,rFSR1L} + rWREG;
|
| 1145 |
|
|
wire [DSIZ-1:0] wFSRPLUSW2 = {rFSR2H,rFSR2L} + rWREG;
|
| 1146 |
|
|
always @(negedge clk or negedge qrst)
|
| 1147 |
|
|
if (!qrst) begin
|
| 1148 |
|
|
/*AUTORESET*/
|
| 1149 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1150 |
|
|
rDWBADR <= 16'h0;
|
| 1151 |
|
|
// End of automatics
|
| 1152 |
|
|
end else if (qrun & rNSKP)
|
| 1153 |
|
|
case (qfsm)
|
| 1154 |
|
|
FSM_Q0:
|
| 1155 |
|
|
case (rMXFSR)
|
| 1156 |
|
|
MXFSR_INDF0,MXFSR_POSTINC0,MXFSR_POSTDEC0: rDWBADR <= #1 {rFSR0H,rFSR0L};
|
| 1157 |
|
|
MXFSR_INDF1,MXFSR_POSTINC1,MXFSR_POSTDEC1: rDWBADR <= #1 {rFSR1H,rFSR1L};
|
| 1158 |
|
|
MXFSR_INDF2,MXFSR_POSTINC2,MXFSR_POSTDEC2: rDWBADR <= #1 {rFSR2H,rFSR2L};
|
| 1159 |
|
|
MXFSR_PREINC0: rDWBADR <= #1 wFSRINC0;
|
| 1160 |
|
|
MXFSR_PREINC1: rDWBADR <= #1 wFSRINC1;
|
| 1161 |
|
|
MXFSR_PREINC2: rDWBADR <= #1 wFSRINC2;
|
| 1162 |
|
|
MXFSR_PLUSW2: rDWBADR <= #1 wFSRPLUSW2;
|
| 1163 |
|
|
MXFSR_PLUSW1: rDWBADR <= #1 wFSRPLUSW1;
|
| 1164 |
|
|
MXFSR_PLUSW0: rDWBADR <= #1 wFSRPLUSW0;
|
| 1165 |
|
|
default: rDWBADR <= #1 rEAPTR;
|
| 1166 |
|
|
endcase // case(rMXFSR)
|
| 1167 |
|
|
FSM_Q1: rDWBADR <= #1 (rMXBSR == MXBSR_LIT) ? {rROMLAT[11:0]} : rDWBADR;
|
| 1168 |
|
|
default: rDWBADR <= #1 rDWBADR;
|
| 1169 |
|
|
endcase // case(qfsm)
|
| 1170 |
|
|
|
| 1171 |
|
|
// DWB WE signal
|
| 1172 |
|
|
always @(negedge clk or negedge qrst)
|
| 1173 |
|
|
if (!qrst) begin
|
| 1174 |
|
|
/*AUTORESET*/
|
| 1175 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1176 |
|
|
rDWBWE <= 1'h0;
|
| 1177 |
|
|
// End of automatics
|
| 1178 |
|
|
end else if (qrun & rNSKP)
|
| 1179 |
|
|
case (qfsm)
|
| 1180 |
|
|
FSM_Q2: rDWBWE <= #1 (rMXDST == MXDST_FILE);
|
| 1181 |
|
|
default: rDWBWE <= #1 1'b0;
|
| 1182 |
|
|
endcase // case(qfsm)
|
| 1183 |
|
|
|
| 1184 |
|
|
// DWB STB signal
|
| 1185 |
|
|
always @(negedge clk or negedge qrst)
|
| 1186 |
|
|
if (!qrst) begin
|
| 1187 |
|
|
/*AUTORESET*/
|
| 1188 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1189 |
|
|
rDWBSTB <= 1'h0;
|
| 1190 |
|
|
// End of automatics
|
| 1191 |
|
|
end else if (qrun & rNSKP)
|
| 1192 |
|
|
case (qfsm)
|
| 1193 |
|
|
FSM_Q2: rDWBSTB <= #1 (rMXDST == MXDST_FILE);
|
| 1194 |
|
|
FSM_Q0: rDWBSTB <= #1 ((rMXSRC == MXSRC_FILE) | (rMXTGT == MXTGT_FILE));
|
| 1195 |
|
|
default: rDWBSTB <= #1 1'b0;
|
| 1196 |
|
|
endcase // case(qfsm)
|
| 1197 |
|
|
|
| 1198 |
|
|
/*
|
| 1199 |
|
|
* SFR Bank
|
| 1200 |
|
|
*/
|
| 1201 |
|
|
parameter [15:0]
|
| 1202 |
|
|
//aRCON = 16'hFFD0,
|
| 1203 |
|
|
aWDTCON = 16'hFFD1,
|
| 1204 |
|
|
aSTATUS = 16'hFFD8,//
|
| 1205 |
|
|
aFSR2L = 16'hFFD9,//
|
| 1206 |
|
|
aFSR2H = 16'hFFDA,//
|
| 1207 |
|
|
aBSR = 16'hFFE0,//
|
| 1208 |
|
|
aFSR1L = 16'hFFE1,//
|
| 1209 |
|
|
aFSR1H = 16'hFFE2,//
|
| 1210 |
|
|
aWREG = 16'hFFE8,//
|
| 1211 |
|
|
aFSR0L = 16'hFFE9,//
|
| 1212 |
|
|
aFSR0H = 16'hFFEA,//
|
| 1213 |
|
|
aPRODL = 16'hFFF3,//
|
| 1214 |
|
|
aPRODH = 16'hFFF4,//
|
| 1215 |
|
|
aPRNG = 16'hFFD4,//
|
| 1216 |
|
|
aTABLAT = 16'hFFF5,//
|
| 1217 |
|
|
aTBLPTRL = 16'hFFF6,//
|
| 1218 |
|
|
aTBLPTRH = 16'hFFF7,//
|
| 1219 |
|
|
aTBLPTRU = 16'hFFF8,//
|
| 1220 |
|
|
aPCL = 16'hFFF9,//
|
| 1221 |
|
|
aPCLATH = 16'hFFFA,//
|
| 1222 |
|
|
aPCLATU = 16'hFFFB,//
|
| 1223 |
|
|
aSTKPTR = 16'hFFFC,//
|
| 1224 |
|
|
aTOSL = 16'hFFFD,//
|
| 1225 |
|
|
aTOSH = 16'hFFFE,//
|
| 1226 |
|
|
aTOSU = 16'hFFFF;//
|
| 1227 |
|
|
|
| 1228 |
|
|
// Read SFR
|
| 1229 |
|
|
always @(posedge clk or negedge qrst)
|
| 1230 |
|
|
if (!qrst) begin
|
| 1231 |
|
|
/*AUTORESET*/
|
| 1232 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1233 |
|
|
rSFRDAT <= 8'h0;
|
| 1234 |
|
|
// End of automatics
|
| 1235 |
|
|
end else if (rDWBSTB & rNSKP) begin
|
| 1236 |
|
|
case (rDWBADR[5:0])
|
| 1237 |
|
|
aWDTCON[5:0]: rSFRDAT <= #1 {7'd0,rSWDTEN};
|
| 1238 |
|
|
aSTATUS[5:0]: rSFRDAT <= #1 {3'd0,rN,rOV,rZ,rDC,rC};
|
| 1239 |
|
|
aFSR2L[5:0]: rSFRDAT <= #1 rFSR2L;
|
| 1240 |
|
|
aFSR2H[5:0]: rSFRDAT <= #1 rFSR2H;
|
| 1241 |
|
|
aBSR[5:0]: rSFRDAT <= #1 rBSR;
|
| 1242 |
|
|
aFSR1L[5:0]: rSFRDAT <= #1 rFSR1L;
|
| 1243 |
|
|
aFSR1H[5:0]: rSFRDAT <= #1 rFSR1H;
|
| 1244 |
|
|
aWREG[5:0]: rSFRDAT <= #1 rWREG;
|
| 1245 |
|
|
aFSR0L[5:0]: rSFRDAT <= #1 rFSR0L;
|
| 1246 |
|
|
aFSR0H[5:0]: rSFRDAT <= #1 rFSR0H;
|
| 1247 |
|
|
aPRODL[5:0]: rSFRDAT <= #1 rPRODL;
|
| 1248 |
|
|
aPRODH[5:0]: rSFRDAT <= #1 rPRODH;
|
| 1249 |
|
|
aPRNG[5:0]: rSFRDAT <= #1 rPRNG;
|
| 1250 |
|
|
aTABLAT[5:0]: rSFRDAT <= #1 rTABLAT;
|
| 1251 |
|
|
aTBLPTRL[5:0]: rSFRDAT <= #1 rTBLPTRL;
|
| 1252 |
|
|
aTBLPTRH[5:0]: rSFRDAT <= #1 rTBLPTRH;
|
| 1253 |
|
|
aTBLPTRU[5:0]: rSFRDAT <= #1 rTBLPTRU;
|
| 1254 |
|
|
aPCL[5:0]: rSFRDAT <= #1 rPCL;
|
| 1255 |
|
|
aPCLATH[5:0]: rSFRDAT <= #1 rPCLATH;
|
| 1256 |
|
|
aPCLATU[5:0]: rSFRDAT <= #1 rPCLATU;
|
| 1257 |
|
|
aSTKPTR[5:0]: rSFRDAT <= #1 {rSTKFUL,rSTKUNF,1'b0,rSTKPTR[4:0]};
|
| 1258 |
|
|
aTOSU[5:0]: rSFRDAT <= #1 rTOSU;
|
| 1259 |
|
|
aTOSH[5:0]: rSFRDAT <= #1 rTOSH;
|
| 1260 |
|
|
aTOSL[5:0]: rSFRDAT <= #1 rTOSL;
|
| 1261 |
|
|
default rSFRDAT <= #1 rSFRDAT;
|
| 1262 |
|
|
endcase // case(rDWBADR)
|
| 1263 |
|
|
end
|
| 1264 |
|
|
|
| 1265 |
|
|
wire wSFRSTB = (rDWBADR[15:6] == 10'h3FF);
|
| 1266 |
|
|
always @(posedge clk or negedge qrst)
|
| 1267 |
|
|
if (!qrst) begin
|
| 1268 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1269 |
|
|
rSFRSTB <= 1'h0;
|
| 1270 |
|
|
// End of automatics
|
| 1271 |
|
|
end else if (rDWBSTB & rNSKP) begin
|
| 1272 |
|
|
case (rDWBADR[5:0])
|
| 1273 |
|
|
aFSR2L[5:0],aFSR2H[5:0],aFSR1L[5:0],aFSR1H[5:0],aFSR0H[5:0],aFSR0L[5:0],
|
| 1274 |
|
|
aWDTCON[5:0],aBSR[5:0],aWREG[5:0],aSTATUS[5:0],
|
| 1275 |
|
|
aPRODL[5:0],aPRODH[5:0],aPRNG[5:0],
|
| 1276 |
|
|
aTABLAT[5:0],aTBLPTRH[5:0],aTBLPTRU[5:0],aTBLPTRL[5:0],
|
| 1277 |
|
|
aPCL[5:0],aPCLATH[5:0],aPCLATU[5:0],
|
| 1278 |
|
|
aSTKPTR[5:0],aTOSU[5:0],aTOSH[5:0],aTOSL[5:0]: rSFRSTB <= #1 wSFRSTB;
|
| 1279 |
|
|
default rSFRSTB <= #1 1'b0;
|
| 1280 |
|
|
endcase // case(rDWBADR)
|
| 1281 |
|
|
end
|
| 1282 |
|
|
|
| 1283 |
|
|
// WDTCON
|
| 1284 |
|
|
always @(posedge clk or negedge qrst)
|
| 1285 |
|
|
if (!qrst)
|
| 1286 |
|
|
rSWDTEN <= 1;
|
| 1287 |
|
|
else if (qena[3] & rNSKP)
|
| 1288 |
|
|
rSWDTEN <= #1 ((rDWBADR == aWDTCON) & rDWBWE) ? rRESULT[0] : rSWDTEN;
|
| 1289 |
|
|
|
| 1290 |
|
|
// TOSH, TOSU, TOSL, STKPTR
|
| 1291 |
|
|
wire [5:0] wSTKINC = rSTKPTR + 1;
|
| 1292 |
|
|
wire [5:0] wSTKDEC = rSTKPTR - 1;
|
| 1293 |
|
|
|
| 1294 |
|
|
always @(posedge clk or negedge qrst)
|
| 1295 |
|
|
if (!qrst) begin
|
| 1296 |
|
|
/*AUTORESET*/
|
| 1297 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1298 |
|
|
rSTKPTR_ <= 6'h0;
|
| 1299 |
|
|
// End of automatics
|
| 1300 |
|
|
end else if (qena[0]) begin
|
| 1301 |
|
|
rSTKPTR_ <= #1 wSTKINC;
|
| 1302 |
|
|
end
|
| 1303 |
|
|
|
| 1304 |
|
|
always @(posedge clk or negedge qrst)
|
| 1305 |
|
|
if (!qrst) begin
|
| 1306 |
|
|
/*AUTORESET*/
|
| 1307 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1308 |
|
|
rSTKFUL <= 1'h0;
|
| 1309 |
|
|
rSTKPTR <= 6'h0;
|
| 1310 |
|
|
rSTKUNF <= 1'h0;
|
| 1311 |
|
|
// End of automatics
|
| 1312 |
|
|
end else if (qrun & rNSKP) begin
|
| 1313 |
|
|
rSTKFUL <= #1 (wSTKINC == 6'h20);
|
| 1314 |
|
|
rSTKUNF <= #1 (wSTKDEC == 6'h3F);
|
| 1315 |
|
|
case (qfsm)
|
| 1316 |
|
|
FSM_Q3: begin
|
| 1317 |
|
|
rSTKPTR <= #1 ((rDWBADR == aSTKPTR) & rDWBWE) ? rRESULT : rSTKPTR;
|
| 1318 |
|
|
end
|
| 1319 |
|
|
FSM_Q2: begin
|
| 1320 |
|
|
case (rMXSTK)
|
| 1321 |
|
|
MXSTK_PUSH: begin
|
| 1322 |
|
|
rSTKPTR <= #1 (rSTKFUL) ? rSTKPTR : wSTKINC;
|
| 1323 |
|
|
end
|
| 1324 |
|
|
MXSTK_POP: begin
|
| 1325 |
|
|
rSTKPTR <= #1 (rSTKUNF) ? rSTKPTR : wSTKDEC;
|
| 1326 |
|
|
end
|
| 1327 |
|
|
default: begin
|
| 1328 |
|
|
rSTKPTR <= #1 rSTKPTR;
|
| 1329 |
|
|
end
|
| 1330 |
|
|
endcase // case(rMXSTK)
|
| 1331 |
|
|
end // case: FSM_Q2
|
| 1332 |
|
|
default: begin
|
| 1333 |
|
|
rSTKPTR <= #1 rSTKPTR;
|
| 1334 |
|
|
end
|
| 1335 |
|
|
endcase // case(qfsm)
|
| 1336 |
|
|
end // if (qrun & rNSKP)
|
| 1337 |
|
|
|
| 1338 |
|
|
always @(posedge clk or negedge qrst)
|
| 1339 |
|
|
if (!qrst) begin
|
| 1340 |
|
|
/*AUTORESET*/
|
| 1341 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1342 |
|
|
rTOSH <= 8'h0;
|
| 1343 |
|
|
rTOSL <= 8'h0;
|
| 1344 |
|
|
rTOSU <= 8'h0;
|
| 1345 |
|
|
// End of automatics
|
| 1346 |
|
|
end else if (qrun & rNSKP)
|
| 1347 |
|
|
case (qfsm)
|
| 1348 |
|
|
FSM_Q3: begin
|
| 1349 |
|
|
rTOSU <= #1 ((rDWBADR == aTOSU) & rDWBWE) ? rRESULT : rTOSU;
|
| 1350 |
|
|
rTOSH <= #1 ((rDWBADR == aTOSH) & rDWBWE) ? rRESULT : rTOSH;
|
| 1351 |
|
|
rTOSL <= #1 ((rDWBADR == aTOSL) & rDWBWE) ? rRESULT : rTOSL;
|
| 1352 |
|
|
end
|
| 1353 |
|
|
FSM_Q2: begin
|
| 1354 |
|
|
case (rMXSTK)
|
| 1355 |
|
|
MXSTK_PUSH: begin
|
| 1356 |
|
|
{rTOSU,rTOSH,rTOSL} <= #1 {wPCLAT,1'b0};
|
| 1357 |
|
|
end
|
| 1358 |
|
|
MXSTK_POP: begin
|
| 1359 |
|
|
{rTOSU,rTOSH,rTOSL} <= #1 wSTKR;
|
| 1360 |
|
|
end
|
| 1361 |
|
|
default: begin
|
| 1362 |
|
|
rTOSU <= #1 rTOSU;
|
| 1363 |
|
|
rTOSH <= #1 rTOSH;
|
| 1364 |
|
|
rTOSL <= #1 rTOSL;
|
| 1365 |
|
|
end
|
| 1366 |
|
|
endcase // case(rMXSTK)
|
| 1367 |
|
|
end // case: FSM_Q2
|
| 1368 |
|
|
default: begin
|
| 1369 |
|
|
rTOSU <= #1 rTOSU;
|
| 1370 |
|
|
rTOSH <= #1 rTOSH;
|
| 1371 |
|
|
rTOSL <= #1 rTOSL;
|
| 1372 |
|
|
end
|
| 1373 |
|
|
endcase // case(qfsm)
|
| 1374 |
|
|
|
| 1375 |
|
|
|
| 1376 |
|
|
// SHADOW REGISTERS
|
| 1377 |
|
|
always @(posedge clk or negedge qrst)
|
| 1378 |
|
|
if (!qrst) begin
|
| 1379 |
|
|
/*AUTORESET*/
|
| 1380 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1381 |
|
|
rBSR_ <= 8'h0;
|
| 1382 |
|
|
rSTATUS_ <= 5'h0;
|
| 1383 |
|
|
rWREG_ <= 8'h0;
|
| 1384 |
|
|
// End of automatics
|
| 1385 |
|
|
end else if (qena[3] & rNSKP) begin
|
| 1386 |
|
|
rWREG_ <= #1 (rMXSHA == MXSHA_CALL) ? rWREG : rWREG_;
|
| 1387 |
|
|
rBSR_ <= #1 (rMXSHA == MXSHA_CALL) ? rBSR : rBSR_;
|
| 1388 |
|
|
rSTATUS_ <= #1 (rMXSHA == MXSHA_CALL) ? {rN,rOV,rZ,rDC,rC} : rSTATUS_;
|
| 1389 |
|
|
end
|
| 1390 |
|
|
|
| 1391 |
|
|
// STATUS
|
| 1392 |
|
|
reg [2:0] rMXSTAL;
|
| 1393 |
|
|
always @(negedge clk or negedge qrst)
|
| 1394 |
|
|
if (!qrst)
|
| 1395 |
|
|
/*AUTORESET*/
|
| 1396 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1397 |
|
|
rMXSTAL <= 3'h0;
|
| 1398 |
|
|
// End of automatics
|
| 1399 |
|
|
else if (qena[3])
|
| 1400 |
|
|
rMXSTAL <= #1 rMXSTA;
|
| 1401 |
|
|
|
| 1402 |
|
|
always @(posedge clk or negedge qrst)
|
| 1403 |
|
|
if (!qrst) begin
|
| 1404 |
|
|
/*AUTORESET*/
|
| 1405 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1406 |
|
|
rC <= 1'h0;
|
| 1407 |
|
|
rDC <= 1'h0;
|
| 1408 |
|
|
rN <= 1'h0;
|
| 1409 |
|
|
rOV <= 1'h0;
|
| 1410 |
|
|
rZ <= 1'h0;
|
| 1411 |
|
|
// End of automatics
|
| 1412 |
|
|
end else if (qrun & rNSKP) begin
|
| 1413 |
|
|
case (qfsm)
|
| 1414 |
|
|
default: {rN,rOV,rZ,rDC,rC} <= #1 ((rDWBADR == aSTATUS) & rDWBWE) ? rRESULT : {rN,rOV,rZ,rDC,rC};
|
| 1415 |
|
|
FSM_Q2: {rN,rOV,rZ,rDC,rC} <= #1 (rMXSHA == MXSHA_RET) ? rSTATUS_ : {rN,rOV,rZ,rDC,rC};
|
| 1416 |
|
|
FSM_Q0: case (rMXSTAL)
|
| 1417 |
|
|
MXSTA_ALL: {rN,rOV,rZ,rDC,rC} <= #1 {wN,wOV,wZ,wDC,wC};
|
| 1418 |
|
|
MXSTA_CZN: {rN,rOV,rZ,rDC,rC} <= #1 {wN,rOV,wZ,rDC,wC};
|
| 1419 |
|
|
MXSTA_ZN: {rN,rOV,rZ,rDC,rC} <= #1 {wN,rOV,wZ,rDC,rC};
|
| 1420 |
|
|
MXSTA_Z: {rN,rOV,rZ,rDC,rC} <= #1 {rN,rOV,wZ,rDC,rC};
|
| 1421 |
|
|
MXSTA_C: {rN,rOV,rZ,rDC,rC} <= #1 {rN,rOV,rZ,rDC,wC};
|
| 1422 |
|
|
default: {rN,rOV,rZ,rDC,rC} <= #1 {rN,rOV,rZ,rDC,rC};
|
| 1423 |
|
|
endcase // case(rMXSTA)
|
| 1424 |
|
|
endcase // case(qfsm)
|
| 1425 |
|
|
end // if (qena[3] & rNSKP)
|
| 1426 |
|
|
|
| 1427 |
|
|
// WREG
|
| 1428 |
|
|
// TODO: DAW
|
| 1429 |
|
|
wire [7:0] wDAW = ((rMXALU == MXALU_DAW) & (rMXDST == MXDST_EXT)) ? 8'h00 : rWREG;
|
| 1430 |
|
|
always @(posedge clk or negedge qrst)
|
| 1431 |
|
|
if (!qrst) begin
|
| 1432 |
|
|
/*AUTORESET*/
|
| 1433 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1434 |
|
|
rWREG <= 8'h0;
|
| 1435 |
|
|
// End of automatics
|
| 1436 |
|
|
end else if (qena[3] & rNSKP) begin
|
| 1437 |
|
|
rWREG <= #1 (((rDWBADR == aWREG) & rDWBWE) | (rMXDST == MXDST_WREG)) ? rRESULT :
|
| 1438 |
|
|
(rMXSHA == MXSHA_RET) ? rWREG_ :
|
| 1439 |
|
|
rWREG;
|
| 1440 |
|
|
end
|
| 1441 |
|
|
|
| 1442 |
|
|
// BSR
|
| 1443 |
|
|
always @(posedge clk or negedge qrst)
|
| 1444 |
|
|
if (!qrst) begin
|
| 1445 |
|
|
/*AUTORESET*/
|
| 1446 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1447 |
|
|
rBSR <= 8'h0;
|
| 1448 |
|
|
// End of automatics
|
| 1449 |
|
|
end else if (qrun & rNSKP)
|
| 1450 |
|
|
case (qfsm)
|
| 1451 |
|
|
FSM_Q3: rBSR <= #1 (((rDWBADR == aBSR) & rDWBWE)) ? rRESULT :
|
| 1452 |
|
|
(rMXSHA == MXSHA_RET) ? rBSR_ :
|
| 1453 |
|
|
rBSR;
|
| 1454 |
|
|
default: rBSR <= #1 ((rMXALU == MXALU_MOVLB) & (rMXDST == MXDST_EXT)) ? rIREG[7:0] : rBSR;
|
| 1455 |
|
|
endcase // case(qfsm)
|
| 1456 |
|
|
|
| 1457 |
|
|
// FSRXH/FSRXL
|
| 1458 |
|
|
wire [DSIZ-1:0] wFSRDEC0 = {rFSR0H,rFSR0L} - 1;
|
| 1459 |
|
|
wire [DSIZ-1:0] wFSRDEC1 = {rFSR1H,rFSR1L} - 1;
|
| 1460 |
|
|
wire [DSIZ-1:0] wFSRDEC2 = {rFSR2H,rFSR2L} - 1;
|
| 1461 |
|
|
|
| 1462 |
|
|
always @(posedge clk or negedge qrst)
|
| 1463 |
|
|
if (!qrst) begin
|
| 1464 |
|
|
/*AUTORESET*/
|
| 1465 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1466 |
|
|
rFSR0H <= 8'h0;
|
| 1467 |
|
|
rFSR0L <= 8'h0;
|
| 1468 |
|
|
rFSR1H <= 8'h0;
|
| 1469 |
|
|
rFSR1L <= 8'h0;
|
| 1470 |
|
|
rFSR2H <= 8'h0;
|
| 1471 |
|
|
rFSR2L <= 8'h0;
|
| 1472 |
|
|
// End of automatics
|
| 1473 |
|
|
end else if (qrun & rNSKP) // if (!qrst)
|
| 1474 |
|
|
case (qfsm)
|
| 1475 |
|
|
FSM_Q3: begin
|
| 1476 |
|
|
rFSR0H <= #1 (((rDWBADR == aFSR0H) & rDWBWE)) ? rRESULT : rFSR0H;
|
| 1477 |
|
|
rFSR0L <= #1 (((rDWBADR == aFSR0L) & rDWBWE)) ? rRESULT : rFSR0L;
|
| 1478 |
|
|
rFSR1H <= #1 (((rDWBADR == aFSR1H) & rDWBWE)) ? rRESULT : rFSR1H;
|
| 1479 |
|
|
rFSR1L <= #1 (((rDWBADR == aFSR1L) & rDWBWE)) ? rRESULT : rFSR1L;
|
| 1480 |
|
|
rFSR2H <= #1 (((rDWBADR == aFSR2H) & rDWBWE)) ? rRESULT : rFSR2H;
|
| 1481 |
|
|
rFSR2L <= #1 (((rDWBADR == aFSR2L) & rDWBWE)) ? rRESULT : rFSR2L;
|
| 1482 |
|
|
end
|
| 1483 |
|
|
FSM_Q2: begin
|
| 1484 |
|
|
// Post Inc/Dec
|
| 1485 |
|
|
case (rMXFSR)
|
| 1486 |
|
|
MXFSR_POSTINC0: {rFSR0H,rFSR0L} <= #1 wFSRINC0;
|
| 1487 |
|
|
MXFSR_POSTINC1: {rFSR1H,rFSR1L} <= #1 wFSRINC1;
|
| 1488 |
|
|
MXFSR_POSTINC2: {rFSR2H,rFSR2L} <= #1 wFSRINC2;
|
| 1489 |
|
|
MXFSR_POSTDEC0: {rFSR0H,rFSR0L} <= #1 wFSRDEC0;
|
| 1490 |
|
|
MXFSR_POSTDEC1: {rFSR1H,rFSR1L} <= #1 wFSRDEC1;
|
| 1491 |
|
|
MXFSR_POSTDEC2: {rFSR2H,rFSR2L} <= #1 wFSRDEC2;
|
| 1492 |
|
|
endcase // case(rMXFSR)
|
| 1493 |
|
|
end // case: FSM_Q2
|
| 1494 |
|
|
FSM_Q1: begin
|
| 1495 |
|
|
// Load Literals
|
| 1496 |
|
|
if ((rMXALU == MXALU_LFSR) & (rMXDST == MXDST_EXT))
|
| 1497 |
|
|
case (rIREG[5:4])
|
| 1498 |
|
|
2'o0: {rFSR0H,rFSR0L} <= #1 {rIREG[3:0],rROMLAT[7:0]};
|
| 1499 |
|
|
2'o1: {rFSR1H,rFSR1L} <= #1 {rIREG[3:0],rROMLAT[7:0]};
|
| 1500 |
|
|
2'o2: {rFSR2H,rFSR2L} <= #1 {rIREG[3:0],rROMLAT[7:0]};
|
| 1501 |
|
|
endcase // case(rIREG[5:4])
|
| 1502 |
|
|
end // case: FSM_Q1
|
| 1503 |
|
|
|
| 1504 |
|
|
FSM_Q0: begin
|
| 1505 |
|
|
// Pre inc
|
| 1506 |
|
|
case (rMXFSR)
|
| 1507 |
|
|
MXFSR_PREINC0: {rFSR0H,rFSR0L} <= #1 wFSRINC0;
|
| 1508 |
|
|
MXFSR_PREINC1: {rFSR1H,rFSR1L} <= #1 wFSRINC1;
|
| 1509 |
|
|
MXFSR_PREINC2: {rFSR2H,rFSR2L} <= #1 wFSRINC2;
|
| 1510 |
|
|
endcase // case(rMXFSR)
|
| 1511 |
|
|
end
|
| 1512 |
|
|
|
| 1513 |
|
|
endcase // case(qfsm)
|
| 1514 |
|
|
|
| 1515 |
|
|
|
| 1516 |
|
|
// PRODH/PRODL
|
| 1517 |
|
|
wire [15:0] wPRODUCT = ((rMXALU == MXALU_MUL) & (rMXDST == MXDST_EXT)) ? (rSRC * rTGT) : {rPRODH,rPRODL};
|
| 1518 |
|
|
always @(posedge clk or negedge qrst)
|
| 1519 |
|
|
if (!qrst) begin
|
| 1520 |
|
|
/*AUTORESET*/
|
| 1521 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1522 |
|
|
rPRODH <= 8'h0;
|
| 1523 |
|
|
rPRODL <= 8'h0;
|
| 1524 |
|
|
// End of automatics
|
| 1525 |
|
|
end else if (qena[3] & rNSKP) begin
|
| 1526 |
|
|
rPRODH <= #1 (((rDWBADR == aPRODH) & rDWBWE)) ? rRESULT : wPRODUCT[15:8];
|
| 1527 |
|
|
rPRODL <= #1 (((rDWBADR == aPRODL) & rDWBWE)) ? rRESULT : wPRODUCT[7:0];
|
| 1528 |
|
|
end
|
| 1529 |
|
|
|
| 1530 |
|
|
// TBLATU/TBLATH/TBLATL
|
| 1531 |
|
|
wire [ISIZ-1:0] wTBLINC = {rTBLPTRU,rTBLPTRH,rTBLPTRL} + 1;
|
| 1532 |
|
|
wire [ISIZ-1:0] wTBLAT = {rTBLPTRU,rTBLPTRH,rTBLPTRL};
|
| 1533 |
|
|
wire [ISIZ-1:0] wTBLDEC = {rTBLPTRU,rTBLPTRH,rTBLPTRL} - 1;
|
| 1534 |
|
|
always @(posedge clk or negedge qrst)
|
| 1535 |
|
|
if (!qrst) begin
|
| 1536 |
|
|
/*AUTORESET*/
|
| 1537 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1538 |
|
|
rTBLPTRH <= 8'h0;
|
| 1539 |
|
|
rTBLPTRL <= 8'h0;
|
| 1540 |
|
|
rTBLPTRU <= 8'h0;
|
| 1541 |
|
|
// End of automatics
|
| 1542 |
|
|
end else if (qrun & rNSKP)
|
| 1543 |
|
|
case (qfsm)
|
| 1544 |
|
|
FSM_Q0: {rTBLPTRU,rTBLPTRH,rTBLPTRL} <= #1 ((rMXTBL == MXTBL_WTPRE) | (rMXTBL == MXTBL_RDPRE)) ? wTBLINC : wTBLAT;
|
| 1545 |
|
|
FSM_Q2: {rTBLPTRU,rTBLPTRH,rTBLPTRL} <= #1 ((rMXTBL == MXTBL_WTINC) | (rMXTBL == MXTBL_RDINC)) ? wTBLINC :
|
| 1546 |
|
|
((rMXTBL == MXTBL_WTDEC) | (rMXTBL == MXTBL_RDDEC)) ? wTBLDEC : wTBLAT;
|
| 1547 |
|
|
default: begin
|
| 1548 |
|
|
rTBLPTRU <= #1 ((rDWBADR == aTBLPTRU) & rDWBWE) ? rRESULT : rTBLPTRU;
|
| 1549 |
|
|
rTBLPTRH <= #1 ((rDWBADR == aTBLPTRH) & rDWBWE) ? rRESULT : rTBLPTRH;
|
| 1550 |
|
|
rTBLPTRL <= #1 ((rDWBADR == aTBLPTRL) & rDWBWE) ? rRESULT : rTBLPTRL;
|
| 1551 |
|
|
end
|
| 1552 |
|
|
endcase // case(qfsm)
|
| 1553 |
|
|
|
| 1554 |
|
|
// TABLAT
|
| 1555 |
|
|
always @(posedge clk or negedge qrst)
|
| 1556 |
|
|
if (!qrst) begin
|
| 1557 |
|
|
/*AUTORESET*/
|
| 1558 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1559 |
|
|
rTABLAT <= 8'h0;
|
| 1560 |
|
|
// End of automatics
|
| 1561 |
|
|
end else if (qena[3] & rNSKP)
|
| 1562 |
|
|
case (rMXTBL)
|
| 1563 |
|
|
MXTBL_RD,MXTBL_RDINC,MXTBL_RDDEC,MXTBL_RDPRE:
|
| 1564 |
|
|
rTABLAT <= #1 rILAT;
|
| 1565 |
|
|
default: rTABLAT <= #1 (rDWBWE & (rDWBADR == aTABLAT)) ? rRESULT : rTABLAT;
|
| 1566 |
|
|
endcase // case(rMXTBL)
|
| 1567 |
|
|
|
| 1568 |
|
|
// PCLATU/PCLATH
|
| 1569 |
|
|
always @(posedge clk or negedge qrst)
|
| 1570 |
|
|
if (!qrst) begin
|
| 1571 |
|
|
/*AUTORESET*/
|
| 1572 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1573 |
|
|
rPCLATH <= 8'h0;
|
| 1574 |
|
|
rPCLATU <= 8'h0;
|
| 1575 |
|
|
// End of automatics
|
| 1576 |
|
|
end else if (qena[3] & rNSKP) begin
|
| 1577 |
|
|
rPCLATU <= #1 ((rDWBADR == aPCLATU) & rDWBWE) ? rRESULT :
|
| 1578 |
|
|
((rDWBADR == aPCL) & ~rDWBWE) ? rPCU :
|
| 1579 |
|
|
rPCLATU;
|
| 1580 |
|
|
rPCLATH <= #1 ((rDWBADR == aPCLATH) & rDWBWE) ? rRESULT :
|
| 1581 |
|
|
((rDWBADR == aPCL) & ~rDWBWE) ? rPCH :
|
| 1582 |
|
|
rPCLATH;
|
| 1583 |
|
|
end
|
| 1584 |
|
|
|
| 1585 |
|
|
// PCU/PCH/PCL
|
| 1586 |
|
|
always @(negedge clk or negedge qrst)
|
| 1587 |
|
|
if (!qrst) begin
|
| 1588 |
|
|
/*AUTORESET*/
|
| 1589 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 1590 |
|
|
rPCH <= 8'h0;
|
| 1591 |
|
|
rPCL <= 8'h0;
|
| 1592 |
|
|
rPCU <= 5'h0;
|
| 1593 |
|
|
// End of automatics
|
| 1594 |
|
|
end else if (qena[3]) begin
|
| 1595 |
|
|
{rPCU,rPCH,rPCL} <= #1 ((rDWBADR == aPCL) & rDWBWE) ? {rPCLATU,rPCLATH,rRESULT} :
|
| 1596 |
|
|
{rPCNXT,1'b0};
|
| 1597 |
|
|
end
|
| 1598 |
|
|
|
| 1599 |
|
|
endmodule // ae18_core
|
