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[/] [ae18/] [trunk/] [sw/] [asm/] [ae18_core.asm] - Blame information for rev 2

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;;;
;;; Copyright (C) 2006 Shawn Tan Ser Ngiap 
;;;
;;; This library is free software; you can redistribute it and/or modify it
;;; under the terms of the GNU Lesser General Public License as published by
;;; the Free Software Foundation; either version 2.1 of the License,
;;; or (at your option) any later version.
;;;
;;; This library is distributed in the hope that it will be useful, but
;;; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
;;; License for more details.
;;;
;;; You should have received a copy of the GNU Lesser General Public License
;;; along with this library; if not, write to the Free Software Foundation, Inc.,
;;; 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;;
;;; DESCRIPTION
;;; This file contains a simple test programme to test the functionality of
;;; the AE18 core. It is by no means an exhaustive test. However, it does
;;; perform at least each PIC18 command at least once. This file has been
;;; compiled using GPASM and GPLINK.
;;;
;;; 2006-12-27
;;; Passes ALL tests.
;;;
 
        include "p18f452.inc"
 
        processor p18f452
        radix   hex
 
_RAM    udata   0x020
reg0    res     1
reg1    res     1
reg2    res     2
_FSR    udata   0x100
fsr0    res     10
fsr1    res     10
fsr2    res     10
 
_RESET  code    0x0000
        goto    _START_TEST
_ERROR:
        goto    $
 
_ISRH   code    0x08
        goto    _ISRH_TEST
 
_ISRL   code    0x018
        goto    _ISRL_TEST
 
_MAIN   code    0x0020
 
        ;;
        ;; MAIN test code loop
        ;; Calls a series of test subroutines. Ends with a SLEEP.
        ;;
_START_TEST:
        ;; Clear WDT
        clrwdt
 
        rcall   _NPC_TEST
        rcall   _LW2W_TEST
        rcall   _BSR_TEST
        rcall   _F2F_TEST
        rcall   _FW2W_TEST
        rcall   _FW2F_TEST
        rcall   _SKIP_TEST
        rcall   _BCC_TEST
        rcall   _C_TEST
        rcall   _MUL_TEST
        rcall   _BIT_TEST
        rcall   _N2F_TEST
        rcall   _FSR_TEST
        rcall   _SHA_TEST
        rcall   _TBL_TEST
 
 
        ;; All tests OK!!
        sleep
 
        ;; BUGFIX! : Two NOPs required after SLEEP command.
        nop
        nop
 
        ;; RESET on wake up
        reset
 
        ;; Infinite Loop. It should NEVER loop.
        bra     $
 
        ;;
        ;; TABLE tests - OK
        ;; Tests to check that TBLWT/TBLRD are working
        ;;
_TBL_TEST:
        tblrd*+                 ; TABLAT = 10
        tblrd*+                 ; TABLAT = EF
        tblrd*+                 ; TABLAT = 00
        tblrd*+                 ; TABLAT = FF
        retlw   0x00
 
        ;;
        ;; SHADOW test - OK
        ;; Tests to make sure that CALL,S and RETURN,S are working
        ;;
_SHA_TEST:
        movlw   0xA5            ; WREG = 0xA5
        call    _SHA0,1
        xorlw   0xA5            ; Z = 1
        bnz     $
        retlw   0x00
_SHA0:
        movlw   0x00            ; WREG = 0x00
        xorlw   0x00            ; Z = 1
        bnz     $
        return  1               ; WREG = 0xA5
 
        ;;
        ;; FSR test - OK
        ;; Uses INDF0/INDF1/INDF2 for moving values around
        ;;
_FSR_TEST:
        lfsr    2,fsr2
        lfsr    1,fsr1
        lfsr    0,fsr0
 
        movlw   0xA5
        movwf   INDF0           ; FSR2 = A5
        movff   fsr0,reg0       ; REG2 = FSR2
        xorwf   reg0,W          ; Z = 1
        bnz     $
 
        movlw   0xB6
        movwf   INDF1
        movff   fsr1,reg1
        xorwf   reg1,W
        bnz     $
 
        movlw   0xC7
        movwf   INDF2
        movff   fsr2,reg2
        xorwf   reg2,W
        bnz     $
 
        retlw   0x00
 
        ;;
        ;; SETF/NEGF/CLRF tests - OK
        ;; Miscellaneous mono op operations
        ;;
_N2F_TEST:
        clrf    reg0            ; Z = 1, N = 0
        movf    reg0,F
        bnz     $
        bn      $
        setf    reg0            ; Z = 0, N = 1
        movf    reg0,F
        bz      $
        bnn     $
        negf    reg0            ; REG0 = 0x01
        movf    reg0,F
        bz      $
        bn      $
        retlw   0x00
 
        ;;
        ;; BCC test - OK
        ;; Tests all the Z/N/C/OV conditional branches for
        ;; positive and negative results
        ;;
_BCC_TEST:
        ;; Positive tests
        movlw   0x01
        movwf   reg0            ; REG0 = 0x01
 
        rrcf    reg0,W          ; C = 1, WREG = 0x00
        bc      $+4
        bra     $
        rlcf    reg0,W          ; C = 0, WREG = 0x02
        bnc     $+4
        bra     $
 
        andlw   0x00            ; Z = 1
        bz      $+4
        bra     $
        iorlw   0x01            ; Z = 0
        bnz     $+4
        bra     $
 
        xorlw   0x81            ; N = 1
        bn      $+4
        bra     $
        xorlw   0x80            ; N = 0
        bnn     $+4
        bra     $
 
        ;; Negative test
        movlw   0x00            ; WREG = 0
        addlw   0x00            ; WREG = 0, C = 0
        iorlw   0xFF            ; Z = 0, N = 1
        bz      $
        bnn     $
        bc      $
 
        addlw   0x01            ; C = 1, Z = 1, N = 0
        bnc     $
        bnz     $
        bn      $
 
        ;; Test OV
        movlw   0x80
        addlw   0x80            ; C = 1, OV = 1, N = 0, Z = 1
        bnov    $
        bov     $+4
        bra     $
        retlw   0x00
 
        ;;
        ;; BSR test - OK
        ;; Simple test to check that BSR is working
        ;;
_BSR_TEST:
        movlw   0xA5            ; WREG = 0xA5
        movlb   0x02            ; BSR = 0x02
        movwf   0x00,B          ; (0x0200) = 0xA5
        movff   0x0200, 0x0000  ; (0x0000) = 0xA5
        swapf   0x0000,W        ; WREG = 0x5A;
        xorlw   0x5A            ; WREG = 0, Z = 1
        bnz     $
        retlw   0x00
 
        ;;
        ;; C used instruction tests
        ;; Tests a series of instructions that use C
        ;; TODO - verify
_C_TEST:
        movlw   0xFF            ; Indicate Start
        movlw   0x00
        addlw   0x00            ; C = 0
        movwf   reg2            ; REG2 = 0
 
        movlw   0x80            ; WREG = 0x80, C = 0
        addlw   0x80            ; WREG = 0x00, C = 1
        rrcf    reg2,W          ; WREG = 0x80, C = 0;
        addlw   0x80            ; WREG = 0x00, C = 1;
        rlcf    reg2,W          ; WREG = 0x01, C = 0;
 
        addlw   0xFF            ; WREG = 0x00, C = 1;
        addwfc  reg2,W          ; WREG = 0x01, C = 0;
 
        subwfb  reg2,W          ; WREG = 0xFE, C = 1;
        addwfc  reg2,W          ; WREG = 0xFF, C = 0;
        subfwb  reg2,W          ; WREG = 0xFE, C = 0;
 
        retlw   0x00
 
        ;;
        ;; SKIP tests - OK
        ;; Tests the various SNZ/SZ/SEQ/SGT/SLT instructions
        ;;
_SKIP_TEST:
        movlw   0x01            ; WREG = 0x01
        movwf   reg0            ; REG0 = 0x01
 
        btfss   reg0,0
        bra     $
        btfsc   reg0,1
        bra     $
 
        decfsz  reg0,f          ; REG0 = 0x00
        bra     $
        dcfsnz  reg0,f          ; REG0 = 0xFF
        bra     $
        incfsz  reg0,f          ; REG0 = 0x00
        bra     $
        infsnz  reg0,f          ; REG0 = 0x01
        bra     $
 
        cpfseq  reg0
        bra     $
        movlw   0x00            ; WREG = 0x00
        cpfsgt  reg0
        bra     $
        movlw   0x02
        cpfslt  reg0
        bra     $
 
        movlw   0x00
        movwf   reg2
        tstfsz  reg2
        bra     $
 
        retlw   0x00
 
        ;;
        ;; FILE * WREG => FILE tests - OK
        ;; Tests the series of byte file operations
        ;;
_FW2F_TEST:
        movlw   0xA5            ; WREG = 0xA5
        movwf   reg2            ; REG2 = 0xA5
 
        swapf   reg2,F          ; REG2 = 0x5A
        andwf   reg2,F          ; REG2 = 0x00
        iorwf   reg2,F          ; REG2 = 0xA5
        xorwf   reg2,F          ; REG2 = 0x00
 
        addwf   reg2,F          ; REG2 = 0xA5
        subwf   reg2,F          ; REG2 = 0x00
 
        movwf   reg2            ; REG2 = 0xA5
        rrncf   reg2,F          ; REG2 = 0xD2
        rlncf   reg2,F          ; REG2 = 0xA5
 
        comf    reg2,F          ; REG2 = 0x5A
        incf    reg2,F          ; REG2 = 0x5B
        decf    reg2,F          ; REG2 = 0x5A
 
        xorwf   reg2,W          ; WREG = 0x00
        bnz     $
        retlw   0x00
 
        ;;
        ;; FILE * WREG => WREG test - OK
        ;; Tests the series of byte file operations
        ;;
_FW2W_TEST:
        movlw   0xA5            ; WREG = 0xA5
        movwf   reg2            ; REG2 = 0xA5
 
        swapf   reg2,W          ; WREG = 0x5A
        andwf   reg2,W          ; WREG = 0x00
        iorwf   reg2,W          ; WREG = 0xA5
        xorwf   reg2,W          ; WREG = 0x00
 
        addwf   reg2,W          ; WREG = 0xA5
        subwf   reg2,W          ; WREG = 0x00
 
        rrncf   reg2,W          ; WREG = 0xD2
        rlncf   reg2,W          ; WREG = 0x4B
 
        comf    reg2,W          ; WREG = 0x5A
        incf    reg2,W          ; WREG = 0xA6
        decf    reg2,W          ; WREG = 0xA4
 
        xorlw   0xA4
        bnz     $
        retlw   0x00            ; WREG = 0x0
 
        ;;
        ;; MOVE FILE=>WREG/FILE=>FILE/WREG=>FILE tests - OK
        ;; Tests moves between FILE and WREG
        ;;
_F2F_TEST:
        movlw   0xA5            ; WREG = 0xA5
        movwf   reg0            ; REG0 = 0xA5
        movlw   0x00            ; WREG = 0x00
        movff   reg0,reg1       ; REG1 = 0xA5
        movf    reg0,f          ; REG0 = 0xA5
        movf    reg1,w          ; WREG = 0xA5
        xorlw   0xA5
        bnz     $
        retlw   0x00
 
        ;;
        ;; BIT test - OK
        ;; Tests the sequence of BIT ops
        ;;
_BIT_TEST:
        movlw   0xA5            ; WREG = 0xA5
        movwf   reg2            ; REG2 = 0xA5
        bcf     reg2,0          ;
        movf    reg2,W          ; WREG = 0xA4
        bsf     reg2,0          ;
        movf    reg2,W          ; WREG = 0xA5
        btg     reg2,0          ;
        movf    reg2,W          ; WREG = 0xA4
        xorlw   0xA4            ; Z = 1
        bnz     $
        retlw   0x00
 
        ;;
        ;; LIT * WREG => WREG tests - OK
        ;; Tests that the sequence of literal operations
        ;;
_LW2W_TEST:
        movlw   0xA5            ; WREG = 0xA5
        addlw   0x05            ; WREG = 0xAA
        sublw   0xFF            ; WREG = 0x55
        andlw   0xF0            ; WREG = 0x50
        iorlw   0x0A            ; WREG = 0x5A
        xorlw   0xFF            ; WREG = 0xA5
        xorlw   0xA5
        bnz     $
        retlw   0x00            ; WREG = 0x00
 
        ;;
        ;; NEAR test - OK
        ;; Tests the ability to perform BRA and RCALL by doing some
        ;; jump acrobatics.
        ;;
_NPC_TEST:
        bra     _NTFWD
        goto    $               ; Forward Jump
_NTFWD: bra     _NTBWD
_NTRET: return
        goto    $
_NTBWD: bra     _NTRET          ; Backward Jump
        goto    $
 
        ;;
        ;; MULLW/MULWF tests - OK
        ;; Tests that the multiplier produces the correct results
        ;;
_MUL_TEST:
        movlw   0x0A            ; WREG = 0x0A
        movwf   reg0            ; REG0 = 0x0A
        mullw   0xA0            ; PRODH,PRODL = 0x0640
 
        movf    PRODH,W         ; Z = 0
        xorlw   0x06            ; Z = 1
        bnz     $
        movf    PRODL,W         ; Z = 0
        xorlw   0x40            ; Z = 1
        bnz     $
 
        movlw   0x40            ; WREG = 0x40
        mulwf   reg0            ; PRODH,PRODL = 0x0280
 
        movf    PRODH,W         ; Z = 0
        xorlw   0x02            ; Z = 1
        bnz     $
        movf    PRODL,W         ; Z = 0
        xorlw   0x80            ; Z = 1
        bnz     $
 
        retlw   0x00
 
        ;;
        ;; Interrupt Response Test - OK
        ;; Just check to see if it jumps here and returns correctly.
        ;;
_ISRH_TEST:
_ISRL_TEST:
        nop                     ; Do something
        retfie  1
 
        ;; Add some NOP at the end to avoid simulation error
        ;; due to XXXX content at memory locations outside
        ;; of the end of the programme.
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        end

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[/] [ae18/] [trunk/] [sw/] [asm/] [ae18_core.asm] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sybreon	`;;;`
2			`;;; Copyright (C) 2006 Shawn Tan Ser Ngiap`
3			`;;;`
4			`;;; This library is free software; you can redistribute it and/or modify it`
5			`;;; under the terms of the GNU Lesser General Public License as published by`
6			`;;; the Free Software Foundation; either version 2.1 of the License,`
7			`;;; or (at your option) any later version.`
8			`;;;`
9			`;;; This library is distributed in the hope that it will be useful, but`
10			`;;; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
11			`;;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
12			`;;; License for more details.`
13			`;;;`
14			`;;; You should have received a copy of the GNU Lesser General Public License`
15			`;;; along with this library; if not, write to the Free Software Foundation, Inc.,`
16			`;;; 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
17			`;;;`
18			`;;; DESCRIPTION`
19			`;;; This file contains a simple test programme to test the functionality of`
20			`;;; the AE18 core. It is by no means an exhaustive test. However, it does`
21			`;;; perform at least each PIC18 command at least once. This file has been`
22			`;;; compiled using GPASM and GPLINK.`
23			`;;;`
24			`;;; 2006-12-27`
25			`;;; Passes ALL tests.`
26			`;;;`
27
28			`include "p18f452.inc"`
29
30			`processor p18f452`
31			`radix hex`
32
33			`_RAM udata 0x020`
34			`reg0 res 1`
35			`reg1 res 1`
36			`reg2 res 2`
37			`_FSR udata 0x100`
38			`fsr0 res 10`
39			`fsr1 res 10`
40			`fsr2 res 10`
41
42			`_RESET code 0x0000`
43			`goto _START_TEST`
44			`_ERROR:`
45			`goto $`
46
47			`_ISRH code 0x08`
48			`goto _ISRH_TEST`
49
50			`_ISRL code 0x018`
51			`goto _ISRL_TEST`
52
53			`_MAIN code 0x0020`
54
55			`;;`
56			`;; MAIN test code loop`
57			`;; Calls a series of test subroutines. Ends with a SLEEP.`
58			`;;`
59			`_START_TEST:`
60			`;; Clear WDT`
61			`clrwdt`
62
63			`rcall _NPC_TEST`
64			`rcall _LW2W_TEST`
65			`rcall _BSR_TEST`
66			`rcall _F2F_TEST`
67			`rcall _FW2W_TEST`
68			`rcall _FW2F_TEST`
69			`rcall _SKIP_TEST`
70			`rcall _BCC_TEST`
71			`rcall _C_TEST`
72			`rcall _MUL_TEST`
73			`rcall _BIT_TEST`
74			`rcall _N2F_TEST`
75			`rcall _FSR_TEST`
76			`rcall _SHA_TEST`
77			`rcall _TBL_TEST`
78
79
80			`;; All tests OK!!`
81			`sleep`
82
83			`;; BUGFIX! : Two NOPs required after SLEEP command.`
84			`nop`
85			`nop`
86
87			`;; RESET on wake up`
88			`reset`
89
90			`;; Infinite Loop. It should NEVER loop.`
91			`bra $`
92
93			`;;`
94			`;; TABLE tests - OK`
95			`;; Tests to check that TBLWT/TBLRD are working`
96			`;;`
97			`_TBL_TEST:`
98			`tblrd*+ ; TABLAT = 10`
99			`tblrd*+ ; TABLAT = EF`
100			`tblrd*+ ; TABLAT = 00`
101			`tblrd*+ ; TABLAT = FF`
102			`retlw 0x00`
103
104			`;;`
105			`;; SHADOW test - OK`
106			`;; Tests to make sure that CALL,S and RETURN,S are working`
107			`;;`
108			`_SHA_TEST:`
109			`movlw 0xA5 ; WREG = 0xA5`
110			`call _SHA0,1`
111			`xorlw 0xA5 ; Z = 1`
112			`bnz $`
113			`retlw 0x00`
114			`_SHA0:`
115			`movlw 0x00 ; WREG = 0x00`
116			`xorlw 0x00 ; Z = 1`
117			`bnz $`
118			`return 1 ; WREG = 0xA5`
119
120			`;;`
121			`;; FSR test - OK`
122			`;; Uses INDF0/INDF1/INDF2 for moving values around`
123			`;;`
124			`_FSR_TEST:`
125			`lfsr 2,fsr2`
126			`lfsr 1,fsr1`
127			`lfsr 0,fsr0`
128
129			`movlw 0xA5`
130			`movwf INDF0 ; FSR2 = A5`
131			`movff fsr0,reg0 ; REG2 = FSR2`
132			`xorwf reg0,W ; Z = 1`
133			`bnz $`
134
135			`movlw 0xB6`
136			`movwf INDF1`
137			`movff fsr1,reg1`
138			`xorwf reg1,W`
139			`bnz $`
140
141			`movlw 0xC7`
142			`movwf INDF2`
143			`movff fsr2,reg2`
144			`xorwf reg2,W`
145			`bnz $`
146
147			`retlw 0x00`
148
149			`;;`
150			`;; SETF/NEGF/CLRF tests - OK`
151			`;; Miscellaneous mono op operations`
152			`;;`
153			`_N2F_TEST:`
154			`clrf reg0 ; Z = 1, N = 0`
155			`movf reg0,F`
156			`bnz $`
157			`bn $`
158			`setf reg0 ; Z = 0, N = 1`
159			`movf reg0,F`
160			`bz $`
161			`bnn $`
162			`negf reg0 ; REG0 = 0x01`
163			`movf reg0,F`
164			`bz $`
165			`bn $`
166			`retlw 0x00`
167
168			`;;`
169			`;; BCC test - OK`
170			`;; Tests all the Z/N/C/OV conditional branches for`
171			`;; positive and negative results`
172			`;;`
173			`_BCC_TEST:`
174			`;; Positive tests`
175			`movlw 0x01`
176			`movwf reg0 ; REG0 = 0x01`
177
178			`rrcf reg0,W ; C = 1, WREG = 0x00`
179			`bc $+4`
180			`bra $`
181			`rlcf reg0,W ; C = 0, WREG = 0x02`
182			`bnc $+4`
183			`bra $`
184
185			`andlw 0x00 ; Z = 1`
186			`bz $+4`
187			`bra $`
188			`iorlw 0x01 ; Z = 0`
189			`bnz $+4`
190			`bra $`
191
192			`xorlw 0x81 ; N = 1`
193			`bn $+4`
194			`bra $`
195			`xorlw 0x80 ; N = 0`
196			`bnn $+4`
197			`bra $`
198
199			`;; Negative test`
200			`movlw 0x00 ; WREG = 0`
201			`addlw 0x00 ; WREG = 0, C = 0`
202			`iorlw 0xFF ; Z = 0, N = 1`
203			`bz $`
204			`bnn $`
205			`bc $`
206
207			`addlw 0x01 ; C = 1, Z = 1, N = 0`
208			`bnc $`
209			`bnz $`
210			`bn $`
211
212			`;; Test OV`
213			`movlw 0x80`
214			`addlw 0x80 ; C = 1, OV = 1, N = 0, Z = 1`
215			`bnov $`
216			`bov $+4`
217			`bra $`
218			`retlw 0x00`
219
220			`;;`
221			`;; BSR test - OK`
222			`;; Simple test to check that BSR is working`
223			`;;`
224			`_BSR_TEST:`
225			`movlw 0xA5 ; WREG = 0xA5`
226			`movlb 0x02 ; BSR = 0x02`
227			`movwf 0x00,B ; (0x0200) = 0xA5`
228			`movff 0x0200, 0x0000 ; (0x0000) = 0xA5`
229			`swapf 0x0000,W ; WREG = 0x5A;`
230			`xorlw 0x5A ; WREG = 0, Z = 1`
231			`bnz $`
232			`retlw 0x00`
233
234			`;;`
235			`;; C used instruction tests`
236			`;; Tests a series of instructions that use C`
237			`;; TODO - verify`
238			`_C_TEST:`
239			`movlw 0xFF ; Indicate Start`
240			`movlw 0x00`
241			`addlw 0x00 ; C = 0`
242			`movwf reg2 ; REG2 = 0`
243
244			`movlw 0x80 ; WREG = 0x80, C = 0`
245			`addlw 0x80 ; WREG = 0x00, C = 1`
246			`rrcf reg2,W ; WREG = 0x80, C = 0;`
247			`addlw 0x80 ; WREG = 0x00, C = 1;`
248			`rlcf reg2,W ; WREG = 0x01, C = 0;`
249
250			`addlw 0xFF ; WREG = 0x00, C = 1;`
251			`addwfc reg2,W ; WREG = 0x01, C = 0;`
252
253			`subwfb reg2,W ; WREG = 0xFE, C = 1;`
254			`addwfc reg2,W ; WREG = 0xFF, C = 0;`
255			`subfwb reg2,W ; WREG = 0xFE, C = 0;`
256
257			`retlw 0x00`
258
259			`;;`
260			`;; SKIP tests - OK`
261			`;; Tests the various SNZ/SZ/SEQ/SGT/SLT instructions`
262			`;;`
263			`_SKIP_TEST:`
264			`movlw 0x01 ; WREG = 0x01`
265			`movwf reg0 ; REG0 = 0x01`
266
267			`btfss reg0,0`
268			`bra $`
269			`btfsc reg0,1`
270			`bra $`
271
272			`decfsz reg0,f ; REG0 = 0x00`
273			`bra $`
274			`dcfsnz reg0,f ; REG0 = 0xFF`
275			`bra $`
276			`incfsz reg0,f ; REG0 = 0x00`
277			`bra $`
278			`infsnz reg0,f ; REG0 = 0x01`
279			`bra $`
280
281			`cpfseq reg0`
282			`bra $`
283			`movlw 0x00 ; WREG = 0x00`
284			`cpfsgt reg0`
285			`bra $`
286			`movlw 0x02`
287			`cpfslt reg0`
288			`bra $`
289
290			`movlw 0x00`
291			`movwf reg2`
292			`tstfsz reg2`
293			`bra $`
294
295			`retlw 0x00`
296
297			`;;`
298			`;; FILE * WREG => FILE tests - OK`
299			`;; Tests the series of byte file operations`
300			`;;`
301			`_FW2F_TEST:`
302			`movlw 0xA5 ; WREG = 0xA5`
303			`movwf reg2 ; REG2 = 0xA5`
304
305			`swapf reg2,F ; REG2 = 0x5A`
306			`andwf reg2,F ; REG2 = 0x00`
307			`iorwf reg2,F ; REG2 = 0xA5`
308			`xorwf reg2,F ; REG2 = 0x00`
309
310			`addwf reg2,F ; REG2 = 0xA5`
311			`subwf reg2,F ; REG2 = 0x00`
312
313			`movwf reg2 ; REG2 = 0xA5`
314			`rrncf reg2,F ; REG2 = 0xD2`
315			`rlncf reg2,F ; REG2 = 0xA5`
316
317			`comf reg2,F ; REG2 = 0x5A`
318			`incf reg2,F ; REG2 = 0x5B`
319			`decf reg2,F ; REG2 = 0x5A`
320
321			`xorwf reg2,W ; WREG = 0x00`
322			`bnz $`
323			`retlw 0x00`
324
325			`;;`
326			`;; FILE * WREG => WREG test - OK`
327			`;; Tests the series of byte file operations`
328			`;;`
329			`_FW2W_TEST:`
330			`movlw 0xA5 ; WREG = 0xA5`
331			`movwf reg2 ; REG2 = 0xA5`
332
333			`swapf reg2,W ; WREG = 0x5A`
334			`andwf reg2,W ; WREG = 0x00`
335			`iorwf reg2,W ; WREG = 0xA5`
336			`xorwf reg2,W ; WREG = 0x00`
337
338			`addwf reg2,W ; WREG = 0xA5`
339			`subwf reg2,W ; WREG = 0x00`
340
341			`rrncf reg2,W ; WREG = 0xD2`
342			`rlncf reg2,W ; WREG = 0x4B`
343
344			`comf reg2,W ; WREG = 0x5A`
345			`incf reg2,W ; WREG = 0xA6`
346			`decf reg2,W ; WREG = 0xA4`
347
348			`xorlw 0xA4`
349			`bnz $`
350			`retlw 0x00 ; WREG = 0x0`
351
352			`;;`
353			`;; MOVE FILE=>WREG/FILE=>FILE/WREG=>FILE tests - OK`
354			`;; Tests moves between FILE and WREG`
355			`;;`
356			`_F2F_TEST:`
357			`movlw 0xA5 ; WREG = 0xA5`
358			`movwf reg0 ; REG0 = 0xA5`
359			`movlw 0x00 ; WREG = 0x00`
360			`movff reg0,reg1 ; REG1 = 0xA5`
361			`movf reg0,f ; REG0 = 0xA5`
362			`movf reg1,w ; WREG = 0xA5`
363			`xorlw 0xA5`
364			`bnz $`
365			`retlw 0x00`
366
367			`;;`
368			`;; BIT test - OK`
369			`;; Tests the sequence of BIT ops`
370			`;;`
371			`_BIT_TEST:`
372			`movlw 0xA5 ; WREG = 0xA5`
373			`movwf reg2 ; REG2 = 0xA5`
374			`bcf reg2,0 ;`
375			`movf reg2,W ; WREG = 0xA4`
376			`bsf reg2,0 ;`
377			`movf reg2,W ; WREG = 0xA5`
378			`btg reg2,0 ;`
379			`movf reg2,W ; WREG = 0xA4`
380			`xorlw 0xA4 ; Z = 1`
381			`bnz $`
382			`retlw 0x00`
383
384			`;;`
385			`;; LIT * WREG => WREG tests - OK`
386			`;; Tests that the sequence of literal operations`
387			`;;`
388			`_LW2W_TEST:`
389			`movlw 0xA5 ; WREG = 0xA5`
390			`addlw 0x05 ; WREG = 0xAA`
391			`sublw 0xFF ; WREG = 0x55`
392			`andlw 0xF0 ; WREG = 0x50`
393			`iorlw 0x0A ; WREG = 0x5A`
394			`xorlw 0xFF ; WREG = 0xA5`
395			`xorlw 0xA5`
396			`bnz $`
397			`retlw 0x00 ; WREG = 0x00`
398
399			`;;`
400			`;; NEAR test - OK`
401			`;; Tests the ability to perform BRA and RCALL by doing some`
402			`;; jump acrobatics.`
403			`;;`
404			`_NPC_TEST:`
405			`bra _NTFWD`
406			`goto $ ; Forward Jump`
407			`_NTFWD: bra _NTBWD`
408			`_NTRET: return`
409			`goto $`
410			`_NTBWD: bra _NTRET ; Backward Jump`
411			`goto $`
412
413			`;;`
414			`;; MULLW/MULWF tests - OK`
415			`;; Tests that the multiplier produces the correct results`
416			`;;`
417			`_MUL_TEST:`
418			`movlw 0x0A ; WREG = 0x0A`
419			`movwf reg0 ; REG0 = 0x0A`
420			`mullw 0xA0 ; PRODH,PRODL = 0x0640`
421
422			`movf PRODH,W ; Z = 0`
423			`xorlw 0x06 ; Z = 1`
424			`bnz $`
425			`movf PRODL,W ; Z = 0`
426			`xorlw 0x40 ; Z = 1`
427			`bnz $`
428
429			`movlw 0x40 ; WREG = 0x40`
430			`mulwf reg0 ; PRODH,PRODL = 0x0280`
431
432			`movf PRODH,W ; Z = 0`
433			`xorlw 0x02 ; Z = 1`
434			`bnz $`
435			`movf PRODL,W ; Z = 0`
436			`xorlw 0x80 ; Z = 1`
437			`bnz $`
438
439			`retlw 0x00`
440
441			`;;`
442			`;; Interrupt Response Test - OK`
443			`;; Just check to see if it jumps here and returns correctly.`
444			`;;`
445			`_ISRH_TEST:`
446			`_ISRL_TEST:`
447			`nop ; Do something`
448			`retfie 1`
449
450			`;; Add some NOP at the end to avoid simulation error`
451			`;; due to XXXX content at memory locations outside`
452			`;; of the end of the programme.`
453			`nop`
454			`nop`
455			`nop`
456			`nop`
457			`nop`
458			`nop`
459			`nop`
460			`nop`
461			`nop`
462			`end`