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// $Id: aeMB_ctrl.v,v 1.4 2007-11-08 17:48:14 sybreon Exp $
//
// AEMB CONTROL UNIT
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation; either version 2.1 of
// the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//  
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_ctrl (/*AUTOARG*/
   // Outputs
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
   dwb_wre_o,
   // Inputs
   rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
   dwb_ack_i, iwb_ack_i, gclk, grst, gena
   );
   // INTERNAL   
   //output [31:2] rPCLNK;
   output [1:0]  rMXDST;
   output [1:0]  rMXSRC, rMXTGT, rMXALT;
   output [2:0]  rMXALU;
   output [4:0]  rRW;
   output        rDWBSTB;
   input [1:0]    rXCE;
   input         rDLY;
   input [15:0]  rIMM;
   input [10:0]  rALT;
   input [5:0]    rOPC;
   input [4:0]    rRD, rRA, rRB;
   input [31:2]  rPC;
   input         rBRA;
   input         rMSR_IE;
 
   // DATA WISHBONE
   output        dwb_stb_o;
   output        dwb_wre_o;
   input         dwb_ack_i;
 
   // INST WISHBONE
   input         iwb_ack_i;
 
   // SYSTEM
   input         gclk, grst, gena;
 
   // --- DECODE INSTRUCTIONS
   // TODO: Simplify
 
   wire          fSFT = (rOPC == 6'o44);
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
 
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire          fDIV = (rOPC == 6'o22);
 
   wire          fRTD = (rOPC == 6'o55);
   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire          fBRA = fBRU & rRA[3];
 
   wire          fIMM = (rOPC == 6'o54);
   wire          fMOV = (rOPC == 6'o45);
 
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire          fLDST = (&rOPC[5:4]);
 
 
   // --- OPERAND SELECTOR ---------------------------------
 
   wire          fRDWE = |rRW;
   wire          fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
   wire          fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
   wire          fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
   wire          fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
 
   assign        rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
                          (fAFWD_M) ? 2'o2: // RAM
                          (fAFWD_R) ? 2'o1: // FWD
                          2'o0; // REG
 
   assign        rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
                          (fBFWD_M) ? 2'o2 : // RAM
                          (fBFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
   assign        rMXALT = (fAFWD_M) ? 2'o2 : // RAM
                          (fAFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
 
   // --- ALU CONTROL ---------------------------------------
 
   reg [2:0]      rMXALU;
   always @(/*AUTOSENSE*/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
            or fSFT) begin
      rMXALU <= (fBRA | fMOV) ? 3'o3 :
                (fSFT) ? 3'o2 :
                (fLOG) ? 3'o1 :
                (fMUL) ? 3'o4 :
                (fBSF) ? 3'o5 :
                (fDIV) ? 3'o6 :
                3'o0;
   end
 
 
   // --- RAM CONTROL ---------------------------------------
 
   reg           rDWBSTB, xDWBSTB;
   reg           rDWBWRE, xDWBWRE;
 
   assign        dwb_stb_o = rDWBSTB;
   assign        dwb_wre_o = rDWBWRE;
 
   // --- DELAY SLOT REGISTERS ------------------------------
 
   reg [31:2]    rPCLNK, xPCLNK;
   reg [1:0]      rMXDST, xMXDST;
   reg [4:0]      rRW, xRW;
 
   wire          fSKIP = (rBRA & !rDLY);
   wire          fDACK = !(rDWBSTB ^ dwb_ack_i);
 
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
     if (fSKIP | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xDWBSTB <= 1'h0;
        xDWBWRE <= 1'h0;
        // End of automatics
     end else begin
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
        xDWBWRE <= fSTR & iwb_ack_i;
     end
 
   always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
            or rRD or rXCE)
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXDST <= 2'h0;
        xRW <= 5'h0;
        // End of automatics
     end else begin
        case (rXCE)
          2'o2: xMXDST <= 2'o1;
          default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                             (fLOD) ? 2'o2 :
                             (fBRU) ? 2'o1 :
                             2'o0;
        endcase
 
        case (rXCE)
          2'o2: xRW <= 5'd14;
          default: xRW <= rRD;
        endcase
 
     end // else: !if(fSKIP)
 
 
   // --- PIPELINE CONTROL DELAY ----------------------------
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMXDST <= 2'h0;
        rRW <= 5'h0;
        // End of automatics
     end else if (gena) begin
        //rPCLNK <= #1 xPCLNK;
        rMXDST <= #1 xMXDST;
        rRW <= #1 xRW;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rDWBSTB <= 1'h0;
        rDWBWRE <= 1'h0;
        // End of automatics
     end else if (fDACK) begin
        rDWBSTB <= #1 xDWBSTB;
        rDWBWRE <= #1 xDWBWRE;
     end
 
 
endmodule // aeMB_ctrl

Line No.	Rev	Author	Line
1	51	sybreon	`// $Id: aeMB_ctrl.v,v 1.4 2007-11-08 17:48:14 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB CONTROL UNIT`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7			`// This library is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU Lesser General Public License`
9			`// as published by the Free Software Foundation; either version 2.1 of`
10			`// the License, or (at your option) any later version.`
11			`//`
12			`// This library is distributed in the hope that it will be useful, but`
13			`// WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`// Lesser General Public License for more details.`
16			`//`
17			`// You should have received a copy of the GNU Lesser General Public`
18			`// License along with this library; if not, write to the Free Software`
19			`// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
20			`// USA`
21			`//`
22			`// $Log: not supported by cvs2svn $`
23	51	sybreon	`// Revision 1.3 2007/11/08 14:17:47 sybreon`
24			`// Parameterised optional components.`
25			`//`
26	50	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
27			`// Added better (beta) interrupt support.`
28			`// Changed MSR_IE to disabled at reset as per MB docs.`
29			`//`
30	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
31			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
32			`// Fixed various minor data hazard bugs.`
33			`// Code compatible with -O0/1/2/3/s generated code.`
34			`//`
35	41	sybreon
36			`module aeMB_ctrl (/AUTOARG/`
37			`// Outputs`
38	44	sybreon	`rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,`
39			`dwb_wre_o,`
40	41	sybreon	`// Inputs`
41	44	sybreon	`rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,`
42	51	sybreon	`dwb_ack_i, iwb_ack_i, gclk, grst, gena`
43	41	sybreon	`);`
44			`// INTERNAL`
45			`//output [31:2] rPCLNK;`
46			`output [1:0] rMXDST;`
47			`output [1:0] rMXSRC, rMXTGT, rMXALT;`
48			`output [2:0] rMXALU;`
49			`output [4:0] rRW;`
50			`output rDWBSTB;`
51	44	sybreon	`input [1:0] rXCE;`
52	41	sybreon	`input rDLY;`
53			`input [15:0] rIMM;`
54			`input [10:0] rALT;`
55			`input [5:0] rOPC;`
56			`input [4:0] rRD, rRA, rRB;`
57			`input [31:2] rPC;`
58			`input rBRA;`
59			`input rMSR_IE;`
60
61			`// DATA WISHBONE`
62			`output dwb_stb_o;`
63			`output dwb_wre_o;`
64	51	sybreon	`input dwb_ack_i;`
65
66			`// INST WISHBONE`
67			`input iwb_ack_i;`
68	41	sybreon
69			`// SYSTEM`
70			`input gclk, grst, gena;`
71
72			`// --- DECODE INSTRUCTIONS`
73			`// TODO: Simplify`
74
75			`wire fSFT = (rOPC == 6'o44);`
76			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
77
78			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
79			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
80			`wire fDIV = (rOPC == 6'o22);`
81
82			`wire fRTD = (rOPC == 6'o55);`
83			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
84			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
85			`wire fBRA = fBRU & rRA[3];`
86
87			`wire fIMM = (rOPC == 6'o54);`
88			`wire fMOV = (rOPC == 6'o45);`
89
90			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
91			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
92			`wire fLDST = (&rOPC[5:4]);`
93
94
95			`// --- OPERAND SELECTOR ---------------------------------`
96
97			`wire fRDWE = \|rRW;`
98			`wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;`
99			`wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;`
100			`wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;`
101			`wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;`
102
103			`assign rMXSRC = (fBRU \| fBCC) ? 2'o3 : // PC`
104			`(fAFWD_M) ? 2'o2: // RAM`
105			`(fAFWD_R) ? 2'o1: // FWD`
106			`2'o0; // REG`
107
108			`assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM`
109			`(fBFWD_M) ? 2'o2 : // RAM`
110			`(fBFWD_R) ? 2'o1 : // FWD`
111			`2'o0; // REG`
112
113			`assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM`
114			`(fAFWD_R) ? 2'o1 : // FWD`
115			`2'o0; // REG`
116
117
118			`// --- ALU CONTROL ---------------------------------------`
119
120			`reg [2:0] rMXALU;`
121			`always @(/AUTOSENSE/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL`
122			`or fSFT) begin`
123			`rMXALU <= (fBRA \| fMOV) ? 3'o3 :`
124			`(fSFT) ? 3'o2 :`
125			`(fLOG) ? 3'o1 :`
126			`(fMUL) ? 3'o4 :`
127			`(fBSF) ? 3'o5 :`
128			`(fDIV) ? 3'o6 :`
129			`3'o0;`
130			`end`
131
132
133			`// --- RAM CONTROL ---------------------------------------`
134
135			`reg rDWBSTB, xDWBSTB;`
136			`reg rDWBWRE, xDWBWRE;`
137
138			`assign dwb_stb_o = rDWBSTB;`
139			`assign dwb_wre_o = rDWBWRE;`
140
141			`// --- DELAY SLOT REGISTERS ------------------------------`
142
143			`reg [31:2] rPCLNK, xPCLNK;`
144			`reg [1:0] rMXDST, xMXDST;`
145			`reg [4:0] rRW, xRW;`
146
147	50	sybreon	`wire fSKIP = (rBRA & !rDLY);`
148	51	sybreon	`wire fDACK = !(rDWBSTB ^ dwb_ack_i);`
149
150			`always @(/AUTOSENSE/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)`
151	44	sybreon	`if (fSKIP \| \|rXCE) begin`
152	41	sybreon	`/AUTORESET/`
153			`// Beginning of autoreset for uninitialized flops`
154			`xDWBSTB <= 1'h0;`
155			`xDWBWRE <= 1'h0;`
156			`// End of automatics`
157			`end else begin`
158	51	sybreon	`xDWBSTB <= (fLOD \| fSTR) & iwb_ack_i;`
159			`xDWBWRE <= fSTR & iwb_ack_i;`
160	41	sybreon	`end`
161
162			`always @(/AUTOSENSE/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR`
163	44	sybreon	`or rRD or rXCE)`
164	41	sybreon	`if (fSKIP) begin`
165			`/AUTORESET/`
166			`// Beginning of autoreset for uninitialized flops`
167			`xMXDST <= 2'h0;`
168			`xRW <= 5'h0;`
169			`// End of automatics`
170			`end else begin`
171			`case (rXCE)`
172	44	sybreon	`2'o2: xMXDST <= 2'o1;`
173	41	sybreon	`default: xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
174			`(fLOD) ? 2'o2 :`
175			`(fBRU) ? 2'o1 :`
176			`2'o0;`
177	44	sybreon	`endcase`
178
179	41	sybreon	`case (rXCE)`
180	44	sybreon	`2'o2: xRW <= 5'd14;`
181	41	sybreon	`default: xRW <= rRD;`
182	44	sybreon	`endcase`
183	41	sybreon
184	44	sybreon	`end // else: !if(fSKIP)`
185	41	sybreon
186
187			`// --- PIPELINE CONTROL DELAY ----------------------------`
188
189			`always @(posedge gclk)`
190			`if (grst) begin`
191			`/AUTORESET/`
192			`// Beginning of autoreset for uninitialized flops`
193			`rMXDST <= 2'h0;`
194			`rRW <= 5'h0;`
195			`// End of automatics`
196			`end else if (gena) begin`
197			`//rPCLNK <= #1 xPCLNK;`
198			`rMXDST <= #1 xMXDST;`
199			`rRW <= #1 xRW;`
200	51	sybreon	`end`
201
202			`always @(posedge gclk)`
203			`if (grst) begin`
204			`/AUTORESET/`
205			`// Beginning of autoreset for uninitialized flops`
206			`rDWBSTB <= 1'h0;`
207			`rDWBWRE <= 1'h0;`
208			`// End of automatics`
209			`end else if (fDACK) begin`
210	41	sybreon	`rDWBSTB <= #1 xDWBSTB;`
211			`rDWBWRE <= #1 xDWBWRE;`
212	51	sybreon	`end`
213	41	sybreon
214
215			`endmodule // aeMB_ctrl`

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