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// $Id: aeMB_ctrl.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB CONTROL UNIT
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation; either version 2.1 of
// the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//  
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_ctrl (/*AUTOARG*/
   // Outputs
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
   dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
   // Inputs
   rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
   dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
   );
   // INTERNAL   
   //output [31:2] rPCLNK;
   output [1:0]  rMXDST;
   output [1:0]  rMXSRC, rMXTGT, rMXALT;
   output [2:0]  rMXALU;
   output [4:0]  rRW;
   output        rDWBSTB;
   output        rFSLSTB;
 
   input [1:0]    rXCE;
   input         rDLY;
   input [15:0]  rIMM;
   input [10:0]  rALT;
   input [5:0]    rOPC;
   input [4:0]    rRD, rRA, rRB;
   input [31:2]  rPC;
   input         rBRA;
   input         rMSR_IE;
 
   // DATA WISHBONE
   output        dwb_stb_o;
   output        dwb_wre_o;
   input         dwb_ack_i;
 
   // INST WISHBONE
   input         iwb_ack_i;
 
   // FSL WISHBONE
   output        fsl_stb_o;
   output        fsl_wre_o;
   input         fsl_ack_i;
 
   // SYSTEM
   input         gclk, grst, gena;
 
   // --- DECODE INSTRUCTIONS
   // TODO: Simplify
 
   wire          fSFT = (rOPC == 6'o44);
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
 
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire          fDIV = (rOPC == 6'o22);
 
   wire          fRTD = (rOPC == 6'o55);
   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire          fBRA = fBRU & rRA[3];
 
   wire          fIMM = (rOPC == 6'o54);
   wire          fMOV = (rOPC == 6'o45);
 
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire          fLDST = (&rOPC[5:4]);
 
   wire          fPUT = (rOPC == 6'o33) & rRB[4];
   wire          fGET = (rOPC == 6'o33) & !rRB[4];
 
   // --- OPERAND SELECTOR ---------------------------------
 
   wire          fRDWE = |rRW;
   wire          fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
   wire          fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
   wire          fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
   wire          fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
 
   assign        rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
                          (fAFWD_M) ? 2'o2: // RAM
                          (fAFWD_R) ? 2'o1: // FWD
                          2'o0; // REG
 
   assign        rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
                          (fBFWD_M) ? 2'o2 : // RAM
                          (fBFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
   assign        rMXALT = (fAFWD_M) ? 2'o2 : // RAM
                          (fAFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
 
   // --- ALU CONTROL ---------------------------------------
 
   reg [2:0]      rMXALU;
   always @(/*AUTOSENSE*/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
            or fSFT) begin
      rMXALU <= (fBRA | fMOV) ? 3'o3 :
                (fSFT) ? 3'o2 :
                (fLOG) ? 3'o1 :
                (fMUL) ? 3'o4 :
                (fBSF) ? 3'o5 :
                (fDIV) ? 3'o6 :
                3'o0;
   end
 
 
   // --- DELAY SLOT REGISTERS ------------------------------
 
   reg [31:2]    rPCLNK, xPCLNK;
   reg [1:0]      rMXDST, xMXDST;
   reg [4:0]      rRW, xRW;
 
   wire          fSKIP = (rBRA & !rDLY);
 
   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
            or fSTR or rRD or rXCE)
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXDST <= 2'h0;
        xRW <= 5'h0;
        // End of automatics
     end else begin
        case (rXCE)
          2'o2: xMXDST <= 2'o1;
          default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                             (fLOD | fGET) ? 2'o2 :
                             (fBRU) ? 2'o1 :
                             2'o0;
        endcase
 
        case (rXCE)
          2'o2: xRW <= 5'd14;
          default: xRW <= rRD;
        endcase
 
     end // else: !if(fSKIP)
 
 
   // --- DATA WISHBONE ----------------------------------
 
   wire          fDACK = !(rDWBSTB ^ dwb_ack_i);
 
   reg           rDWBSTB, xDWBSTB;
   reg           rDWBWRE, xDWBWRE;
 
   assign        dwb_stb_o = rDWBSTB;
   assign        dwb_wre_o = rDWBWRE;
 
 
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
     if (fSKIP | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xDWBSTB <= 1'h0;
        xDWBWRE <= 1'h0;
        // End of automatics
     end else begin
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
        xDWBWRE <= fSTR & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rDWBSTB <= 1'h0;
        rDWBWRE <= 1'h0;
        // End of automatics
     end else if (fDACK) begin
        rDWBSTB <= #1 xDWBSTB;
        rDWBWRE <= #1 xDWBWRE;
     end
 
 
   // --- FSL WISHBONE -----------------------------------
 
   wire          fFACK = !(rFSLSTB ^ fsl_ack_i);
 
   reg           rFSLSTB, xFSLSTB;
   reg           rFSLWRE, xFSLWRE;
 
   assign        fsl_stb_o = rFSLSTB;
   assign        fsl_wre_o = rFSLWRE;
 
   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
     if (fSKIP | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xFSLSTB <= 1'h0;
        xFSLWRE <= 1'h0;
        // End of automatics
     end else begin
        xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
        xFSLWRE <= fPUT & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFSLSTB <= 1'h0;
        rFSLWRE <= 1'h0;
        // End of automatics
     end else if (fFACK) begin
        rFSLSTB <= #1 xFSLSTB;
        rFSLWRE <= #1 xFSLWRE;
     end
 
   // --- PIPELINE CONTROL DELAY ----------------------------
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMXDST <= 2'h0;
        rRW <= 5'h0;
        // End of automatics
     end else if (gena) begin
        //rPCLNK <= #1 xPCLNK;
        rMXDST <= #1 xMXDST;
        rRW <= #1 xRW;
     end
 
 
endmodule // aeMB_ctrl

Line No.	Rev	Author	Line
1	53	sybreon	`// $Id: aeMB_ctrl.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB CONTROL UNIT`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7			`// This library is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU Lesser General Public License`
9			`// as published by the Free Software Foundation; either version 2.1 of`
10			`// the License, or (at your option) any later version.`
11			`//`
12			`// This library is distributed in the hope that it will be useful, but`
13			`// WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`// Lesser General Public License for more details.`
16			`//`
17			`// You should have received a copy of the GNU Lesser General Public`
18			`// License along with this library; if not, write to the Free Software`
19			`// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
20			`// USA`
21			`//`
22			`// $Log: not supported by cvs2svn $`
23	53	sybreon	`// Revision 1.4 2007/11/08 17:48:14 sybreon`
24			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
25			`//`
26	51	sybreon	`// Revision 1.3 2007/11/08 14:17:47 sybreon`
27			`// Parameterised optional components.`
28			`//`
29	50	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
30			`// Added better (beta) interrupt support.`
31			`// Changed MSR_IE to disabled at reset as per MB docs.`
32			`//`
33	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
34			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
35			`// Fixed various minor data hazard bugs.`
36			`// Code compatible with -O0/1/2/3/s generated code.`
37			`//`
38	41	sybreon
39			`module aeMB_ctrl (/AUTOARG/`
40			`// Outputs`
41	53	sybreon	`rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,`
42			`dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,`
43	41	sybreon	`// Inputs`
44	44	sybreon	`rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,`
45	53	sybreon	`dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena`
46	41	sybreon	`);`
47			`// INTERNAL`
48			`//output [31:2] rPCLNK;`
49			`output [1:0] rMXDST;`
50			`output [1:0] rMXSRC, rMXTGT, rMXALT;`
51			`output [2:0] rMXALU;`
52			`output [4:0] rRW;`
53	53	sybreon	`output rDWBSTB;`
54			`output rFSLSTB;`
55
56	44	sybreon	`input [1:0] rXCE;`
57	41	sybreon	`input rDLY;`
58			`input [15:0] rIMM;`
59			`input [10:0] rALT;`
60			`input [5:0] rOPC;`
61			`input [4:0] rRD, rRA, rRB;`
62			`input [31:2] rPC;`
63			`input rBRA;`
64			`input rMSR_IE;`
65
66			`// DATA WISHBONE`
67			`output dwb_stb_o;`
68			`output dwb_wre_o;`
69	51	sybreon	`input dwb_ack_i;`
70
71			`// INST WISHBONE`
72			`input iwb_ack_i;`
73	41	sybreon
74	53	sybreon	`// FSL WISHBONE`
75			`output fsl_stb_o;`
76			`output fsl_wre_o;`
77			`input fsl_ack_i;`
78
79	41	sybreon	`// SYSTEM`
80			`input gclk, grst, gena;`
81
82			`// --- DECODE INSTRUCTIONS`
83			`// TODO: Simplify`
84
85			`wire fSFT = (rOPC == 6'o44);`
86			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
87
88			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
89			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
90			`wire fDIV = (rOPC == 6'o22);`
91
92			`wire fRTD = (rOPC == 6'o55);`
93			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
94			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
95			`wire fBRA = fBRU & rRA[3];`
96
97			`wire fIMM = (rOPC == 6'o54);`
98			`wire fMOV = (rOPC == 6'o45);`
99
100			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
101			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
102			`wire fLDST = (&rOPC[5:4]);`
103
104	53	sybreon	`wire fPUT = (rOPC == 6'o33) & rRB[4];`
105			`wire fGET = (rOPC == 6'o33) & !rRB[4];`
106	41	sybreon
107			`// --- OPERAND SELECTOR ---------------------------------`
108
109			`wire fRDWE = \|rRW;`
110			`wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;`
111			`wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;`
112			`wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;`
113			`wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;`
114
115			`assign rMXSRC = (fBRU \| fBCC) ? 2'o3 : // PC`
116			`(fAFWD_M) ? 2'o2: // RAM`
117			`(fAFWD_R) ? 2'o1: // FWD`
118			`2'o0; // REG`
119
120			`assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM`
121			`(fBFWD_M) ? 2'o2 : // RAM`
122			`(fBFWD_R) ? 2'o1 : // FWD`
123			`2'o0; // REG`
124
125			`assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM`
126			`(fAFWD_R) ? 2'o1 : // FWD`
127			`2'o0; // REG`
128
129
130			`// --- ALU CONTROL ---------------------------------------`
131
132			`reg [2:0] rMXALU;`
133			`always @(/AUTOSENSE/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL`
134			`or fSFT) begin`
135			`rMXALU <= (fBRA \| fMOV) ? 3'o3 :`
136			`(fSFT) ? 3'o2 :`
137			`(fLOG) ? 3'o1 :`
138			`(fMUL) ? 3'o4 :`
139			`(fBSF) ? 3'o5 :`
140			`(fDIV) ? 3'o6 :`
141			`3'o0;`
142			`end`
143
144
145			`// --- DELAY SLOT REGISTERS ------------------------------`
146
147			`reg [31:2] rPCLNK, xPCLNK;`
148			`reg [1:0] rMXDST, xMXDST;`
149			`reg [4:0] rRW, xRW;`
150
151	50	sybreon	`wire fSKIP = (rBRA & !rDLY);`
152	51	sybreon
153	53	sybreon	`always @(/AUTOSENSE/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP`
154			`or fSTR or rRD or rXCE)`
155	41	sybreon	`if (fSKIP) begin`
156			`/AUTORESET/`
157			`// Beginning of autoreset for uninitialized flops`
158			`xMXDST <= 2'h0;`
159			`xRW <= 5'h0;`
160			`// End of automatics`
161			`end else begin`
162			`case (rXCE)`
163	44	sybreon	`2'o2: xMXDST <= 2'o1;`
164	41	sybreon	`default: xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
165	53	sybreon	`(fLOD \| fGET) ? 2'o2 :`
166	41	sybreon	`(fBRU) ? 2'o1 :`
167			`2'o0;`
168	44	sybreon	`endcase`
169
170	41	sybreon	`case (rXCE)`
171	44	sybreon	`2'o2: xRW <= 5'd14;`
172	41	sybreon	`default: xRW <= rRD;`
173	44	sybreon	`endcase`
174	41	sybreon
175	44	sybreon	`end // else: !if(fSKIP)`
176	53	sybreon
177
178			`// --- DATA WISHBONE ----------------------------------`
179
180			`wire fDACK = !(rDWBSTB ^ dwb_ack_i);`
181	41	sybreon
182	53	sybreon	`reg rDWBSTB, xDWBSTB;`
183			`reg rDWBWRE, xDWBWRE;`
184
185			`assign dwb_stb_o = rDWBSTB;`
186			`assign dwb_wre_o = rDWBWRE;`
187	41	sybreon
188	53	sybreon
189			`always @(/AUTOSENSE/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)`
190			`if (fSKIP \| \|rXCE) begin`
191	41	sybreon	`/AUTORESET/`
192			`// Beginning of autoreset for uninitialized flops`
193	53	sybreon	`xDWBSTB <= 1'h0;`
194			`xDWBWRE <= 1'h0;`
195	41	sybreon	`// End of automatics`
196	53	sybreon	`end else begin`
197			`xDWBSTB <= (fLOD \| fSTR) & iwb_ack_i;`
198			`xDWBWRE <= fSTR & iwb_ack_i;`
199	51	sybreon	`end`
200	53	sybreon
201	51	sybreon	`always @(posedge gclk)`
202			`if (grst) begin`
203			`/AUTORESET/`
204			`// Beginning of autoreset for uninitialized flops`
205			`rDWBSTB <= 1'h0;`
206			`rDWBWRE <= 1'h0;`
207			`// End of automatics`
208			`end else if (fDACK) begin`
209	41	sybreon	`rDWBSTB <= #1 xDWBSTB;`
210			`rDWBWRE <= #1 xDWBWRE;`
211	51	sybreon	`end`
212	41	sybreon
213	53	sybreon
214			`// --- FSL WISHBONE -----------------------------------`
215
216			`wire fFACK = !(rFSLSTB ^ fsl_ack_i);`
217
218			`reg rFSLSTB, xFSLSTB;`
219			`reg rFSLWRE, xFSLWRE;`
220
221			`assign fsl_stb_o = rFSLSTB;`
222			`assign fsl_wre_o = rFSLWRE;`
223
224			`always @(/AUTOSENSE/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)`
225			`if (fSKIP \| \|rXCE) begin`
226			`/AUTORESET/`
227			`// Beginning of autoreset for uninitialized flops`
228			`xFSLSTB <= 1'h0;`
229			`xFSLWRE <= 1'h0;`
230			`// End of automatics`
231			`end else begin`
232			`xFSLSTB <= (fPUT \| fGET) & iwb_ack_i;`
233			`xFSLWRE <= fPUT & iwb_ack_i;`
234			`end`
235
236			`always @(posedge gclk)`
237			`if (grst) begin`
238			`/AUTORESET/`
239			`// Beginning of autoreset for uninitialized flops`
240			`rFSLSTB <= 1'h0;`
241			`rFSLWRE <= 1'h0;`
242			`// End of automatics`
243			`end else if (fFACK) begin`
244			`rFSLSTB <= #1 xFSLSTB;`
245			`rFSLWRE <= #1 xFSLWRE;`
246			`end`
247	41	sybreon
248	53	sybreon	`// --- PIPELINE CONTROL DELAY ----------------------------`
249
250			`always @(posedge gclk)`
251			`if (grst) begin`
252			`/AUTORESET/`
253			`// Beginning of autoreset for uninitialized flops`
254			`rMXDST <= 2'h0;`
255			`rRW <= 5'h0;`
256			`// End of automatics`
257			`end else if (gena) begin`
258			`//rPCLNK <= #1 xPCLNK;`
259			`rMXDST <= #1 xMXDST;`
260			`rRW <= #1 xRW;`
261			`end`
262
263
264	41	sybreon	`endmodule // aeMB_ctrl`

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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] [aeMB_ctrl.v] - Blame information for rev 53