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// $Id: aeMB_edk32.v,v 1.11 2007-11-30 17:08:29 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2007/11/16 21:52:03  sybreon
// Added fsl_tag_o to FSL bus (tag either address or data).
//
// Revision 1.9  2007/11/14 23:19:24  sybreon
// Fixed minor typo.
//
// Revision 1.8  2007/11/14 22:14:34  sybreon
// Changed interrupt handling system (reported by M. Ettus).
//
// Revision 1.7  2007/11/10 16:39:38  sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.6  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.5  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.4  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.3  2007/11/03 08:34:55  sybreon
// Minor code cleanup.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_edk32 (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
   // Inputs
   sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
   dwb_ack_i, sys_clk_i, sys_rst_i
   );
   // Bus widths
   parameter IW = 32; /// Instruction bus address width
   parameter DW = 32; /// Data bus address width
 
   // Optional functions
   parameter MUL = 1; // Multiplier
   parameter BSF = 1; // Barrel Shifter
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
   output [6:2]         fsl_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] fsl_dat_o;              // From regf of aeMB_regf.v
   output               fsl_stb_o;              // From ctrl of aeMB_ctrl.v
   output [1:0]          fsl_tag_o;              // From xecu of aeMB_xecu.v
   output               fsl_wre_o;              // From ctrl of aeMB_ctrl.v
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To ctrl of aeMB_ctrl.v
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
   input                fsl_ack_i;              // To ctrl of aeMB_ctrl.v
   input [31:0]          fsl_dat_i;              // To regf of aeMB_regf.v
   input                iwb_ack_i;              // To ibuf of aeMB_ibuf.v, ...
   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v
   input                sys_int_i;              // To ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
   wire [31:0]           xIREG;                  // From ibuf of aeMB_ibuf.v
   // End of automatics
 
   input                sys_clk_i;
   input                sys_rst_i;
 
   wire                 grst = sys_rst_i;
   wire                 gclk = sys_clk_i;
   wire                 gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
 
   // --- INSTANTIATIONS -------------------------------------
 
   aeMB_ibuf
     ibuf (/*AUTOINST*/
           // Outputs
           .rIMM                        (rIMM[15:0]),
           .rRA                         (rRA[4:0]),
           .rRD                         (rRD[4:0]),
           .rRB                         (rRB[4:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rSIMM                       (rSIMM[31:0]),
           .xIREG                       (xIREG[31:0]),
           .iwb_stb_o                   (iwb_stb_o),
           // Inputs
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .iwb_ack_i                   (iwb_ack_i),
           .sys_int_i                   (sys_int_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_ctrl
     ctrl (/*AUTOINST*/
           // Outputs
           .rMXDST                      (rMXDST[1:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALT                      (rMXALT[1:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rRW                         (rRW[4:0]),
           .dwb_stb_o                   (dwb_stb_o),
           .dwb_wre_o                   (dwb_wre_o),
           .fsl_stb_o                   (fsl_stb_o),
           .fsl_wre_o                   (fsl_wre_o),
           // Inputs
           .rDLY                        (rDLY),
           .rIMM                        (rIMM[15:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rPC                         (rPC[31:2]),
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .xIREG                       (xIREG[31:0]),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .fsl_ack_i                   (fsl_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_bpcu #(IW)
     bpcu (/*AUTOINST*/
           // Outputs
           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
           .rPC                         (rPC[31:2]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           // Inputs
           .rMXALT                      (rMXALT[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rREGA                       (rREGA[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_regf
     regf (/*AUTOINST*/
           // Outputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .dwb_dat_o                   (dwb_dat_o[31:0]),
           .fsl_dat_o                   (fsl_dat_o[31:0]),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rRW                         (rRW[4:0]),
           .rRD                         (rRD[4:0]),
           .rMXDST                      (rMXDST[1:0]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .fsl_dat_i                   (fsl_dat_i[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_xecu #(DW, MUL, BSF)
     xecu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .fsl_adr_o                   (fsl_adr_o[6:2]),
           .fsl_tag_o                   (fsl_tag_o[1:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           // Inputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rALT                        (rALT[10:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rPC                         (rPC[31:2]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
 
   // --- SIMULATION KERNEL ----------------------------------
   // synopsys translate_off
 
`ifdef AEMB_SIMULATION_KERNEL
 
   wire [IW-1:0]         iwb_adr = {iwb_adr_o, 2'd0};
   wire [DW-1:0]         dwb_adr = {dwb_adr_o,2'd0};
   wire [1:0]            wBRA = {rBRA, rDLY};
   wire [3:0]            wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE, xecu.rMSR_BE};
 
   always @(posedge gclk) if (gena) begin
 
      $write ("\n", ($stime/10));
      $writeh (" PC=", iwb_adr );
      $writeh ("\t");
 
      case (wBRA)
        2'b00: $write(" ");
        2'b01: $write(".");
        2'b10: $write("-");
        2'b11: $write("+");
      endcase // case (wBRA)
 
      case (rOPC)
        6'o00: if (rRD == 0) $write("   "); else $write("ADD");
        6'o01: $write("RSUB");
        6'o02: $write("ADDC");
        6'o03: $write("RSUBC");
        6'o04: $write("ADDK");
        6'o05: case (rIMM[1:0])
                 2'o0: $write("RSUBK");
                 2'o1: $write("CMP");
                 2'o3: $write("CMPU");
                 default: $write("XXX");
               endcase // case (rIMM[1:0])
        6'o06: $write("ADDKC");
        6'o07: $write("RSUBKC");
 
        6'o10: $write("ADDI");
        6'o11: $write("RSUBI");
        6'o12: $write("ADDIC");
        6'o13: $write("RSUBIC");
        6'o14: $write("ADDIK");
        6'o15: $write("RSUBIK");
        6'o16: $write("ADDIKC");
        6'o17: $write("RSUBIKC");
 
        6'o20: $write("MUL");
        6'o21: case (rALT[10:9])
                 2'o0: $write("BSRL");
                 2'o1: $write("BSRA");
                 2'o2: $write("BSLL");
                 default: $write("XXX");
               endcase // case (rALT[10:9])
        6'o22: $write("IDIV");
 
        6'o30: $write("MULI");
        6'o31: case (rALT[10:9])
                 2'o0: $write("BSRLI");
                 2'o1: $write("BSRAI");
                 2'o2: $write("BSLLI");
                 default: $write("XXX");
               endcase // case (rALT[10:9])
        6'o33: case (rRB[4:2])
                 3'o0: $write("GET");
                 3'o4: $write("PUT");
                 3'o2: $write("NGET");
                 3'o6: $write("NPUT");
                 3'o1: $write("CGET");
                 3'o5: $write("CPUT");
                 3'o3: $write("NCGET");
                 3'o7: $write("NCPUT");
               endcase // case (rRB[4:2])
 
        6'o40: $write("OR");
        6'o41: $write("AND");
        6'o42: if (rRD == 0) $write("   "); else $write("XOR");
        6'o43: $write("ANDN");
        6'o44: case (rIMM[6:5])
                 2'o0: $write("SRA");
                 2'o1: $write("SRC");
                 2'o2: $write("SRL");
                 2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8");
               endcase // case (rIMM[6:5])
 
        6'o45: $write("MOV");
        6'o46: case (rRA[3:2])
                 3'o0: $write("BR");
                 3'o1: $write("BRL");
                 3'o2: $write("BRA");
                 3'o3: $write("BRAL");
               endcase // case (rRA[3:2])
 
        6'o47: case (rRD[2:0])
                 3'o0: $write("BEQ");
                 3'o1: $write("BNE");
                 3'o2: $write("BLT");
                 3'o3: $write("BLE");
                 3'o4: $write("BGT");
                 3'o5: $write("BGE");
                 default: $write("XXX");
               endcase // case (rRD[2:0])
 
        6'o50: $write("ORI");
        6'o51: $write("ANDI");
        6'o52: $write("XORI");
        6'o53: $write("ANDNI");
        6'o54: $write("IMMI");
        6'o55: case (rRD[1:0])
                 2'o0: $write("RTSD");
                 2'o1: $write("RTID");
                 2'o2: $write("RTBD");
                 default: $write("XXX");
               endcase // case (rRD[1:0])
        6'o56: case (rRA[3:2])
                 3'o0: $write("BRI");
                 3'o1: $write("BRLI");
                 3'o2: $write("BRAI");
                 3'o3: $write("BRALI");
               endcase // case (rRA[3:2])
        6'o57: case (rRD[2:0])
                 3'o0: $write("BEQI");
                 3'o1: $write("BNEI");
                 3'o2: $write("BLTI");
                 3'o3: $write("BLEI");
                 3'o4: $write("BGTI");
                 3'o5: $write("BGEI");
                 default: $write("XXX");
               endcase // case (rRD[2:0])
 
        6'o60: $write("LBU");
        6'o61: $write("LHU");
        6'o62: $write("LW");
        6'o64: $write("SB");
        6'o65: $write("SH");
        6'o66: $write("SW");
 
        6'o70: $write("LBUI");
        6'o71: $write("LHUI");
        6'o72: $write("LWI");
        6'o74: $write("SBI");
        6'o75: $write("SHI");
        6'o76: $write("SWI");
 
        default: $write("XXX");
      endcase // case (rOPC)
 
      case (rOPC[3])
        1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM);
        1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB,"  ");
      endcase // case (rOPC[3])
 
 
      // ALU
      $write("\t");
      $writeh(" A=",xecu.rOPA);
      $writeh(" B=",xecu.rOPB);
 
      case (rMXALU)
        3'o0: $write(" ADD");
        3'o1: $write(" LOG");
        3'o2: $write(" SFT");
        3'o3: $write(" MOV");
        3'o4: $write(" MUL");
        3'o5: $write(" BSF");
        default: $write(" XXX");
      endcase // case (rMXALU)
      $writeh("=h",xecu.xRESULT);
 
      // WRITEBACK
      $writeh("\tSR=", wMSR," ");
 
      if (regf.fRDWE) begin
         case (rMXDST)
           2'o2: begin
              if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")");
              if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")");
           end
           2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")");
           2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")");
         endcase // case (rMXDST)
      end
 
      // STORE
      if (dwb_stb_o & dwb_wre_o) begin
         $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
         case (dwb_sel_o)
           4'hF: $write(":L");
           4'h3,4'hC: $write(":W");
           4'h1,4'h2,4'h4,4'h8: $write(":B");
         endcase // case (dwb_sel_o)
 
      end
 
   end // if (gena)
 
`endif //  `ifdef AEMB_SIMULATION_KERNEL
   // synopsys translate_on
 
endmodule // aeMB_edk32

Line No.	Rev	Author	Line
1	73	sybreon	`// $Id: aeMB_edk32.v,v 1.11 2007-11-30 17:08:29 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	73	sybreon	`// Revision 1.10 2007/11/16 21:52:03 sybreon`
24			`// Added fsl_tag_o to FSL bus (tag either address or data).`
25			`//`
26	66	sybreon	`// Revision 1.9 2007/11/14 23:19:24 sybreon`
27			`// Fixed minor typo.`
28			`//`
29	62	sybreon	`// Revision 1.8 2007/11/14 22:14:34 sybreon`
30			`// Changed interrupt handling system (reported by M. Ettus).`
31			`//`
32	61	sybreon	`// Revision 1.7 2007/11/10 16:39:38 sybreon`
33			`// Upgraded license to LGPLv3.`
34			`// Significant performance optimisations.`
35			`//`
36	55	sybreon	`// Revision 1.6 2007/11/09 20:51:52 sybreon`
37			`// Added GET/PUT support through a FSL bus.`
38			`//`
39	53	sybreon	`// Revision 1.5 2007/11/08 17:48:14 sybreon`
40			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
41			`//`
42	51	sybreon	`// Revision 1.4 2007/11/08 14:17:47 sybreon`
43			`// Parameterised optional components.`
44			`//`
45	50	sybreon	`// Revision 1.3 2007/11/03 08:34:55 sybreon`
46			`// Minor code cleanup.`
47			`//`
48	45	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
49			`// Added better (beta) interrupt support.`
50			`// Changed MSR_IE to disabled at reset as per MB docs.`
51			`//`
52	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
53			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
54			`// Fixed various minor data hazard bugs.`
55			`// Code compatible with -O0/1/2/3/s generated code.`
56			`//`
57	41	sybreon
58			`module aeMB_edk32 (/AUTOARG/`
59			`// Outputs`
60	66	sybreon	`iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,`
61			`fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,`
62	41	sybreon	`// Inputs`
63	61	sybreon	`sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,`
64			`dwb_ack_i, sys_clk_i, sys_rst_i`
65	41	sybreon	`);`
66	50	sybreon	`// Bus widths`
67			`parameter IW = 32; /// Instruction bus address width`
68			`parameter DW = 32; /// Data bus address width`
69	41	sybreon
70	50	sybreon	`// Optional functions`
71			`parameter MUL = 1; // Multiplier`
72			`parameter BSF = 1; // Barrel Shifter`
73	41	sybreon
74			`/AUTOOUTPUT/`
75			`// Beginning of automatic outputs (from unused autoinst outputs)`
76			`output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v`
77			`output [31:0] dwb_dat_o; // From regf of aeMB_regf.v`
78			`output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v`
79			`output dwb_stb_o; // From ctrl of aeMB_ctrl.v`
80			`output dwb_wre_o; // From ctrl of aeMB_ctrl.v`
81	66	sybreon	`output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v`
82	53	sybreon	`output [31:0] fsl_dat_o; // From regf of aeMB_regf.v`
83			`output fsl_stb_o; // From ctrl of aeMB_ctrl.v`
84	66	sybreon	`output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v`
85	53	sybreon	`output fsl_wre_o; // From ctrl of aeMB_ctrl.v`
86	41	sybreon	`output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v`
87			`output iwb_stb_o; // From ibuf of aeMB_ibuf.v`
88			`// End of automatics`
89			`/AUTOINPUT/`
90			`// Beginning of automatic inputs (from unused autoinst inputs)`
91	61	sybreon	`input dwb_ack_i; // To ctrl of aeMB_ctrl.v`
92	41	sybreon	`input [31:0] dwb_dat_i; // To regf of aeMB_regf.v`
93	61	sybreon	`input fsl_ack_i; // To ctrl of aeMB_ctrl.v`
94	53	sybreon	`input [31:0] fsl_dat_i; // To regf of aeMB_regf.v`
95	61	sybreon	`input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...`
96			`input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v`
97			`input sys_int_i; // To ibuf of aeMB_ibuf.v`
98	41	sybreon	`// End of automatics`
99			`/AUTOWIRE/`
100			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
101			`wire [10:0] rALT; // From ibuf of aeMB_ibuf.v`
102			`wire rBRA; // From bpcu of aeMB_bpcu.v`
103			`wire rDLY; // From bpcu of aeMB_bpcu.v`
104			`wire [31:0] rDWBDI; // From regf of aeMB_regf.v`
105			`wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v`
106			`wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v`
107	44	sybreon	`wire rMSR_BIP; // From xecu of aeMB_xecu.v`
108	41	sybreon	`wire rMSR_IE; // From xecu of aeMB_xecu.v`
109			`wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v`
110			`wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v`
111			`wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v`
112			`wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v`
113			`wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v`
114			`wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v`
115			`wire [31:2] rPC; // From bpcu of aeMB_bpcu.v`
116			`wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v`
117			`wire [4:0] rRA; // From ibuf of aeMB_ibuf.v`
118			`wire [4:0] rRB; // From ibuf of aeMB_ibuf.v`
119			`wire [4:0] rRD; // From ibuf of aeMB_ibuf.v`
120			`wire [31:0] rREGA; // From regf of aeMB_regf.v`
121			`wire [31:0] rREGB; // From regf of aeMB_regf.v`
122			`wire [31:0] rRESULT; // From xecu of aeMB_xecu.v`
123			`wire [4:0] rRW; // From ctrl of aeMB_ctrl.v`
124			`wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v`
125	61	sybreon	`wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v`
126	41	sybreon	`// End of automatics`
127	61	sybreon
128			`input sys_clk_i;`
129			`input sys_rst_i;`
130	73	sybreon
131	61	sybreon	`wire grst = sys_rst_i;`
132			`wire gclk = sys_clk_i;`
133			`wire gena = !((dwb_stb_o ^ dwb_ack_i) \| (fsl_stb_o ^ fsl_ack_i) \| !iwb_ack_i);`
134	73	sybreon
135			`// --- INSTANTIATIONS -------------------------------------`
136	50	sybreon
137	41	sybreon	`aeMB_ibuf`
138			`ibuf (/AUTOINST/`
139			`// Outputs`
140			`.rIMM (rIMM[15:0]),`
141			`.rRA (rRA[4:0]),`
142			`.rRD (rRD[4:0]),`
143			`.rRB (rRB[4:0]),`
144			`.rALT (rALT[10:0]),`
145			`.rOPC (rOPC[5:0]),`
146			`.rSIMM (rSIMM[31:0]),`
147	61	sybreon	`.xIREG (xIREG[31:0]),`
148	41	sybreon	`.iwb_stb_o (iwb_stb_o),`
149			`// Inputs`
150			`.rBRA (rBRA),`
151	61	sybreon	`.rMSR_IE (rMSR_IE),`
152			`.rMSR_BIP (rMSR_BIP),`
153	41	sybreon	`.iwb_dat_i (iwb_dat_i[31:0]),`
154			`.iwb_ack_i (iwb_ack_i),`
155	61	sybreon	`.sys_int_i (sys_int_i),`
156	41	sybreon	`.gclk (gclk),`
157			`.grst (grst),`
158			`.gena (gena));`
159
160			`aeMB_ctrl`
161			`ctrl (/AUTOINST/`
162			`// Outputs`
163			`.rMXDST (rMXDST[1:0]),`
164			`.rMXSRC (rMXSRC[1:0]),`
165			`.rMXTGT (rMXTGT[1:0]),`
166			`.rMXALT (rMXALT[1:0]),`
167			`.rMXALU (rMXALU[2:0]),`
168			`.rRW (rRW[4:0]),`
169			`.dwb_stb_o (dwb_stb_o),`
170			`.dwb_wre_o (dwb_wre_o),`
171	53	sybreon	`.fsl_stb_o (fsl_stb_o),`
172			`.fsl_wre_o (fsl_wre_o),`
173	41	sybreon	`// Inputs`
174			`.rDLY (rDLY),`
175			`.rIMM (rIMM[15:0]),`
176			`.rALT (rALT[10:0]),`
177			`.rOPC (rOPC[5:0]),`
178			`.rRD (rRD[4:0]),`
179			`.rRA (rRA[4:0]),`
180			`.rRB (rRB[4:0]),`
181			`.rPC (rPC[31:2]),`
182			`.rBRA (rBRA),`
183			`.rMSR_IE (rMSR_IE),`
184	61	sybreon	`.xIREG (xIREG[31:0]),`
185	50	sybreon	`.dwb_ack_i (dwb_ack_i),`
186	51	sybreon	`.iwb_ack_i (iwb_ack_i),`
187	53	sybreon	`.fsl_ack_i (fsl_ack_i),`
188	41	sybreon	`.gclk (gclk),`
189			`.grst (grst),`
190	44	sybreon	`.gena (gena));`
191	41	sybreon
192			`aeMB_bpcu #(IW)`
193			`bpcu (/AUTOINST/`
194			`// Outputs`
195			`.iwb_adr_o (iwb_adr_o[IW-1:2]),`
196			`.rPC (rPC[31:2]),`
197			`.rPCLNK (rPCLNK[31:2]),`
198			`.rBRA (rBRA),`
199			`.rDLY (rDLY),`
200			`// Inputs`
201			`.rMXALT (rMXALT[1:0]),`
202			`.rOPC (rOPC[5:0]),`
203			`.rRD (rRD[4:0]),`
204			`.rRA (rRA[4:0]),`
205			`.rRESULT (rRESULT[31:0]),`
206			`.rDWBDI (rDWBDI[31:0]),`
207			`.rREGA (rREGA[31:0]),`
208			`.gclk (gclk),`
209			`.grst (grst),`
210			`.gena (gena));`
211
212			`aeMB_regf`
213			`regf (/AUTOINST/`
214			`// Outputs`
215			`.rREGA (rREGA[31:0]),`
216			`.rREGB (rREGB[31:0]),`
217			`.rDWBDI (rDWBDI[31:0]),`
218			`.dwb_dat_o (dwb_dat_o[31:0]),`
219	53	sybreon	`.fsl_dat_o (fsl_dat_o[31:0]),`
220	41	sybreon	`// Inputs`
221			`.rOPC (rOPC[5:0]),`
222			`.rRA (rRA[4:0]),`
223			`.rRB (rRB[4:0]),`
224			`.rRW (rRW[4:0]),`
225			`.rRD (rRD[4:0]),`
226			`.rMXDST (rMXDST[1:0]),`
227			`.rPCLNK (rPCLNK[31:2]),`
228			`.rRESULT (rRESULT[31:0]),`
229			`.rDWBSEL (rDWBSEL[3:0]),`
230			`.rBRA (rBRA),`
231			`.rDLY (rDLY),`
232			`.dwb_dat_i (dwb_dat_i[31:0]),`
233	53	sybreon	`.fsl_dat_i (fsl_dat_i[31:0]),`
234	41	sybreon	`.gclk (gclk),`
235			`.grst (grst),`
236			`.gena (gena));`
237
238	50	sybreon	`aeMB_xecu #(DW, MUL, BSF)`
239			`xecu (/AUTOINST/`
240	41	sybreon	`// Outputs`
241			`.dwb_adr_o (dwb_adr_o[DW-1:2]),`
242			`.dwb_sel_o (dwb_sel_o[3:0]),`
243	66	sybreon	`.fsl_adr_o (fsl_adr_o[6:2]),`
244			`.fsl_tag_o (fsl_tag_o[1:0]),`
245	41	sybreon	`.rRESULT (rRESULT[31:0]),`
246			`.rDWBSEL (rDWBSEL[3:0]),`
247			`.rMSR_IE (rMSR_IE),`
248	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
249	41	sybreon	`// Inputs`
250			`.rREGA (rREGA[31:0]),`
251			`.rREGB (rREGB[31:0]),`
252			`.rMXSRC (rMXSRC[1:0]),`
253			`.rMXTGT (rMXTGT[1:0]),`
254			`.rRA (rRA[4:0]),`
255	53	sybreon	`.rRB (rRB[4:0]),`
256	41	sybreon	`.rMXALU (rMXALU[2:0]),`
257			`.rBRA (rBRA),`
258			`.rDLY (rDLY),`
259	50	sybreon	`.rALT (rALT[10:0]),`
260	41	sybreon	`.rSIMM (rSIMM[31:0]),`
261			`.rIMM (rIMM[15:0]),`
262			`.rOPC (rOPC[5:0]),`
263			`.rRD (rRD[4:0]),`
264			`.rDWBDI (rDWBDI[31:0]),`
265			`.rPC (rPC[31:2]),`
266			`.gclk (gclk),`
267			`.grst (grst),`
268			`.gena (gena));`
269
270	73	sybreon
271			`// --- SIMULATION KERNEL ----------------------------------`
272			`// synopsys translate_off`
273
274			`ifdef AEMB_SIMULATION_KERNEL
275
276			`wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};`
277			`wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};`
278			`wire [1:0] wBRA = {rBRA, rDLY};`
279			`wire [3:0] wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE, xecu.rMSR_BE};`
280
281			`always @(posedge gclk) if (gena) begin`
282	41	sybreon
283	73	sybreon	`$write ("\n", ($stime/10));`
284			`$writeh (" PC=", iwb_adr );`
285			`$writeh ("\t");`
286
287			`case (wBRA)`
288			`2'b00: $write(" ");`
289			`2'b01: $write(".");`
290			`2'b10: $write("-");`
291			`2'b11: $write("+");`
292			`endcase // case (wBRA)`
293
294			`case (rOPC)`
295			`6'o00: if (rRD == 0) $write(" "); else $write("ADD");`
296			`6'o01: $write("RSUB");`
297			`6'o02: $write("ADDC");`
298			`6'o03: $write("RSUBC");`
299			`6'o04: $write("ADDK");`
300			`6'o05: case (rIMM[1:0])`
301			`2'o0: $write("RSUBK");`
302			`2'o1: $write("CMP");`
303			`2'o3: $write("CMPU");`
304			`default: $write("XXX");`
305			`endcase // case (rIMM[1:0])`
306			`6'o06: $write("ADDKC");`
307			`6'o07: $write("RSUBKC");`
308
309			`6'o10: $write("ADDI");`
310			`6'o11: $write("RSUBI");`
311			`6'o12: $write("ADDIC");`
312			`6'o13: $write("RSUBIC");`
313			`6'o14: $write("ADDIK");`
314			`6'o15: $write("RSUBIK");`
315			`6'o16: $write("ADDIKC");`
316			`6'o17: $write("RSUBIKC");`
317
318			`6'o20: $write("MUL");`
319			`6'o21: case (rALT[10:9])`
320			`2'o0: $write("BSRL");`
321			`2'o1: $write("BSRA");`
322			`2'o2: $write("BSLL");`
323			`default: $write("XXX");`
324			`endcase // case (rALT[10:9])`
325			`6'o22: $write("IDIV");`
326
327			`6'o30: $write("MULI");`
328			`6'o31: case (rALT[10:9])`
329			`2'o0: $write("BSRLI");`
330			`2'o1: $write("BSRAI");`
331			`2'o2: $write("BSLLI");`
332			`default: $write("XXX");`
333			`endcase // case (rALT[10:9])`
334			`6'o33: case (rRB[4:2])`
335			`3'o0: $write("GET");`
336			`3'o4: $write("PUT");`
337			`3'o2: $write("NGET");`
338			`3'o6: $write("NPUT");`
339			`3'o1: $write("CGET");`
340			`3'o5: $write("CPUT");`
341			`3'o3: $write("NCGET");`
342			`3'o7: $write("NCPUT");`
343			`endcase // case (rRB[4:2])`
344
345			`6'o40: $write("OR");`
346			`6'o41: $write("AND");`
347			`6'o42: if (rRD == 0) $write(" "); else $write("XOR");`
348			`6'o43: $write("ANDN");`
349			`6'o44: case (rIMM[6:5])`
350			`2'o0: $write("SRA");`
351			`2'o1: $write("SRC");`
352			`2'o2: $write("SRL");`
353			`2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8");`
354			`endcase // case (rIMM[6:5])`
355
356			`6'o45: $write("MOV");`
357			`6'o46: case (rRA[3:2])`
358			`3'o0: $write("BR");`
359			`3'o1: $write("BRL");`
360			`3'o2: $write("BRA");`
361			`3'o3: $write("BRAL");`
362			`endcase // case (rRA[3:2])`
363
364			`6'o47: case (rRD[2:0])`
365			`3'o0: $write("BEQ");`
366			`3'o1: $write("BNE");`
367			`3'o2: $write("BLT");`
368			`3'o3: $write("BLE");`
369			`3'o4: $write("BGT");`
370			`3'o5: $write("BGE");`
371			`default: $write("XXX");`
372			`endcase // case (rRD[2:0])`
373
374			`6'o50: $write("ORI");`
375			`6'o51: $write("ANDI");`
376			`6'o52: $write("XORI");`
377			`6'o53: $write("ANDNI");`
378			`6'o54: $write("IMMI");`
379			`6'o55: case (rRD[1:0])`
380			`2'o0: $write("RTSD");`
381			`2'o1: $write("RTID");`
382			`2'o2: $write("RTBD");`
383			`default: $write("XXX");`
384			`endcase // case (rRD[1:0])`
385			`6'o56: case (rRA[3:2])`
386			`3'o0: $write("BRI");`
387			`3'o1: $write("BRLI");`
388			`3'o2: $write("BRAI");`
389			`3'o3: $write("BRALI");`
390			`endcase // case (rRA[3:2])`
391			`6'o57: case (rRD[2:0])`
392			`3'o0: $write("BEQI");`
393			`3'o1: $write("BNEI");`
394			`3'o2: $write("BLTI");`
395			`3'o3: $write("BLEI");`
396			`3'o4: $write("BGTI");`
397			`3'o5: $write("BGEI");`
398			`default: $write("XXX");`
399			`endcase // case (rRD[2:0])`
400
401			`6'o60: $write("LBU");`
402			`6'o61: $write("LHU");`
403			`6'o62: $write("LW");`
404			`6'o64: $write("SB");`
405			`6'o65: $write("SH");`
406			`6'o66: $write("SW");`
407
408			`6'o70: $write("LBUI");`
409			`6'o71: $write("LHUI");`
410			`6'o72: $write("LWI");`
411			`6'o74: $write("SBI");`
412			`6'o75: $write("SHI");`
413			`6'o76: $write("SWI");`
414
415			`default: $write("XXX");`
416			`endcase // case (rOPC)`
417
418			`case (rOPC[3])`
419			`1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM);`
420			`1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB," ");`
421			`endcase // case (rOPC[3])`
422
423
424			`// ALU`
425			`$write("\t");`
426			`$writeh(" A=",xecu.rOPA);`
427			`$writeh(" B=",xecu.rOPB);`
428
429			`case (rMXALU)`
430			`3'o0: $write(" ADD");`
431			`3'o1: $write(" LOG");`
432			`3'o2: $write(" SFT");`
433			`3'o3: $write(" MOV");`
434			`3'o4: $write(" MUL");`
435			`3'o5: $write(" BSF");`
436			`default: $write(" XXX");`
437			`endcase // case (rMXALU)`
438			`$writeh("=h",xecu.xRESULT);`
439
440			`// WRITEBACK`
441			`$writeh("\tSR=", wMSR," ");`
442
443			`if (regf.fRDWE) begin`
444			`case (rMXDST)`
445			`2'o2: begin`
446			`if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")");`
447			`if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")");`
448			`end`
449			`2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")");`
450			`2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")");`
451			`endcase // case (rMXDST)`
452			`end`
453
454			`// STORE`
455			`if (dwb_stb_o & dwb_wre_o) begin`
456			`$writeh("RAM(", dwb_adr ,")=", dwb_dat_o);`
457			`case (dwb_sel_o)`
458			`4'hF: $write(":L");`
459			`4'h3,4'hC: $write(":W");`
460			`4'h1,4'h2,4'h4,4'h8: $write(":B");`
461			`endcase // case (dwb_sel_o)`
462
463			`end`
464
465			`end // if (gena)`
466
467			`endif // `ifdef AEMB_SIMULATION_KERNEL
468			`// synopsys translate_on`
469
470	41	sybreon	`endmodule // aeMB_edk32`

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