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sybreon |
// $Id: aeMB_edk32.v,v 1.1 2007-11-02 03:25:40 sybreon Exp $
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//
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// AEMB EDK 3.2 Compatible Core
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public License
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// as published by the Free Software Foundation; either version 2.1 of
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// the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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// $Log: not supported by cvs2svn $
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module aeMB_edk32 (/*AUTOARG*/
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// Outputs
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iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_adr_o,
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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dwb_ack_i
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);
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parameter IW = 32;
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parameter DW = 32;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
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output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
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output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v
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output dwb_stb_o; // From ctrl of aeMB_ctrl.v
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output dwb_wre_o; // From ctrl of aeMB_ctrl.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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// End of automatics
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To scon of aeMB_scon.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input iwb_ack_i; // To scon of aeMB_scon.v, ...
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input sys_clk_i; // To scon of aeMB_scon.v
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input sys_int_i; // To scon of aeMB_scon.v, ...
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input sys_rst_i; // To scon of aeMB_scon.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire gclk; // From scon of aeMB_scon.v
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wire gena; // From scon of aeMB_scon.v
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wire grst; // From scon of aeMB_scon.v
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wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
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wire rBRA; // From bpcu of aeMB_bpcu.v
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wire rDLY; // From bpcu of aeMB_bpcu.v
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wire [31:0] rDWBDI; // From regf of aeMB_regf.v
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wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
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wire rDWBSTB; // From ctrl of aeMB_ctrl.v
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wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
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wire rMSR_IE; // From xecu of aeMB_xecu.v
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wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
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wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v
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wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v
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wire [31:2] rPC; // From bpcu of aeMB_bpcu.v
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wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v
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wire [4:0] rRA; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRB; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRD; // From ibuf of aeMB_ibuf.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [1:0] rXCE; // From ctrl of aeMB_ctrl.v
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// End of automatics
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wire [31:0] rOPA, rOPB;
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wire [31:0] rRES_MUL, rRES_BSF;
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/*
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aeMB_mult
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mult (
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// Outputs
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.rRES_MUL (rRES_MUL[31:0]),
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// Inputs
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]));
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*/
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aeMB_bsft
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bsft (
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// Outputs
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.rRES_BSF (rRES_BSF[31:0]),
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// Inputs
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]),
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.rALT (rALT[10:0]));
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// --- NON-OPTIONAL COMPONENTS -------------------------------
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aeMB_scon
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scon (/*AUTOINST*/
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// Outputs
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.grst (grst),
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.gclk (gclk),
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.gena (gena),
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// Inputs
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.rOPC (rOPC[5:0]),
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.rDWBSTB (rDWBSTB),
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.dwb_ack_i (dwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.rMSR_IE (rMSR_IE),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.sys_clk_i (sys_clk_i),
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.sys_rst_i (sys_rst_i),
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.sys_int_i (sys_int_i));
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aeMB_ibuf
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ibuf (/*AUTOINST*/
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// Outputs
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.rIMM (rIMM[15:0]),
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.rRA (rRA[4:0]),
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.rRD (rRD[4:0]),
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.rRB (rRB[4:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rSIMM (rSIMM[31:0]),
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.iwb_stb_o (iwb_stb_o),
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// Inputs
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.rBRA (rBRA),
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.rXCE (rXCE[1:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.gclk (gclk),
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.grst (grst),
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.gena (gena));
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aeMB_ctrl
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ctrl (/*AUTOINST*/
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// Outputs
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.rMXDST (rMXDST[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rMXALU (rMXALU[2:0]),
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.rRW (rRW[4:0]),
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.rDWBSTB (rDWBSTB),
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.rXCE (rXCE[1:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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// Inputs
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.rDLY (rDLY),
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.rIMM (rIMM[15:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rPC (rPC[31:2]),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.gclk (gclk),
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.grst (grst),
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.gena (gena),
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.sys_int_i (sys_int_i));
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aeMB_bpcu #(IW)
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bpcu (/*AUTOINST*/
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// Outputs
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.iwb_adr_o (iwb_adr_o[IW-1:2]),
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.rPC (rPC[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rBRA (rBRA),
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.rDLY (rDLY),
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// Inputs
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.rMXALT (rMXALT[1:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rREGA (rREGA[31:0]),
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.rXCE (rXCE[1:0]),
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.gclk (gclk),
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.grst (grst),
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.gena (gena));
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aeMB_regf
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regf (/*AUTOINST*/
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// Outputs
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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// Inputs
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.rOPC (rOPC[5:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRW (rRW[4:0]),
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.rRD (rRD[4:0]),
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.rMXDST (rMXDST[1:0]),
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.rPCLNK (rPCLNK[31:2]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.gclk (gclk),
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.grst (grst),
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.gena (gena));
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aeMB_xecu #(DW)
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xecu (
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]),
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/*AUTOINST*/
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// Outputs
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.dwb_adr_o (dwb_adr_o[DW-1:2]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rMSR_IE (rMSR_IE),
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// Inputs
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
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.rMXALU (rMXALU[2:0]),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rXCE (rXCE[1:0]),
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.rSIMM (rSIMM[31:0]),
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.rIMM (rIMM[15:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rPC (rPC[31:2]),
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.rRES_MUL (rRES_MUL[31:0]),
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.rRES_BSF (rRES_BSF[31:0]),
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.gclk (gclk),
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.grst (grst),
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.gena (gena));
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endmodule // aeMB_edk32
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