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// $Id: aeMB_edk32.v,v 1.3 2007-11-03 08:34:55 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation; either version 2.1 of
// the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//  
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_edk32 (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
   dwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
   dwb_ack_i
   );
 
   parameter IW = 32;
   parameter DW = 32;
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To scon of aeMB_scon.v
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
   input                iwb_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v
   input                sys_clk_i;              // To scon of aeMB_scon.v
   input                sys_int_i;              // To scon of aeMB_scon.v
   input                sys_rst_i;              // To scon of aeMB_scon.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 gclk;                   // From scon of aeMB_scon.v
   wire                 gena;                   // From scon of aeMB_scon.v
   wire                 grst;                   // From scon of aeMB_scon.v
   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
   wire [1:0]            rATOM;                  // From bpcu of aeMB_bpcu.v
   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
   wire                 rDWBSTB;                // From ctrl of aeMB_ctrl.v
   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
   wire [1:0]            rXCE;                   // From scon of aeMB_scon.v
   // End of automatics
 
   wire [31:0]           rOPA, rOPB;
   wire [31:0]           rRES_MUL, rRES_BSF;
 
   // --- OPTIONAL COMPONENTS -----------------------------------
   // Trade off hardware size/speed for software speed
 
   aeMB_mult
     mult (
           // Outputs
           .rRES_MUL                    (rRES_MUL[31:0]),
           // Inputs
           .rOPA                        (rOPA[31:0]),
           .rOPB                        (rOPB[31:0]));
 
   aeMB_bsft
     bsft (
           // Outputs
           .rRES_BSF                    (rRES_BSF[31:0]),
           // Inputs
           .rOPA                        (rOPA[31:0]),
           .rOPB                        (rOPB[31:0]),
           .rALT                        (rALT[10:0]));
 
 
   // --- NON-OPTIONAL COMPONENTS -------------------------------
   // These components make up the main AEMB processor.
 
   aeMB_scon
     scon (/*AUTOINST*/
           // Outputs
           .rXCE                        (rXCE[1:0]),
           .grst                        (grst),
           .gclk                        (gclk),
           .gena                        (gena),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rATOM                       (rATOM[1:0]),
           .rDWBSTB                     (rDWBSTB),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .sys_clk_i                   (sys_clk_i),
           .sys_rst_i                   (sys_rst_i),
           .sys_int_i                   (sys_int_i));
 
   aeMB_ibuf
     ibuf (/*AUTOINST*/
           // Outputs
           .rIMM                        (rIMM[15:0]),
           .rRA                         (rRA[4:0]),
           .rRD                         (rRD[4:0]),
           .rRB                         (rRB[4:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rSIMM                       (rSIMM[31:0]),
           .iwb_stb_o                   (iwb_stb_o),
           // Inputs
           .rBRA                        (rBRA),
           .rXCE                        (rXCE[1:0]),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .iwb_ack_i                   (iwb_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_ctrl
     ctrl (/*AUTOINST*/
           // Outputs
           .rMXDST                      (rMXDST[1:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALT                      (rMXALT[1:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rRW                         (rRW[4:0]),
           .rDWBSTB                     (rDWBSTB),
           .dwb_stb_o                   (dwb_stb_o),
           .dwb_wre_o                   (dwb_wre_o),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rDLY                        (rDLY),
           .rIMM                        (rIMM[15:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rPC                         (rPC[31:2]),
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_bpcu #(IW)
     bpcu (/*AUTOINST*/
           // Outputs
           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
           .rPC                         (rPC[31:2]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rATOM                       (rATOM[1:0]),
           // Inputs
           .rMXALT                      (rMXALT[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rREGA                       (rREGA[31:0]),
           .rXCE                        (rXCE[1:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_regf
     regf (/*AUTOINST*/
           // Outputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .dwb_dat_o                   (dwb_dat_o[31:0]),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rRW                         (rRW[4:0]),
           .rRD                         (rRD[4:0]),
           .rMXDST                      (rMXDST[1:0]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_xecu #(DW)
     xecu (
           .rOPA                        (rOPA[31:0]),
           .rOPB                        (rOPB[31:0]),
           /*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rRA                         (rRA[4:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rSIMM                       (rSIMM[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rPC                         (rPC[31:2]),
           .rRES_MUL                    (rRES_MUL[31:0]),
           .rRES_BSF                    (rRES_BSF[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
 
endmodule // aeMB_edk32

Line No.	Rev	Author	Line
1	45	sybreon	`// $Id: aeMB_edk32.v,v 1.3 2007-11-03 08:34:55 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7			`// This library is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU Lesser General Public License`
9			`// as published by the Free Software Foundation; either version 2.1 of`
10			`// the License, or (at your option) any later version.`
11			`//`
12			`// This library is distributed in the hope that it will be useful, but`
13			`// WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`// Lesser General Public License for more details.`
16			`//`
17			`// You should have received a copy of the GNU Lesser General Public`
18			`// License along with this library; if not, write to the Free Software`
19			`// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
20			`// USA`
21			`//`
22			`// $Log: not supported by cvs2svn $`
23	45	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
24			`// Added better (beta) interrupt support.`
25			`// Changed MSR_IE to disabled at reset as per MB docs.`
26			`//`
27	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
28			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
29			`// Fixed various minor data hazard bugs.`
30			`// Code compatible with -O0/1/2/3/s generated code.`
31			`//`
32	41	sybreon
33			`module aeMB_edk32 (/AUTOARG/`
34			`// Outputs`
35			`iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,`
36			`dwb_adr_o,`
37			`// Inputs`
38			`sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,`
39			`dwb_ack_i`
40			`);`
41
42			`parameter IW = 32;`
43			`parameter DW = 32;`
44
45			`/AUTOOUTPUT/`
46			`// Beginning of automatic outputs (from unused autoinst outputs)`
47			`output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v`
48			`output [31:0] dwb_dat_o; // From regf of aeMB_regf.v`
49			`output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v`
50			`output dwb_stb_o; // From ctrl of aeMB_ctrl.v`
51			`output dwb_wre_o; // From ctrl of aeMB_ctrl.v`
52			`output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v`
53			`output iwb_stb_o; // From ibuf of aeMB_ibuf.v`
54			`// End of automatics`
55			`/AUTOINPUT/`
56			`// Beginning of automatic inputs (from unused autoinst inputs)`
57			`input dwb_ack_i; // To scon of aeMB_scon.v`
58			`input [31:0] dwb_dat_i; // To regf of aeMB_regf.v`
59			`input iwb_ack_i; // To scon of aeMB_scon.v, ...`
60			`input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v`
61			`input sys_clk_i; // To scon of aeMB_scon.v`
62	44	sybreon	`input sys_int_i; // To scon of aeMB_scon.v`
63	41	sybreon	`input sys_rst_i; // To scon of aeMB_scon.v`
64			`// End of automatics`
65			`/AUTOWIRE/`
66			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
67			`wire gclk; // From scon of aeMB_scon.v`
68			`wire gena; // From scon of aeMB_scon.v`
69			`wire grst; // From scon of aeMB_scon.v`
70			`wire [10:0] rALT; // From ibuf of aeMB_ibuf.v`
71	44	sybreon	`wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v`
72	41	sybreon	`wire rBRA; // From bpcu of aeMB_bpcu.v`
73			`wire rDLY; // From bpcu of aeMB_bpcu.v`
74			`wire [31:0] rDWBDI; // From regf of aeMB_regf.v`
75			`wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v`
76			`wire rDWBSTB; // From ctrl of aeMB_ctrl.v`
77			`wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v`
78	44	sybreon	`wire rMSR_BIP; // From xecu of aeMB_xecu.v`
79	41	sybreon	`wire rMSR_IE; // From xecu of aeMB_xecu.v`
80			`wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v`
81			`wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v`
82			`wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v`
83			`wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v`
84			`wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v`
85			`wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v`
86			`wire [31:2] rPC; // From bpcu of aeMB_bpcu.v`
87			`wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v`
88			`wire [4:0] rRA; // From ibuf of aeMB_ibuf.v`
89			`wire [4:0] rRB; // From ibuf of aeMB_ibuf.v`
90			`wire [4:0] rRD; // From ibuf of aeMB_ibuf.v`
91			`wire [31:0] rREGA; // From regf of aeMB_regf.v`
92			`wire [31:0] rREGB; // From regf of aeMB_regf.v`
93			`wire [31:0] rRESULT; // From xecu of aeMB_xecu.v`
94			`wire [4:0] rRW; // From ctrl of aeMB_ctrl.v`
95			`wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v`
96	44	sybreon	`wire [1:0] rXCE; // From scon of aeMB_scon.v`
97	41	sybreon	`// End of automatics`
98
99			`wire [31:0] rOPA, rOPB;`
100			`wire [31:0] rRES_MUL, rRES_BSF;`
101	44	sybreon
102			`// --- OPTIONAL COMPONENTS -----------------------------------`
103			`// Trade off hardware size/speed for software speed`
104	41	sybreon
105			`aeMB_mult`
106			`mult (`
107			`// Outputs`
108			`.rRES_MUL (rRES_MUL[31:0]),`
109			`// Inputs`
110			`.rOPA (rOPA[31:0]),`
111			`.rOPB (rOPB[31:0]));`
112	45	sybreon
113	41	sybreon	`aeMB_bsft`
114			`bsft (`
115			`// Outputs`
116			`.rRES_BSF (rRES_BSF[31:0]),`
117			`// Inputs`
118			`.rOPA (rOPA[31:0]),`
119			`.rOPB (rOPB[31:0]),`
120			`.rALT (rALT[10:0]));`
121	45	sybreon
122	41	sybreon
123			`// --- NON-OPTIONAL COMPONENTS -------------------------------`
124	44	sybreon	`// These components make up the main AEMB processor.`
125	41	sybreon
126			`aeMB_scon`
127			`scon (/AUTOINST/`
128			`// Outputs`
129	44	sybreon	`.rXCE (rXCE[1:0]),`
130	41	sybreon	`.grst (grst),`
131			`.gclk (gclk),`
132			`.gena (gena),`
133			`// Inputs`
134			`.rOPC (rOPC[5:0]),`
135	44	sybreon	`.rATOM (rATOM[1:0]),`
136	41	sybreon	`.rDWBSTB (rDWBSTB),`
137			`.dwb_ack_i (dwb_ack_i),`
138			`.iwb_ack_i (iwb_ack_i),`
139			`.rMSR_IE (rMSR_IE),`
140	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
141	41	sybreon	`.rBRA (rBRA),`
142			`.rDLY (rDLY),`
143			`.sys_clk_i (sys_clk_i),`
144			`.sys_rst_i (sys_rst_i),`
145			`.sys_int_i (sys_int_i));`
146
147			`aeMB_ibuf`
148			`ibuf (/AUTOINST/`
149			`// Outputs`
150			`.rIMM (rIMM[15:0]),`
151			`.rRA (rRA[4:0]),`
152			`.rRD (rRD[4:0]),`
153			`.rRB (rRB[4:0]),`
154			`.rALT (rALT[10:0]),`
155			`.rOPC (rOPC[5:0]),`
156			`.rSIMM (rSIMM[31:0]),`
157			`.iwb_stb_o (iwb_stb_o),`
158			`// Inputs`
159			`.rBRA (rBRA),`
160			`.rXCE (rXCE[1:0]),`
161			`.iwb_dat_i (iwb_dat_i[31:0]),`
162			`.iwb_ack_i (iwb_ack_i),`
163			`.gclk (gclk),`
164			`.grst (grst),`
165			`.gena (gena));`
166
167			`aeMB_ctrl`
168			`ctrl (/AUTOINST/`
169			`// Outputs`
170			`.rMXDST (rMXDST[1:0]),`
171			`.rMXSRC (rMXSRC[1:0]),`
172			`.rMXTGT (rMXTGT[1:0]),`
173			`.rMXALT (rMXALT[1:0]),`
174			`.rMXALU (rMXALU[2:0]),`
175			`.rRW (rRW[4:0]),`
176			`.rDWBSTB (rDWBSTB),`
177			`.dwb_stb_o (dwb_stb_o),`
178			`.dwb_wre_o (dwb_wre_o),`
179			`// Inputs`
180	44	sybreon	`.rXCE (rXCE[1:0]),`
181	41	sybreon	`.rDLY (rDLY),`
182			`.rIMM (rIMM[15:0]),`
183			`.rALT (rALT[10:0]),`
184			`.rOPC (rOPC[5:0]),`
185			`.rRD (rRD[4:0]),`
186			`.rRA (rRA[4:0]),`
187			`.rRB (rRB[4:0]),`
188			`.rPC (rPC[31:2]),`
189			`.rBRA (rBRA),`
190			`.rMSR_IE (rMSR_IE),`
191			`.gclk (gclk),`
192			`.grst (grst),`
193	44	sybreon	`.gena (gena));`
194	41	sybreon
195			`aeMB_bpcu #(IW)`
196			`bpcu (/AUTOINST/`
197			`// Outputs`
198			`.iwb_adr_o (iwb_adr_o[IW-1:2]),`
199			`.rPC (rPC[31:2]),`
200			`.rPCLNK (rPCLNK[31:2]),`
201			`.rBRA (rBRA),`
202			`.rDLY (rDLY),`
203	44	sybreon	`.rATOM (rATOM[1:0]),`
204	41	sybreon	`// Inputs`
205			`.rMXALT (rMXALT[1:0]),`
206			`.rOPC (rOPC[5:0]),`
207			`.rRD (rRD[4:0]),`
208			`.rRA (rRA[4:0]),`
209			`.rRESULT (rRESULT[31:0]),`
210			`.rDWBDI (rDWBDI[31:0]),`
211			`.rREGA (rREGA[31:0]),`
212			`.rXCE (rXCE[1:0]),`
213			`.gclk (gclk),`
214			`.grst (grst),`
215			`.gena (gena));`
216
217			`aeMB_regf`
218			`regf (/AUTOINST/`
219			`// Outputs`
220			`.rREGA (rREGA[31:0]),`
221			`.rREGB (rREGB[31:0]),`
222			`.rDWBDI (rDWBDI[31:0]),`
223			`.dwb_dat_o (dwb_dat_o[31:0]),`
224			`// Inputs`
225			`.rOPC (rOPC[5:0]),`
226			`.rRA (rRA[4:0]),`
227			`.rRB (rRB[4:0]),`
228			`.rRW (rRW[4:0]),`
229			`.rRD (rRD[4:0]),`
230			`.rMXDST (rMXDST[1:0]),`
231			`.rPCLNK (rPCLNK[31:2]),`
232			`.rRESULT (rRESULT[31:0]),`
233			`.rDWBSEL (rDWBSEL[3:0]),`
234			`.rBRA (rBRA),`
235			`.rDLY (rDLY),`
236			`.dwb_dat_i (dwb_dat_i[31:0]),`
237			`.gclk (gclk),`
238			`.grst (grst),`
239			`.gena (gena));`
240
241			`aeMB_xecu #(DW)`
242			`xecu (`
243			`.rOPA (rOPA[31:0]),`
244			`.rOPB (rOPB[31:0]),`
245			`/AUTOINST/`
246			`// Outputs`
247			`.dwb_adr_o (dwb_adr_o[DW-1:2]),`
248			`.dwb_sel_o (dwb_sel_o[3:0]),`
249			`.rRESULT (rRESULT[31:0]),`
250			`.rDWBSEL (rDWBSEL[3:0]),`
251			`.rMSR_IE (rMSR_IE),`
252	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
253	41	sybreon	`// Inputs`
254	44	sybreon	`.rXCE (rXCE[1:0]),`
255	41	sybreon	`.rREGA (rREGA[31:0]),`
256			`.rREGB (rREGB[31:0]),`
257			`.rMXSRC (rMXSRC[1:0]),`
258			`.rMXTGT (rMXTGT[1:0]),`
259			`.rRA (rRA[4:0]),`
260			`.rMXALU (rMXALU[2:0]),`
261			`.rBRA (rBRA),`
262			`.rDLY (rDLY),`
263			`.rSIMM (rSIMM[31:0]),`
264			`.rIMM (rIMM[15:0]),`
265			`.rOPC (rOPC[5:0]),`
266			`.rRD (rRD[4:0]),`
267			`.rDWBDI (rDWBDI[31:0]),`
268			`.rPC (rPC[31:2]),`
269			`.rRES_MUL (rRES_MUL[31:0]),`
270			`.rRES_BSF (rRES_BSF[31:0]),`
271			`.gclk (gclk),`
272			`.grst (grst),`
273			`.gena (gena));`
274
275
276			`endmodule // aeMB_edk32`

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