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// $Id: aeMB_edk32.v,v 1.5 2007-11-08 17:48:14 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation; either version 2.1 of
// the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//  
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.3  2007/11/03 08:34:55  sybreon
// Minor code cleanup.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_edk32 (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
   dwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
   dwb_ack_i
   );
   // Bus widths
   parameter IW = 32; /// Instruction bus address width
   parameter DW = 32; /// Data bus address width
 
   // Optional functions
   parameter MUL = 1; // Multiplier
   parameter BSF = 1; // Barrel Shifter
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
   input                iwb_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v
   input                sys_clk_i;              // To scon of aeMB_scon.v
   input                sys_int_i;              // To scon of aeMB_scon.v
   input                sys_rst_i;              // To scon of aeMB_scon.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 gclk;                   // From scon of aeMB_scon.v
   wire                 gena;                   // From scon of aeMB_scon.v
   wire                 grst;                   // From scon of aeMB_scon.v
   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
   wire [1:0]            rATOM;                  // From bpcu of aeMB_bpcu.v
   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
   wire                 rDWBSTB;                // From ctrl of aeMB_ctrl.v
   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
   wire [1:0]            rXCE;                   // From scon of aeMB_scon.v
   // End of automatics
 
   aeMB_scon
     scon (/*AUTOINST*/
           // Outputs
           .rXCE                        (rXCE[1:0]),
           .grst                        (grst),
           .gclk                        (gclk),
           .gena                        (gena),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rATOM                       (rATOM[1:0]),
           .rDWBSTB                     (rDWBSTB),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .sys_clk_i                   (sys_clk_i),
           .sys_rst_i                   (sys_rst_i),
           .sys_int_i                   (sys_int_i));
 
   aeMB_ibuf
     ibuf (/*AUTOINST*/
           // Outputs
           .rIMM                        (rIMM[15:0]),
           .rRA                         (rRA[4:0]),
           .rRD                         (rRD[4:0]),
           .rRB                         (rRB[4:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rSIMM                       (rSIMM[31:0]),
           .iwb_stb_o                   (iwb_stb_o),
           // Inputs
           .rBRA                        (rBRA),
           .rXCE                        (rXCE[1:0]),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .iwb_ack_i                   (iwb_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_ctrl
     ctrl (/*AUTOINST*/
           // Outputs
           .rMXDST                      (rMXDST[1:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALT                      (rMXALT[1:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rRW                         (rRW[4:0]),
           .rDWBSTB                     (rDWBSTB),
           .dwb_stb_o                   (dwb_stb_o),
           .dwb_wre_o                   (dwb_wre_o),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rDLY                        (rDLY),
           .rIMM                        (rIMM[15:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rPC                         (rPC[31:2]),
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_bpcu #(IW)
     bpcu (/*AUTOINST*/
           // Outputs
           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
           .rPC                         (rPC[31:2]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rATOM                       (rATOM[1:0]),
           // Inputs
           .rMXALT                      (rMXALT[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rREGA                       (rREGA[31:0]),
           .rXCE                        (rXCE[1:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_regf
     regf (/*AUTOINST*/
           // Outputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .dwb_dat_o                   (dwb_dat_o[31:0]),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rRW                         (rRW[4:0]),
           .rRD                         (rRD[4:0]),
           .rMXDST                      (rMXDST[1:0]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_xecu #(DW, MUL, BSF)
     xecu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rRA                         (rRA[4:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rALT                        (rALT[10:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rPC                         (rPC[31:2]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
 
endmodule // aeMB_edk32

Line No.	Rev	Author	Line
1	51	sybreon	`// $Id: aeMB_edk32.v,v 1.5 2007-11-08 17:48:14 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7			`// This library is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU Lesser General Public License`
9			`// as published by the Free Software Foundation; either version 2.1 of`
10			`// the License, or (at your option) any later version.`
11			`//`
12			`// This library is distributed in the hope that it will be useful, but`
13			`// WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`// Lesser General Public License for more details.`
16			`//`
17			`// You should have received a copy of the GNU Lesser General Public`
18			`// License along with this library; if not, write to the Free Software`
19			`// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
20			`// USA`
21			`//`
22			`// $Log: not supported by cvs2svn $`
23	51	sybreon	`// Revision 1.4 2007/11/08 14:17:47 sybreon`
24			`// Parameterised optional components.`
25			`//`
26	50	sybreon	`// Revision 1.3 2007/11/03 08:34:55 sybreon`
27			`// Minor code cleanup.`
28			`//`
29	45	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
30			`// Added better (beta) interrupt support.`
31			`// Changed MSR_IE to disabled at reset as per MB docs.`
32			`//`
33	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
34			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
35			`// Fixed various minor data hazard bugs.`
36			`// Code compatible with -O0/1/2/3/s generated code.`
37			`//`
38	41	sybreon
39			`module aeMB_edk32 (/AUTOARG/`
40			`// Outputs`
41			`iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,`
42			`dwb_adr_o,`
43			`// Inputs`
44			`sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,`
45			`dwb_ack_i`
46			`);`
47	50	sybreon	`// Bus widths`
48			`parameter IW = 32; /// Instruction bus address width`
49			`parameter DW = 32; /// Data bus address width`
50	41	sybreon
51	50	sybreon	`// Optional functions`
52			`parameter MUL = 1; // Multiplier`
53			`parameter BSF = 1; // Barrel Shifter`
54	41	sybreon
55			`/AUTOOUTPUT/`
56			`// Beginning of automatic outputs (from unused autoinst outputs)`
57			`output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v`
58			`output [31:0] dwb_dat_o; // From regf of aeMB_regf.v`
59			`output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v`
60			`output dwb_stb_o; // From ctrl of aeMB_ctrl.v`
61			`output dwb_wre_o; // From ctrl of aeMB_ctrl.v`
62			`output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v`
63			`output iwb_stb_o; // From ibuf of aeMB_ibuf.v`
64			`// End of automatics`
65			`/AUTOINPUT/`
66			`// Beginning of automatic inputs (from unused autoinst inputs)`
67	50	sybreon	`input dwb_ack_i; // To scon of aeMB_scon.v, ...`
68	41	sybreon	`input [31:0] dwb_dat_i; // To regf of aeMB_regf.v`
69			`input iwb_ack_i; // To scon of aeMB_scon.v, ...`
70			`input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v`
71			`input sys_clk_i; // To scon of aeMB_scon.v`
72	44	sybreon	`input sys_int_i; // To scon of aeMB_scon.v`
73	41	sybreon	`input sys_rst_i; // To scon of aeMB_scon.v`
74			`// End of automatics`
75			`/AUTOWIRE/`
76			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
77			`wire gclk; // From scon of aeMB_scon.v`
78			`wire gena; // From scon of aeMB_scon.v`
79			`wire grst; // From scon of aeMB_scon.v`
80			`wire [10:0] rALT; // From ibuf of aeMB_ibuf.v`
81	44	sybreon	`wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v`
82	41	sybreon	`wire rBRA; // From bpcu of aeMB_bpcu.v`
83			`wire rDLY; // From bpcu of aeMB_bpcu.v`
84			`wire [31:0] rDWBDI; // From regf of aeMB_regf.v`
85			`wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v`
86			`wire rDWBSTB; // From ctrl of aeMB_ctrl.v`
87			`wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v`
88	44	sybreon	`wire rMSR_BIP; // From xecu of aeMB_xecu.v`
89	41	sybreon	`wire rMSR_IE; // From xecu of aeMB_xecu.v`
90			`wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v`
91			`wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v`
92			`wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v`
93			`wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v`
94			`wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v`
95			`wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v`
96			`wire [31:2] rPC; // From bpcu of aeMB_bpcu.v`
97			`wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v`
98			`wire [4:0] rRA; // From ibuf of aeMB_ibuf.v`
99			`wire [4:0] rRB; // From ibuf of aeMB_ibuf.v`
100			`wire [4:0] rRD; // From ibuf of aeMB_ibuf.v`
101			`wire [31:0] rREGA; // From regf of aeMB_regf.v`
102			`wire [31:0] rREGB; // From regf of aeMB_regf.v`
103			`wire [31:0] rRESULT; // From xecu of aeMB_xecu.v`
104			`wire [4:0] rRW; // From ctrl of aeMB_ctrl.v`
105			`wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v`
106	44	sybreon	`wire [1:0] rXCE; // From scon of aeMB_scon.v`
107	41	sybreon	`// End of automatics`
108	50	sybreon
109	41	sybreon	`aeMB_scon`
110			`scon (/AUTOINST/`
111			`// Outputs`
112	44	sybreon	`.rXCE (rXCE[1:0]),`
113	41	sybreon	`.grst (grst),`
114			`.gclk (gclk),`
115			`.gena (gena),`
116			`// Inputs`
117			`.rOPC (rOPC[5:0]),`
118	44	sybreon	`.rATOM (rATOM[1:0]),`
119	41	sybreon	`.rDWBSTB (rDWBSTB),`
120			`.dwb_ack_i (dwb_ack_i),`
121			`.iwb_ack_i (iwb_ack_i),`
122			`.rMSR_IE (rMSR_IE),`
123	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
124	41	sybreon	`.rBRA (rBRA),`
125			`.rDLY (rDLY),`
126			`.sys_clk_i (sys_clk_i),`
127			`.sys_rst_i (sys_rst_i),`
128			`.sys_int_i (sys_int_i));`
129
130			`aeMB_ibuf`
131			`ibuf (/AUTOINST/`
132			`// Outputs`
133			`.rIMM (rIMM[15:0]),`
134			`.rRA (rRA[4:0]),`
135			`.rRD (rRD[4:0]),`
136			`.rRB (rRB[4:0]),`
137			`.rALT (rALT[10:0]),`
138			`.rOPC (rOPC[5:0]),`
139			`.rSIMM (rSIMM[31:0]),`
140			`.iwb_stb_o (iwb_stb_o),`
141			`// Inputs`
142			`.rBRA (rBRA),`
143			`.rXCE (rXCE[1:0]),`
144			`.iwb_dat_i (iwb_dat_i[31:0]),`
145			`.iwb_ack_i (iwb_ack_i),`
146			`.gclk (gclk),`
147			`.grst (grst),`
148			`.gena (gena));`
149
150			`aeMB_ctrl`
151			`ctrl (/AUTOINST/`
152			`// Outputs`
153			`.rMXDST (rMXDST[1:0]),`
154			`.rMXSRC (rMXSRC[1:0]),`
155			`.rMXTGT (rMXTGT[1:0]),`
156			`.rMXALT (rMXALT[1:0]),`
157			`.rMXALU (rMXALU[2:0]),`
158			`.rRW (rRW[4:0]),`
159			`.rDWBSTB (rDWBSTB),`
160			`.dwb_stb_o (dwb_stb_o),`
161			`.dwb_wre_o (dwb_wre_o),`
162			`// Inputs`
163	44	sybreon	`.rXCE (rXCE[1:0]),`
164	41	sybreon	`.rDLY (rDLY),`
165			`.rIMM (rIMM[15:0]),`
166			`.rALT (rALT[10:0]),`
167			`.rOPC (rOPC[5:0]),`
168			`.rRD (rRD[4:0]),`
169			`.rRA (rRA[4:0]),`
170			`.rRB (rRB[4:0]),`
171			`.rPC (rPC[31:2]),`
172			`.rBRA (rBRA),`
173			`.rMSR_IE (rMSR_IE),`
174	50	sybreon	`.dwb_ack_i (dwb_ack_i),`
175	51	sybreon	`.iwb_ack_i (iwb_ack_i),`
176	41	sybreon	`.gclk (gclk),`
177			`.grst (grst),`
178	44	sybreon	`.gena (gena));`
179	41	sybreon
180			`aeMB_bpcu #(IW)`
181			`bpcu (/AUTOINST/`
182			`// Outputs`
183			`.iwb_adr_o (iwb_adr_o[IW-1:2]),`
184			`.rPC (rPC[31:2]),`
185			`.rPCLNK (rPCLNK[31:2]),`
186			`.rBRA (rBRA),`
187			`.rDLY (rDLY),`
188	44	sybreon	`.rATOM (rATOM[1:0]),`
189	41	sybreon	`// Inputs`
190			`.rMXALT (rMXALT[1:0]),`
191			`.rOPC (rOPC[5:0]),`
192			`.rRD (rRD[4:0]),`
193			`.rRA (rRA[4:0]),`
194			`.rRESULT (rRESULT[31:0]),`
195			`.rDWBDI (rDWBDI[31:0]),`
196			`.rREGA (rREGA[31:0]),`
197			`.rXCE (rXCE[1:0]),`
198			`.gclk (gclk),`
199			`.grst (grst),`
200			`.gena (gena));`
201
202			`aeMB_regf`
203			`regf (/AUTOINST/`
204			`// Outputs`
205			`.rREGA (rREGA[31:0]),`
206			`.rREGB (rREGB[31:0]),`
207			`.rDWBDI (rDWBDI[31:0]),`
208			`.dwb_dat_o (dwb_dat_o[31:0]),`
209			`// Inputs`
210			`.rOPC (rOPC[5:0]),`
211			`.rRA (rRA[4:0]),`
212			`.rRB (rRB[4:0]),`
213			`.rRW (rRW[4:0]),`
214			`.rRD (rRD[4:0]),`
215			`.rMXDST (rMXDST[1:0]),`
216			`.rPCLNK (rPCLNK[31:2]),`
217			`.rRESULT (rRESULT[31:0]),`
218			`.rDWBSEL (rDWBSEL[3:0]),`
219			`.rBRA (rBRA),`
220			`.rDLY (rDLY),`
221			`.dwb_dat_i (dwb_dat_i[31:0]),`
222			`.gclk (gclk),`
223			`.grst (grst),`
224			`.gena (gena));`
225
226	50	sybreon	`aeMB_xecu #(DW, MUL, BSF)`
227			`xecu (/AUTOINST/`
228	41	sybreon	`// Outputs`
229			`.dwb_adr_o (dwb_adr_o[DW-1:2]),`
230			`.dwb_sel_o (dwb_sel_o[3:0]),`
231			`.rRESULT (rRESULT[31:0]),`
232			`.rDWBSEL (rDWBSEL[3:0]),`
233			`.rMSR_IE (rMSR_IE),`
234	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
235	41	sybreon	`// Inputs`
236	44	sybreon	`.rXCE (rXCE[1:0]),`
237	41	sybreon	`.rREGA (rREGA[31:0]),`
238			`.rREGB (rREGB[31:0]),`
239			`.rMXSRC (rMXSRC[1:0]),`
240			`.rMXTGT (rMXTGT[1:0]),`
241			`.rRA (rRA[4:0]),`
242			`.rMXALU (rMXALU[2:0]),`
243			`.rBRA (rBRA),`
244			`.rDLY (rDLY),`
245	50	sybreon	`.rALT (rALT[10:0]),`
246	41	sybreon	`.rSIMM (rSIMM[31:0]),`
247			`.rIMM (rIMM[15:0]),`
248			`.rOPC (rOPC[5:0]),`
249			`.rRD (rRD[4:0]),`
250			`.rDWBDI (rDWBDI[31:0]),`
251			`.rPC (rPC[31:2]),`
252			`.gclk (gclk),`
253			`.grst (grst),`
254			`.gena (gena));`
255
256
257			`endmodule // aeMB_edk32`

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