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// $Id: aeMB_edk32.v,v 1.8 2007-11-14 22:14:34 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2007/11/10 16:39:38  sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.6  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.5  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.4  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.3  2007/11/03 08:34:55  sybreon
// Minor code cleanup.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_edk32 (/*AUTOARG*/
   // Outputs
   rFSLSTB, rDWBSTB, iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o,
   fsl_dat_o, fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
   dwb_adr_o,
   // Inputs
   sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
   dwb_ack_i, sys_clk_i, sys_rst_i
   );
   // Bus widths
   parameter IW = 32; /// Instruction bus address width
   parameter DW = 32; /// Data bus address width
 
   // Optional functions
   parameter MUL = 1; // Multiplier
   parameter BSF = 1; // Barrel Shifter
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
   output [14:2]        fsl_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] fsl_dat_o;              // From regf of aeMB_regf.v
   output               fsl_stb_o;              // From ctrl of aeMB_ctrl.v
   output               fsl_wre_o;              // From ctrl of aeMB_ctrl.v
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
   output               rDWBSTB;                // From ctrl of aeMB_ctrl.v
   output               rFSLSTB;                // From ctrl of aeMB_ctrl.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To ctrl of aeMB_ctrl.v
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
   input                fsl_ack_i;              // To ctrl of aeMB_ctrl.v
   input [31:0]          fsl_dat_i;              // To regf of aeMB_regf.v
   input                iwb_ack_i;              // To ibuf of aeMB_ibuf.v, ...
   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v
   input                sys_int_i;              // To ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
   wire [31:0]           xIREG;                  // From ibuf of aeMB_ibuf.v
   // End of automatics
 
   input                sys_clk_i;
   input                sys_rst_i;
 
   wire                 grst = sys_rst_i;
   wire                 gclk = sys_clk_i;
   wire                 gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
 
   aeMB_ibuf
     ibuf (/*AUTOINST*/
           // Outputs
           .rIMM                        (rIMM[15:0]),
           .rRA                         (rRA[4:0]),
           .rRD                         (rRD[4:0]),
           .rRB                         (rRB[4:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rSIMM                       (rSIMM[31:0]),
           .xIREG                       (xIREG[31:0]),
           .iwb_stb_o                   (iwb_stb_o),
           // Inputs
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .iwb_ack_i                   (iwb_ack_i),
           .sys_int_i                   (sys_int_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_ctrl
     ctrl (/*AUTOINST*/
           // Outputs
           .rMXDST                      (rMXDST[1:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALT                      (rMXALT[1:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rRW                         (rRW[4:0]),
           .rDWBSTB                     (rDWBSTB),
           .rFSLSTB                     (rFSLSTB),
           .dwb_stb_o                   (dwb_stb_o),
           .dwb_wre_o                   (dwb_wre_o),
           .fsl_stb_o                   (fsl_stb_o),
           .fsl_wre_o                   (fsl_wre_o),
           // Inputs
           .rDLY                        (rDLY),
           .rIMM                        (rIMM[15:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rPC                         (rPC[31:2]),
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .xIREG                       (xIREG[31:0]),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .fsl_ack_i                   (fsl_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_bpcu #(IW)
     bpcu (/*AUTOINST*/
           // Outputs
           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
           .rPC                         (rPC[31:2]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           // Inputs
           .rMXALT                      (rMXALT[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rREGA                       (rREGA[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_regf
     regf (/*AUTOINST*/
           // Outputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .dwb_dat_o                   (dwb_dat_o[31:0]),
           .fsl_dat_o                   (fsl_dat_o[31:0]),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rRW                         (rRW[4:0]),
           .rRD                         (rRD[4:0]),
           .rMXDST                      (rMXDST[1:0]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .fsl_dat_i                   (fsl_dat_i[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_xecu #(DW, MUL, BSF)
     xecu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .fsl_adr_o                   (fsl_adr_o[14:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           // Inputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rALT                        (rALT[10:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rPC                         (rPC[31:2]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
 
endmodule // aeMB_edk32

Line No.	Rev	Author	Line
1	61	sybreon	`// $Id: aeMB_edk32.v,v 1.8 2007-11-14 22:14:34 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	61	sybreon	`// Revision 1.7 2007/11/10 16:39:38 sybreon`
24			`// Upgraded license to LGPLv3.`
25			`// Significant performance optimisations.`
26			`//`
27	55	sybreon	`// Revision 1.6 2007/11/09 20:51:52 sybreon`
28			`// Added GET/PUT support through a FSL bus.`
29			`//`
30	53	sybreon	`// Revision 1.5 2007/11/08 17:48:14 sybreon`
31			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
32			`//`
33	51	sybreon	`// Revision 1.4 2007/11/08 14:17:47 sybreon`
34			`// Parameterised optional components.`
35			`//`
36	50	sybreon	`// Revision 1.3 2007/11/03 08:34:55 sybreon`
37			`// Minor code cleanup.`
38			`//`
39	45	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
40			`// Added better (beta) interrupt support.`
41			`// Changed MSR_IE to disabled at reset as per MB docs.`
42			`//`
43	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
44			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
45			`// Fixed various minor data hazard bugs.`
46			`// Code compatible with -O0/1/2/3/s generated code.`
47			`//`
48	41	sybreon
49			`module aeMB_edk32 (/AUTOARG/`
50			`// Outputs`
51	61	sybreon	`rFSLSTB, rDWBSTB, iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o,`
52			`fsl_dat_o, fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,`
53			`dwb_adr_o,`
54	41	sybreon	`// Inputs`
55	61	sybreon	`sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,`
56			`dwb_ack_i, sys_clk_i, sys_rst_i`
57	41	sybreon	`);`
58	50	sybreon	`// Bus widths`
59			`parameter IW = 32; /// Instruction bus address width`
60			`parameter DW = 32; /// Data bus address width`
61	41	sybreon
62	50	sybreon	`// Optional functions`
63			`parameter MUL = 1; // Multiplier`
64			`parameter BSF = 1; // Barrel Shifter`
65	41	sybreon
66			`/AUTOOUTPUT/`
67			`// Beginning of automatic outputs (from unused autoinst outputs)`
68			`output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v`
69			`output [31:0] dwb_dat_o; // From regf of aeMB_regf.v`
70			`output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v`
71			`output dwb_stb_o; // From ctrl of aeMB_ctrl.v`
72			`output dwb_wre_o; // From ctrl of aeMB_ctrl.v`
73	53	sybreon	`output [14:2] fsl_adr_o; // From xecu of aeMB_xecu.v`
74			`output [31:0] fsl_dat_o; // From regf of aeMB_regf.v`
75			`output fsl_stb_o; // From ctrl of aeMB_ctrl.v`
76			`output fsl_wre_o; // From ctrl of aeMB_ctrl.v`
77	41	sybreon	`output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v`
78			`output iwb_stb_o; // From ibuf of aeMB_ibuf.v`
79	61	sybreon	`output rDWBSTB; // From ctrl of aeMB_ctrl.v`
80			`output rFSLSTB; // From ctrl of aeMB_ctrl.v`
81	41	sybreon	`// End of automatics`
82			`/AUTOINPUT/`
83			`// Beginning of automatic inputs (from unused autoinst inputs)`
84	61	sybreon	`input dwb_ack_i; // To ctrl of aeMB_ctrl.v`
85	41	sybreon	`input [31:0] dwb_dat_i; // To regf of aeMB_regf.v`
86	61	sybreon	`input fsl_ack_i; // To ctrl of aeMB_ctrl.v`
87	53	sybreon	`input [31:0] fsl_dat_i; // To regf of aeMB_regf.v`
88	61	sybreon	`input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...`
89			`input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v`
90			`input sys_int_i; // To ibuf of aeMB_ibuf.v`
91	41	sybreon	`// End of automatics`
92			`/AUTOWIRE/`
93			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
94			`wire [10:0] rALT; // From ibuf of aeMB_ibuf.v`
95			`wire rBRA; // From bpcu of aeMB_bpcu.v`
96			`wire rDLY; // From bpcu of aeMB_bpcu.v`
97			`wire [31:0] rDWBDI; // From regf of aeMB_regf.v`
98			`wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v`
99			`wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v`
100	44	sybreon	`wire rMSR_BIP; // From xecu of aeMB_xecu.v`
101	41	sybreon	`wire rMSR_IE; // From xecu of aeMB_xecu.v`
102			`wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v`
103			`wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v`
104			`wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v`
105			`wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v`
106			`wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v`
107			`wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v`
108			`wire [31:2] rPC; // From bpcu of aeMB_bpcu.v`
109			`wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v`
110			`wire [4:0] rRA; // From ibuf of aeMB_ibuf.v`
111			`wire [4:0] rRB; // From ibuf of aeMB_ibuf.v`
112			`wire [4:0] rRD; // From ibuf of aeMB_ibuf.v`
113			`wire [31:0] rREGA; // From regf of aeMB_regf.v`
114			`wire [31:0] rREGB; // From regf of aeMB_regf.v`
115			`wire [31:0] rRESULT; // From xecu of aeMB_xecu.v`
116			`wire [4:0] rRW; // From ctrl of aeMB_ctrl.v`
117			`wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v`
118	61	sybreon	`wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v`
119	41	sybreon	`// End of automatics`
120	61	sybreon
121			`input sys_clk_i;`
122			`input sys_rst_i;`
123
124			`wire grst = sys_rst_i;`
125			`wire gclk = sys_clk_i;`
126			`wire gena = !((dwb_stb_o ^ dwb_ack_i) \| (fsl_stb_o ^ fsl_ack_i) \| !iwb_ack_i);`
127	50	sybreon
128	41	sybreon	`aeMB_ibuf`
129			`ibuf (/AUTOINST/`
130			`// Outputs`
131			`.rIMM (rIMM[15:0]),`
132			`.rRA (rRA[4:0]),`
133			`.rRD (rRD[4:0]),`
134			`.rRB (rRB[4:0]),`
135			`.rALT (rALT[10:0]),`
136			`.rOPC (rOPC[5:0]),`
137			`.rSIMM (rSIMM[31:0]),`
138	61	sybreon	`.xIREG (xIREG[31:0]),`
139	41	sybreon	`.iwb_stb_o (iwb_stb_o),`
140			`// Inputs`
141			`.rBRA (rBRA),`
142	61	sybreon	`.rMSR_IE (rMSR_IE),`
143			`.rMSR_BIP (rMSR_BIP),`
144	41	sybreon	`.iwb_dat_i (iwb_dat_i[31:0]),`
145			`.iwb_ack_i (iwb_ack_i),`
146	61	sybreon	`.sys_int_i (sys_int_i),`
147	41	sybreon	`.gclk (gclk),`
148			`.grst (grst),`
149			`.gena (gena));`
150
151			`aeMB_ctrl`
152			`ctrl (/AUTOINST/`
153			`// Outputs`
154			`.rMXDST (rMXDST[1:0]),`
155			`.rMXSRC (rMXSRC[1:0]),`
156			`.rMXTGT (rMXTGT[1:0]),`
157			`.rMXALT (rMXALT[1:0]),`
158			`.rMXALU (rMXALU[2:0]),`
159			`.rRW (rRW[4:0]),`
160			`.rDWBSTB (rDWBSTB),`
161	53	sybreon	`.rFSLSTB (rFSLSTB),`
162	41	sybreon	`.dwb_stb_o (dwb_stb_o),`
163			`.dwb_wre_o (dwb_wre_o),`
164	53	sybreon	`.fsl_stb_o (fsl_stb_o),`
165			`.fsl_wre_o (fsl_wre_o),`
166	41	sybreon	`// Inputs`
167			`.rDLY (rDLY),`
168			`.rIMM (rIMM[15:0]),`
169			`.rALT (rALT[10:0]),`
170			`.rOPC (rOPC[5:0]),`
171			`.rRD (rRD[4:0]),`
172			`.rRA (rRA[4:0]),`
173			`.rRB (rRB[4:0]),`
174			`.rPC (rPC[31:2]),`
175			`.rBRA (rBRA),`
176			`.rMSR_IE (rMSR_IE),`
177	61	sybreon	`.xIREG (xIREG[31:0]),`
178	50	sybreon	`.dwb_ack_i (dwb_ack_i),`
179	51	sybreon	`.iwb_ack_i (iwb_ack_i),`
180	53	sybreon	`.fsl_ack_i (fsl_ack_i),`
181	41	sybreon	`.gclk (gclk),`
182			`.grst (grst),`
183	44	sybreon	`.gena (gena));`
184	41	sybreon
185			`aeMB_bpcu #(IW)`
186			`bpcu (/AUTOINST/`
187			`// Outputs`
188			`.iwb_adr_o (iwb_adr_o[IW-1:2]),`
189			`.rPC (rPC[31:2]),`
190			`.rPCLNK (rPCLNK[31:2]),`
191			`.rBRA (rBRA),`
192			`.rDLY (rDLY),`
193			`// Inputs`
194			`.rMXALT (rMXALT[1:0]),`
195			`.rOPC (rOPC[5:0]),`
196			`.rRD (rRD[4:0]),`
197			`.rRA (rRA[4:0]),`
198			`.rRESULT (rRESULT[31:0]),`
199			`.rDWBDI (rDWBDI[31:0]),`
200			`.rREGA (rREGA[31:0]),`
201			`.gclk (gclk),`
202			`.grst (grst),`
203			`.gena (gena));`
204
205			`aeMB_regf`
206			`regf (/AUTOINST/`
207			`// Outputs`
208			`.rREGA (rREGA[31:0]),`
209			`.rREGB (rREGB[31:0]),`
210			`.rDWBDI (rDWBDI[31:0]),`
211			`.dwb_dat_o (dwb_dat_o[31:0]),`
212	53	sybreon	`.fsl_dat_o (fsl_dat_o[31:0]),`
213	41	sybreon	`// Inputs`
214			`.rOPC (rOPC[5:0]),`
215			`.rRA (rRA[4:0]),`
216			`.rRB (rRB[4:0]),`
217			`.rRW (rRW[4:0]),`
218			`.rRD (rRD[4:0]),`
219			`.rMXDST (rMXDST[1:0]),`
220			`.rPCLNK (rPCLNK[31:2]),`
221			`.rRESULT (rRESULT[31:0]),`
222			`.rDWBSEL (rDWBSEL[3:0]),`
223			`.rBRA (rBRA),`
224			`.rDLY (rDLY),`
225			`.dwb_dat_i (dwb_dat_i[31:0]),`
226	53	sybreon	`.fsl_dat_i (fsl_dat_i[31:0]),`
227	41	sybreon	`.gclk (gclk),`
228			`.grst (grst),`
229			`.gena (gena));`
230
231	50	sybreon	`aeMB_xecu #(DW, MUL, BSF)`
232			`xecu (/AUTOINST/`
233	41	sybreon	`// Outputs`
234			`.dwb_adr_o (dwb_adr_o[DW-1:2]),`
235			`.dwb_sel_o (dwb_sel_o[3:0]),`
236	53	sybreon	`.fsl_adr_o (fsl_adr_o[14:2]),`
237	41	sybreon	`.rRESULT (rRESULT[31:0]),`
238			`.rDWBSEL (rDWBSEL[3:0]),`
239			`.rMSR_IE (rMSR_IE),`
240	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
241	41	sybreon	`// Inputs`
242			`.rREGA (rREGA[31:0]),`
243			`.rREGB (rREGB[31:0]),`
244			`.rMXSRC (rMXSRC[1:0]),`
245			`.rMXTGT (rMXTGT[1:0]),`
246			`.rRA (rRA[4:0]),`
247	53	sybreon	`.rRB (rRB[4:0]),`
248	41	sybreon	`.rMXALU (rMXALU[2:0]),`
249			`.rBRA (rBRA),`
250			`.rDLY (rDLY),`
251	50	sybreon	`.rALT (rALT[10:0]),`
252	41	sybreon	`.rSIMM (rSIMM[31:0]),`
253			`.rIMM (rIMM[15:0]),`
254			`.rOPC (rOPC[5:0]),`
255			`.rRD (rRD[4:0]),`
256			`.rDWBDI (rDWBDI[31:0]),`
257			`.rPC (rPC[31:2]),`
258			`.gclk (gclk),`
259			`.grst (grst),`
260			`.gena (gena));`
261
262
263			`endmodule // aeMB_edk32`

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