OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [AEMB2_712/] [sim/] [verilog/] [edk32.v] - Blame information for rev 191

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 73 sybreon 
// $Id: edk32.v,v 1.10 2007-11-30 17:08:30 sybreon Exp $
2 41 sybreon 
//
3 
// AEMB EDK 3.2 Compatible Core TEST
4 
//
5 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
6 
//
7 59 sybreon 
// This file is part of AEMB.
8 41 sybreon 
//
9 59 sybreon 
// AEMB is free software: you can redistribute it and/or modify it
10 
// under the terms of the GNU Lesser General Public License as
11 
// published by the Free Software Foundation, either version 3 of the
12 
// License, or (at your option) any later version.
13 
//
14 
// AEMB is distributed in the hope that it will be useful, but WITHOUT
15 
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
17 
// Public License for more details.
18 
//
19 41 sybreon 
// You should have received a copy of the GNU Lesser General Public
20 59 sybreon 
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
21 41 sybreon 
//
22 
// $Log: not supported by cvs2svn $
23 73 sybreon 
// Revision 1.9  2007/11/20 18:36:00  sybreon
24 
// Removed unnecessary byte acrobatics with VMEM data.
25 
//
26 69 sybreon 
// Revision 1.8  2007/11/18 19:41:45  sybreon
27 
// Minor simulation fixes.
28 
//
29 67 sybreon 
// Revision 1.7  2007/11/14 22:11:41  sybreon
30 
// Added posedge/negedge bus interface.
31 
// Modified interrupt test system.
32 
//
33 59 sybreon 
// Revision 1.6  2007/11/13 23:37:28  sybreon
34 
// Updated simulation to also check BRI 0x00 instruction.
35 
//
36 58 sybreon 
// Revision 1.5  2007/11/09 20:51:53  sybreon
37 
// Added GET/PUT support through a FSL bus.
38 
//
39 53 sybreon 
// Revision 1.4  2007/11/08 14:18:00  sybreon
40 
// Parameterised optional components.
41 
//
42 50 sybreon 
// Revision 1.3  2007/11/05 10:59:31  sybreon
43 
// Added random seed for simulation.
44 
//
45 49 sybreon 
// Revision 1.2  2007/11/02 19:16:10  sybreon
46 
// Added interrupt simulation.
47 
// Changed "human readable" simulation output.
48 
//
49 43 sybreon 
// Revision 1.1  2007/11/02 03:25:45  sybreon
50 
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
51 
// Fixed various minor data hazard bugs.
52 
// Code compatible with -O0/1/2/3/s generated code.
53 
//
54 41 sybreon 
 
55 
module edk32 ();
56 49 sybreon 
 
57 
`include "random.v"
58 
 
59 41 sybreon 
   // INITIAL SETUP //////////////////////////////////////////////////////
60 
 
61 
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
62 
   reg       svc;
63 
   integer   inttime;
64 49 sybreon 
   integer   seed;
65 58 sybreon 
   integer   theend;
66 41 sybreon 
 
67 
   always #5 sys_clk_i = ~sys_clk_i;
68 
 
69 
   initial begin
70 69 sybreon 
      //$dumpfile("dump.vcd");
71 
      //$dumpvars(1,dut);
72 41 sybreon 
   end
73 
 
74 
   initial begin
75 58 sybreon 
      seed = randseed;
76 
      theend = 0;
77 41 sybreon 
      svc = 0;
78 49 sybreon 
      sys_clk_i = $random(seed);
79 41 sybreon 
      sys_rst_i = 1;
80 
      sys_int_i = 0;
81 
      sys_exc_i = 0;
82 59 sybreon 
      #50 sys_rst_i = 0;
83 41 sybreon 
   end
84 
 
85 
   initial fork
86 
      //inttime $display("FSADFASDFSDAF");
87 43 sybreon 
      //#10000 sys_int_i = 1;
88 41 sybreon 
      //#1100 sys_int_i = 0;
89 
      //#100000 $displayh("\nTest Completed.");
90 
      //#4000 $finish;
91 
   join
92 
 
93 
 
94 
   // FAKE MEMORY ////////////////////////////////////////////////////////
95 53 sybreon 
 
96 
   wire        fsl_stb_o;
97 
   wire        fsl_wre_o;
98 
   wire [31:0] fsl_dat_o;
99 
   wire [31:0] fsl_dat_i;
100 67 sybreon 
   wire [6:2]  fsl_adr_o;
101 41 sybreon 
 
102 
   wire [15:2] iwb_adr_o;
103 
   wire        iwb_stb_o;
104 
   wire        dwb_stb_o;
105 
   reg [31:0]  rom [0:65535];
106 
   wire [31:0] iwb_dat_i;
107 53 sybreon 
   reg         iwb_ack_i, dwb_ack_i, fsl_ack_i;
108 41 sybreon 
 
109 
   reg [31:0]  ram[0:65535];
110 
   wire [31:0] dwb_dat_i;
111 
   reg [31:0]  dwblat;
112 
   wire        dwb_we_o;
113 
   reg [15:2]  dadr,iadr;
114 
   wire [3:0]  dwb_sel_o;
115 
   wire [31:0] dwb_dat_o;
116 
   wire [15:2] dwb_adr_o;
117 59 sybreon 
   wire [31:0] dwb_dat_t;
118 
 
119 
   initial begin
120 
      dwb_ack_i = 0;
121 
      iwb_ack_i = 0;
122 
      fsl_ack_i = 0;
123 
   end
124 41 sybreon 
 
125 69 sybreon 
   assign      dwb_dat_t = ram[dwb_adr_o];
126 
   assign      iwb_dat_i = ram[iadr];
127 
   assign      dwb_dat_i = ram[dadr];
128 53 sybreon 
   assign      fsl_dat_i = fsl_adr_o;
129 59 sybreon 
 
130 
`ifdef POSEDGE
131 41 sybreon 
 
132 59 sybreon 
   always @(posedge sys_clk_i)
133 
     if (sys_rst_i) begin
134 
        /*AUTORESET*/
135 
        // Beginning of autoreset for uninitialized flops
136 
        dwb_ack_i <= 1'h0;
137 
        fsl_ack_i <= 1'h0;
138 
        iwb_ack_i <= 1'h0;
139 
        // End of automatics
140 
     end else begin
141 
        iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
142 
        dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
143 
        fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
144 73 sybreon 
     end // else: !if(sys_rst_i)
145 59 sybreon 
 
146 
   always @(posedge sys_clk_i) begin
147 
      iadr <= #1 iwb_adr_o;
148 
      dadr <= #1 dwb_adr_o;
149 
 
150 
      if (dwb_we_o & dwb_stb_o) begin
151 
         case (dwb_sel_o)
152 69 sybreon 
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
153 
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
154 
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
155 
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
156 
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
157 
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
158 
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
159 59 sybreon 
         endcase // case (dwb_sel_o)
160 
      end // if (dwb_we_o & dwb_stb_o)
161 73 sybreon 
   end // always @ (posedge sys_clk_i)
162 59 sybreon 
 
163 
`else // !`ifdef POSEDGE
164 
 
165 
   always @(negedge sys_clk_i)
166 
     if (sys_rst_i) begin
167 
        /*AUTORESET*/
168 
        // Beginning of autoreset for uninitialized flops
169 
        dwb_ack_i <= 1'h0;
170 
        fsl_ack_i <= 1'h0;
171 
        iwb_ack_i <= 1'h0;
172 
        // End of automatics
173 
     end else begin
174 
        iwb_ack_i <= #1 iwb_stb_o;
175 
        dwb_ack_i <= #1 dwb_stb_o;
176 
        fsl_ack_i <= #1 fsl_stb_o;
177 73 sybreon 
     end // else: !if(sys_rst_i)
178 59 sybreon 
 
179 41 sybreon 
   always @(negedge sys_clk_i) begin
180 59 sybreon 
      iadr <= #1 iwb_adr_o;
181 
      dadr <= #1 dwb_adr_o;
182 53 sybreon 
 
183 41 sybreon 
      if (dwb_we_o & dwb_stb_o) begin
184 
         case (dwb_sel_o)
185 69 sybreon 
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
186 
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
187 
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
188 
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
189 
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
190 
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
191 
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
192 43 sybreon 
         endcase // case (dwb_sel_o)
193 
      end // if (dwb_we_o & dwb_stb_o)
194 
   end // always @ (negedge sys_clk_i)
195 59 sybreon 
 
196 
`endif // !`ifdef POSEDGE
197 
 
198 41 sybreon 
 
199 
   integer i;
200 
   initial begin
201 
      for (i=0;i<65535;i=i+1) begin
202 
         ram[i] <= $random;
203 43 sybreon 
      end
204 69 sybreon 
      #1 $readmemh("dump.rom",ram);
205 41 sybreon 
   end
206 
 
207 
   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
208 
 
209 58 sybreon 
   integer rnd;
210 
 
211 41 sybreon 
   always @(posedge sys_clk_i) begin
212 43 sybreon 
 
213 
      // Interrupt Monitors
214 
      if (!dut.rMSR_IE) begin
215 
         rnd = $random % 30;
216 
         inttime = $stime + 1000 + (rnd*rnd * 10);
217 
      end
218 
      if ($stime > inttime) begin
219 
         sys_int_i = 1;
220 
         svc = 0;
221 
      end
222 
      if (($stime > inttime + 500) && !svc) begin
223 
         $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
224 
         $finish;
225 
      end
226 
      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
227 59 sybreon 
      if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
228 
         svc = 1;
229 
         //$display("\nLATENCY: ", ($stime - inttime)/10);
230 
      end
231 41 sybreon 
 
232 
      // Pass/Fail Monitors
233 
      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
234 
         $display("\n\tFAIL");
235 
         $finish;
236 43 sybreon 
      end
237 58 sybreon 
 
238 41 sybreon 
      if (iwb_dat_i == 32'hb8000000) begin
239 58 sybreon 
         theend = theend + 1;
240 
      end
241 
 
242 
      if (theend == 5) begin
243 41 sybreon 
         $display("\n\t*** PASSED ALL TESTS ***");
244 
         $finish;
245 
      end
246 
   end // always @ (posedge sys_clk_i)
247 
 
248 
   // INTERNAL WIRING ////////////////////////////////////////////////////
249 
 
250 
   aeMB_edk32 #(16,16)
251 
     dut (
252 
          .sys_int_i(sys_int_i),
253 
          .dwb_ack_i(dwb_ack_i),
254 
          .dwb_stb_o(dwb_stb_o),
255 
          .dwb_adr_o(dwb_adr_o),
256 
          .dwb_dat_o(dwb_dat_o),
257 
          .dwb_dat_i(dwb_dat_i),
258 
          .dwb_wre_o(dwb_we_o),
259 
          .dwb_sel_o(dwb_sel_o),
260 53 sybreon 
 
261 
          .fsl_ack_i(fsl_ack_i),
262 
          .fsl_stb_o(fsl_stb_o),
263 
          .fsl_adr_o(fsl_adr_o),
264 
          .fsl_dat_o(fsl_dat_o),
265 
          .fsl_dat_i(fsl_dat_i),
266 
          .fsl_wre_o(fsl_we_o),
267 
 
268 41 sybreon 
          .iwb_adr_o(iwb_adr_o),
269 
          .iwb_dat_i(iwb_dat_i),
270 
          .iwb_stb_o(iwb_stb_o),
271 
          .iwb_ack_i(iwb_ack_i),
272 
          .sys_clk_i(sys_clk_i),
273 
          .sys_rst_i(sys_rst_i)
274 
          );
275 
 
276 43 sybreon 
endmodule // edk32

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.