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/* $Id: aeMB2_aslu.v,v 1.9 2008-01-09 19:17:33 sybreon Exp $
**
** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aeMB2_aslu (/*AUTOARG*/
   // Outputs
   dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
   iwb_tga_o, dwb_tga_o, rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE,
   rMSR_BIP,
   // Inputs
   rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,
   rOPB_OF, pha_i, clk_i, rst_i, ena_i
   );
 
   parameter DWB = 32;
   parameter TXE = 1;
 
   parameter MUL = 0;
   parameter BSF = 1;
   parameter FSL = 1;
 
   // DWB
   output [DWB-1:2] dwb_adr_o;
   output [3:0]     dwb_sel_o;
   output [3:0]     rSEL_MA;
 
   // FSL
   output [6:2]     cwb_adr_o;
   output [1:0]     cwb_tga_o;
   output [3:0]     cwb_sel_o;
 
   // CACHE ENABLE
   output           iwb_tga_o,
                    dwb_tga_o;
 
   // PIPELINE
   output [31:0]    rMUL_MA;
   output [31:0]    rRES_MA,
                    rRES_EX;
 
   output           rMSR_IE,
                    rMSR_BE,
                    //rMSR_TXE,
                    //rMSR_DCE,
                    //rMSR_ICE,             
                    rMSR_BIP;
 
   input [15:0]     rIMM_OF;
   input [2:0]       rALU_OF;
   input [5:0]       rOPC_OF,
                    rOPC_IF;
 
   input [4:0]       rRA_OF,
                    rRD_OF;
 
   input [31:0]     rOPA_OF, // RA, PC
                    rOPB_OF; // RB, IMM
 
   // SYSTEM
   input            pha_i,
                    clk_i,
                    rst_i,
                    ena_i;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [6:2]            cwb_adr_o;
   reg [3:0]             cwb_sel_o;
   reg [1:0]             cwb_tga_o;
   reg [DWB-1:2]        dwb_adr_o;
   reg [3:0]             dwb_sel_o;
   reg                  dwb_tga_o;
   reg                  iwb_tga_o;
   reg                  rMSR_BE;
   reg                  rMSR_BIP;
   reg                  rMSR_IE;
   reg [31:0]            rMUL_MA;
   reg [31:0]            rRES_EX;
   reg [31:0]            rRES_MA;
   reg [3:0]             rSEL_MA;
   // End of automatics
 
   reg                  rMSR_C0,
                        rMSR_C1,
                        rMSR_C,
                        rMSR_CC,
                        rMSR_CL[0:1];
 
 
   wire [4:0]            rRD = rRD_OF;
   wire [31:0]           rOPA = rOPA_OF;
   wire [31:0]           rOPB = rOPB_OF;
   wire [5:0]            rOPC = rOPC_OF;
   wire [4:0]            rRA = rRA_OF;
   wire [15:0]           rIMM = rIMM_OF;
   wire [10:0]           rALT = rIMM_OF[10:0];
 
   /*
    MSR REGISTER
 
    We should keep common configuration bits in the lower 16-bits of
    the MSR in order to avoid using the IMMI instruction.
 
    MSR bits
    31 - CC (carry copy)
 
    10 - HTE (hardware thread enabled)
     9 - PHA (current phase)
     8 - TXE (enable threads)
 
     7 - DCE (data cache enable)
     5 - ICE (instruction cache enable)
     4 - FSL (FSL available)
 
     3 - BIP (break in progress)
     2 - C (carry flag)
     1 - IE (interrupt enable)
 
 
    */
 
   wire [31:0]           wMSR = {rMSR_C, // MSR_CC
 
                                20'd0, // Reserved
 
                                TXE[0], // (PVR)
                                pha_i, // (EIP)
                                TXE[0], // (EE)
 
                                dwb_tga_o, // MSR_DCE
                                1'b0, // reserved for DZ
                                iwb_tga_o, // MSR_ICE
                                FSL[0], // GET/PUT available
 
                                rMSR_BIP, // MSR_BIP
                                rMSR_C, // MSR_C
                                rMSR_IE, // MSR_IE
                                rMSR_BE}; // MSR_BE
 
 
   /*
    C SELECTOR
 
    Preselects the C to speed things up.  */
 
   // TODO: Optimise
 
   wire                 wMSR_CX, wMSR_C;
   assign               wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;
 
   assign               wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
                                 (rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
                                 (rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
   /*
   assign               wMSR_C = ((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o1)) ? 1'b1 : // RSUB = 1
                                 ((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o0)) ? 1'b0 : // ADD = 0
                                 wMSR_CX;
   */
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMSR_C <= 1'h0;
        rMSR_CC <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
        rMSR_C <= #1 wMSR_CX;
        rMSR_CC <= #1 wMSR_C;
     end
 
   /*
    ADD/SUB SELECTOR
 
    Current implementation is a clutz. It needs to be
    re-implemented. It is also in the critical path.  */
 
   // FIXME: Redesign
   // TODO: Verify signed compare   
 
   wire                 wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
   wire [31:0]           wADD, wSUB, wRES_A, wCMP, wOPX;
 
   wire                 wCMPU = (rOPA > rOPB);
   wire                 wCMPF = (rIMM[1]) ? wCMPU :
                        ((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
 
   assign               {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
   assign               wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
   //assign             wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
   assign               wOPC = rMSR_CC;
 
   assign               {wSUBC,wSUB} = {wADDC,wADD};
   assign               {wADDC,wADD} = (rOPB + wOPX) + wOPC;
 
   reg                  rRES_ADDC;
   reg [31:0]            rRES_ADD;
   always @(rIMM or rOPC or wADD or wADDC or wCMP
            or wCMPC or wSUB or wSUBC)
     case ({rOPC[3],rOPC[0],rIMM[0]})
       4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {wSUBC,wSUB}; // SUB
       4'h3: {rRES_ADDC,rRES_ADD} <= #1 {wCMPC,wCMP}; // CMP
       default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
     endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
 
   /*
    LOGIC
 
    This can be combined with the shifter below.
    */
 
   reg [31:0]            rRES_LOG;
   always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
     case (rOPC[2:0])
       2'o0: rRES_LOG <= #1 rOPA | rOPB;
       2'o1: rRES_LOG <= #1 rOPA & rOPB;
       2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
       2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
     endcase // case (rOPC[2:0])
 
   /*
    SIMPLE SHIFTER
 
    Implemented as wiring and registers.
    */
 
   reg [31:0]            rRES_SFT;
   reg                  rRES_SFTC;
 
   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
     case (rIMM[6:5])
       2'o0: rRES_SFT <= {rOPA[31],rOPA[31:1]}; // SRA
       2'o1: rRES_SFT <= {rMSR_C,rOPA[31:1]}; // SRC
       2'o2: rRES_SFT <= {1'b0,rOPA[31:1]}; // SRL
       2'o3: rRES_SFT <= (rIMM[0]) ?
                         {{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
                         {{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
     endcase // case (rIMM[6:5])
 
   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
     rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];
 
   /*
    MOVER
    */
 
   wire                 fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
   wire                 fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
   reg [31:0]            rRES_MOV;
 
   always @(/*AUTOSENSE*/fMFSR or rOPA or rOPB or rRA or wMSR)
     case ({fMFSR, rRA[3]})
       2'o0: rRES_MOV <= rOPA; // MFS rpc
       2'o1: rRES_MOV <= rOPB; // BRA       
       2'o2: rRES_MOV <= wMSR; // MFS rmsr
       default: rRES_MOV <= 32'hX;
     endcase // case ({fMFSR, rRA[3]})
 
 
   /*
    COMBINED SHIFT/LOGIC/MOVE
 
    */
 
   reg [31:0]            rRES_SLM;
 
   always @(/*AUTOSENSE*/fMFSR or rIMM or rMSR_C or rOPA or rOPB
            or rOPC or rRA or wMSR)
     case (rOPC[2:0])
       3'o0: rRES_SLM <= #1 rOPA | rOPB;
       3'o1: rRES_SLM <= #1 rOPA & rOPB;
       3'o2: rRES_SLM <= #1 rOPA ^ rOPB;
       3'o3: rRES_SLM <= #1 rOPA & ~rOPB;
       3'o4: case (rIMM[6:5])
               2'o0: rRES_SLM <= #1 {rOPA[31],rOPA[31:1]}; // SRA
               2'o1: rRES_SLM <= #1 {rMSR_C,rOPA[31:1]}; // SRC
               2'o2: rRES_SLM <= #1 {1'b0,rOPA[31:1]}; // SRL
               2'o3: rRES_SLM <= #1 (rIMM[0]) ?
                                 {{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
                                 {{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
             endcase // case (rIMM[6:5])
       3'o5: case ({fMFSR, rRA[3]})
               2'o0: rRES_SLM <= #1 rOPA; // MFS rpc
               2'o1: rRES_SLM <= #1 rOPB; // BRA       
               2'o2: rRES_SLM <= #1 wMSR; // MFS rmsr
               default: rRES_MOV <= #1 32'hX;
             endcase // case ({fMFSR, rRA[3]})
       3'o6: rRES_SLM <= #1 rOPB;
       default: rRES_SLM <= #1 32'hX;
     endcase // case (rOPC[2:0])
 
 
   /*
    MULTIPLIER
 
    Implemented as a 2-stage multiplier in order to increase clock
    speed. */
 
   reg [31:0]        rRES_MUL;
   always @(posedge clk_i) if (ena_i) begin
      rMUL_MA <= #1 rRES_MUL;
      rRES_MUL <= #1 (rOPA * rOPB);
   end
 
   /*
    BARREL SHIFTER
 
    This can be potentially made 2-stage if it is a
    bottleneck. Doesn't seem necessary at the moment as the critical
    path runs through the adder. */
 
   reg [31:0]     rRES_BSF;
   reg [31:0]     xBSRL, xBSRA, xBSLL;
 
   /* logical left barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     xBSLL <= rOPA << rOPB[4:0];
 
   /* logical right barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     xBSRL <= rOPA >> rOPB[4:0];
 
   /* arithmetic right barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     case (rOPB[4:0])
       5'd00: xBSRA <= rOPA;
       5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
       5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
       5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
       5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
       5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
       5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
       5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
       5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
       5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
       5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
       5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
       5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
       5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
       5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
       5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
       5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
       5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
       5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
       5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
       5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
       5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
       5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
       5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
       5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
       5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
       5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
       5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
       5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
       5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
       5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
       5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
     endcase // case (rOPB[4:0])
 
   /* select the shift result (2nd stage) */
   always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
     case (rALT[10:9])
       2'd0: rRES_BSF <= xBSRL;
       2'd1: rRES_BSF <= xBSRA;
       2'd2: rRES_BSF <= xBSLL;
       default: rRES_BSF <= 32'hX;
     endcase // case (rALT[10:9])
 
 
   /*
    RESULTS
    */
 
   // RESULT   
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rRES_EX <= 32'h0;
        rRES_MA <= 32'h0;
        // End of automatics
     end else if (ena_i) begin
        rRES_MA <= #1 rRES_EX;
        /*
        case (rALU_OF)
          3'o0: rRES_EX <= #1 rRES_ADD;
          3'o1: rRES_EX <= #1 rRES_LOG;
          3'o2: rRES_EX <= #1 rRES_SFT;
          3'o3: rRES_EX <= #1 rRES_MOV;
          3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
          default: rRES_EX <= #1 32'hX;
        endcase // case (rALU_OF)
         */
        case (rALU_OF[1:0])
        //case (rOPC[5:4])
          2'o0: rRES_EX <= #1 rRES_ADD;
          2'o2: rRES_EX <= #1 rRES_SLM;
          2'o1: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
          default: rRES_EX <= #1 32'hX;
        endcase // case (rALU_OF[1:0])
 
     end // if (ena_i)
 
 
   /*
    MSR REGISTER
 
    Move data to the MSR or change due to break/returns. */
 
   reg           xMSR_C;
 
   // C
   wire          fMTS = (rOPC == 6'o45) & rIMM[14];
   wire          fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
 
   always @(/*AUTOSENSE*/fADDC or rALU_OF or rIMM or rMSR_C or rOPC
            or rRES_ADDC or rRES_SFTC)
     case (rALU_OF[1:0])
     //case (rOPC[5:4])
       3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
       3'o2: case (rOPC[2:0])
               3'o5: xMSR_C <= (rIMM[14]) ? rOPA[2] : rMSR_C; // MTS
               3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX
               default: xMSR_C <= rMSR_C;
             endcase // case (rOPC[2:0])
       default: xMSR_C <= rMSR_C;
     endcase // case (rOPC[5:4])
 
     /*
     case (rALU_OF)
       3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
       3'o1: xMSR_C <= rMSR_C; // LOGIC
       3'o2: xMSR_C <= rRES_SFTC; // SHIFT
       3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
       3'o4: xMSR_C <= rMSR_C;
       3'o5: xMSR_C <= rMSR_C;
       default: xMSR_C <= 1'hX;
     endcase // case (rALU_OF)
      */
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMSR_C0 <= 1'h0;
        rMSR_C1 <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
        if (pha_i)
          rMSR_C1 <= #1 xMSR_C;
        else
          rMSR_C0 <= #1 xMSR_C;
     end
 
   // IE/BIP/BE
   wire             fRTID = (rOPC == 6'o55) & rRD[0];
   wire             fRTBD = (rOPC == 6'o55) & rRD[1];
   wire             fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
   wire             fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_tga_o <= 1'h0;
        iwb_tga_o <= 1'h0;
        rMSR_BE <= 1'h0;
        rMSR_BIP <= 1'h0;
        rMSR_IE <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
 
        // Interrupt enable (compatible)
        rMSR_IE <= #1
                   (fINT) ? 1'b0 :
                   (fRTID) ? 1'b1 :
                   (fMTS) ? rOPA[1] :
                   rMSR_IE;
 
        // Break in progress (compatible)
        rMSR_BIP <= #1
                    (fBRK) ? 1'b1 :
                    (fRTBD) ? 1'b0 :
                    (fMTS) ? rOPA[3] :
                    rMSR_BIP;
 
        // Forcibly assert dwb_cyc_o signal     
        rMSR_BE <= #1
                   (fMTS) ? rOPA[0] : rMSR_BE;
 
        // Enable the thread extension
        //rMSR_TXE <= #1 TXE[0];        
 
        // Enable the caches
        dwb_tga_o <= #1 (fMTS) ?
                     rOPA[7] :
                     dwb_tga_o;
        iwb_tga_o <= #1 (fMTS) ?
                     rOPA[5] :
                     iwb_tga_o;
 
     end // if (ena_i)
 
   /*
    DATA/FSL WISHBONE
 
    Asserts the data address as calculated by the adder and the
    appropriate byte select lanes depending on the byte offset of the
    address. It does not check for mis-aligned addresses.  */
 
   // TODO: Check for mis-alignment
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        cwb_adr_o <= 5'h0;
        cwb_sel_o <= 4'h0;
        cwb_tga_o <= 2'h0;
        dwb_adr_o <= {(1+(DWB-1)-(2)){1'b0}};
        dwb_sel_o <= 4'h0;
        rSEL_MA <= 4'h0;
        // End of automatics
     end else if (ena_i) begin // if (rst_i)
        rSEL_MA <= #1 dwb_sel_o;
 
        dwb_adr_o <= #1 wADD[DWB-1:2];
        case (rOPC[1:0])
          2'o0: case (wADD[1:0]) // 8'bit
                  2'o0: dwb_sel_o <= #1 4'h8;
                  2'o1: dwb_sel_o <= #1 4'h4;
                  2'o2: dwb_sel_o <= #1 4'h2;
                  2'o3: dwb_sel_o <= #1 4'h1;
                endcase // case (wADD[1:0])
          2'o1: dwb_sel_o <= #1 (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
          2'o2: dwb_sel_o <= #1 4'hF; // 32'bit
          2'o3: dwb_sel_o <= #1 4'h0; // FSL
        endcase // case (rOPC[1:0])
 
        {cwb_adr_o, cwb_tga_o} <= #1 {rIMM_OF[4:0], rIMM_OF[15:14]};
        cwb_sel_o <= #1 {(4){ &rOPC[1:0]}};
 
     end // if (ena_i)
 
endmodule // aeMB2_aslu
 
/* $Log: not supported by cvs2svn $
/* Revision 1.8  2008/01/09 19:12:59  sybreon
/* multiplier issues
/*
/* Revision 1.7  2007/12/17 12:53:27  sybreon
/* Fixed Carry bit bug.
/*
/* Revision 1.6  2007/12/16 20:38:06  sybreon
/* Minor optimisations.
/*
/* Revision 1.5  2007/12/16 03:25:37  sybreon
/* Some optimisations.
/*
/* Revision 1.4  2007/12/13 21:25:41  sybreon
/* Further optimisations (speed + size).
/*
/* Revision 1.3  2007/12/13 20:12:11  sybreon
/* Code cleanup + minor speed regression.
/*
/* Revision 1.2  2007/12/12 19:16:59  sybreon
/* Minor optimisations (~10% faster)
/*
/* Revision 1.1  2007/12/11 00:43:17  sybreon
/* initial import
/* */

Line No.	Rev	Author	Line
1	101	sybreon	`/* $Id: aeMB2_aslu.v,v 1.9 2008-01-09 19:17:33 sybreon Exp $`
2	78	sybreon	`**`
3			`** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT`
4			`**`
5			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`**`
7			`** This file is part of AEMB.`
8			`**`
9			`** AEMB is free software: you can redistribute it and/or modify it`
10			`** under the terms of the GNU Lesser General Public License as`
11			`** published by the Free Software Foundation, either version 3 of the`
12			`** License, or (at your option) any later version.`
13			`**`
14			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21			`*/`
22
23			`module aeMB2_aslu (/AUTOARG/`
24			`// Outputs`
25			`dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,`
26	81	sybreon	`iwb_tga_o, dwb_tga_o, rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE,`
27			`rMSR_BIP,`
28	78	sybreon	`// Inputs`
29	80	sybreon	`rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,`
30	78	sybreon	`rOPB_OF, pha_i, clk_i, rst_i, ena_i`
31			`);`
32
33			`parameter DWB = 32;`
34	80	sybreon	`parameter TXE = 1;`
35	78	sybreon
36			`parameter MUL = 0;`
37			`parameter BSF = 1;`
38			`parameter FSL = 1;`
39
40			`// DWB`
41			`output [DWB-1:2] dwb_adr_o;`
42			`output [3:0] dwb_sel_o;`
43	81	sybreon	`output [3:0] rSEL_MA;`
44
45	78	sybreon	`// FSL`
46			`output [6:2] cwb_adr_o;`
47			`output [1:0] cwb_tga_o;`
48			`output [3:0] cwb_sel_o;`
49
50	81	sybreon	`// CACHE ENABLE`
51			`output iwb_tga_o,`
52			`dwb_tga_o;`
53
54	78	sybreon	`// PIPELINE`
55			`output [31:0] rMUL_MA;`
56			`output [31:0] rRES_MA,`
57			`rRES_EX;`
58	81	sybreon
59	78	sybreon	`output rMSR_IE,`
60			`rMSR_BE,`
61	81	sybreon	`//rMSR_TXE,`
62			`//rMSR_DCE,`
63			`//rMSR_ICE,`
64	78	sybreon	`rMSR_BIP;`
65
66			`input [15:0] rIMM_OF;`
67			`input [2:0] rALU_OF;`
68	80	sybreon	`input [5:0] rOPC_OF,`
69			`rOPC_IF;`
70
71	78	sybreon	`input [4:0] rRA_OF,`
72			`rRD_OF;`
73	80	sybreon
74	78	sybreon	`input [31:0] rOPA_OF, // RA, PC`
75			`rOPB_OF; // RB, IMM`
76
77			`// SYSTEM`
78			`input pha_i,`
79			`clk_i,`
80			`rst_i,`
81			`ena_i;`
82
83			`/AUTOREG/`
84			`// Beginning of automatic regs (for this module's undeclared outputs)`
85			`reg [6:2] cwb_adr_o;`
86			`reg [3:0] cwb_sel_o;`
87			`reg [1:0] cwb_tga_o;`
88			`reg [DWB-1:2] dwb_adr_o;`
89			`reg [3:0] dwb_sel_o;`
90	81	sybreon	`reg dwb_tga_o;`
91			`reg iwb_tga_o;`
92	78	sybreon	`reg rMSR_BE;`
93			`reg rMSR_BIP;`
94			`reg rMSR_IE;`
95			`reg [31:0] rMUL_MA;`
96			`reg [31:0] rRES_EX;`
97			`reg [31:0] rRES_MA;`
98			`reg [3:0] rSEL_MA;`
99			`// End of automatics`
100
101			`reg rMSR_C0,`
102			`rMSR_C1,`
103	81	sybreon	`rMSR_C,`
104	90	sybreon	`rMSR_CC,`
105	80	sybreon	`rMSR_CL[0:1];`
106	78	sybreon
107
108	80	sybreon	`wire [4:0] rRD = rRD_OF;`
109			`wire [31:0] rOPA = rOPA_OF;`
110			`wire [31:0] rOPB = rOPB_OF;`
111			`wire [5:0] rOPC = rOPC_OF;`
112			`wire [4:0] rRA = rRA_OF;`
113			`wire [15:0] rIMM = rIMM_OF;`
114			`wire [10:0] rALT = rIMM_OF[10:0];`
115
116			`/*`
117	81	sybreon	`MSR REGISTER`
118
119			`We should keep common configuration bits in the lower 16-bits of`
120			`the MSR in order to avoid using the IMMI instruction.`
121
122			`MSR bits`
123			`31 - CC (carry copy)`
124
125			`10 - HTE (hardware thread enabled)`
126			`9 - PHA (current phase)`
127			`8 - TXE (enable threads)`
128
129			`7 - DCE (data cache enable)`
130			`5 - ICE (instruction cache enable)`
131			`4 - FSL (FSL available)`
132
133			`3 - BIP (break in progress)`
134			`2 - C (carry flag)`
135			`1 - IE (interrupt enable)`
136
137
138			`*/`
139
140			`wire [31:0] wMSR = {rMSR_C, // MSR_CC`
141
142			`20'd0, // Reserved`
143
144			`TXE[0], // (PVR)`
145			`pha_i, // (EIP)`
146			`TXE[0], // (EE)`
147
148			`dwb_tga_o, // MSR_DCE`
149			`1'b0, // reserved for DZ`
150			`iwb_tga_o, // MSR_ICE`
151			`FSL[0], // GET/PUT available`
152
153			`rMSR_BIP, // MSR_BIP`
154			`rMSR_C, // MSR_C`
155			`rMSR_IE, // MSR_IE`
156			`rMSR_BE}; // MSR_BE`
157
158
159			`/*`
160	80	sybreon	`C SELECTOR`
161
162	81	sybreon	`Preselects the C to speed things up. */`
163	80	sybreon
164			`// TODO: Optimise`
165	78	sybreon
166	80	sybreon	`wire wMSR_CX, wMSR_C;`
167	90	sybreon	`assign wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;`
168
169	80	sybreon	`assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX \| // SRX`
170			`(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX \| // ADDC/RSUBC`
171			`(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB`
172	90	sybreon	`/*`
173			`assign wMSR_C = ((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o1)) ? 1'b1 : // RSUB = 1`
174			`((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o0)) ? 1'b0 : // ADD = 0`
175			`wMSR_CX;`
176			`*/`
177
178	80	sybreon	`always @(posedge clk_i)`
179			`if (rst_i) begin`
180			`/AUTORESET/`
181			`// Beginning of autoreset for uninitialized flops`
182			`rMSR_C <= 1'h0;`
183	90	sybreon	`rMSR_CC <= 1'h0;`
184	80	sybreon	`// End of automatics`
185			`end else if (ena_i) begin`
186	90	sybreon	`rMSR_C <= #1 wMSR_CX;`
187			`rMSR_CC <= #1 wMSR_C;`
188	80	sybreon	`end`
189
190			`/*`
191			`ADD/SUB SELECTOR`
192
193			`Current implementation is a clutz. It needs to be`
194			`re-implemented. It is also in the critical path. */`
195
196	78	sybreon	`// FIXME: Redesign`
197	80	sybreon	`// TODO: Verify signed compare`
198
199			`wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;`
200			`wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;`
201	78	sybreon
202	80	sybreon	`wire wCMPU = (rOPA > rOPB);`
203			`wire wCMPF = (rIMM[1]) ? wCMPU :`
204			`((wCMPU & ~(rOPB[31] ^ rOPA[31])) \| (rOPB[31] & ~rOPA[31]));`
205	78	sybreon
206	80	sybreon	`assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};`
207			`assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;`
208	90	sybreon	`//assign wOPC = ((rMSR_C & rOPC[1]) \| (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);`
209			`assign wOPC = rMSR_CC;`
210	78	sybreon
211	80	sybreon	`assign {wSUBC,wSUB} = {wADDC,wADD};`
212			`assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;`
213	78	sybreon
214	80	sybreon	`reg rRES_ADDC;`
215			`reg [31:0] rRES_ADD;`
216	78	sybreon	`always @(rIMM or rOPC or wADD or wADDC or wCMP`
217			`or wCMPC or wSUB or wSUBC)`
218			`case ({rOPC[3],rOPC[0],rIMM[0]})`
219	90	sybreon	`4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {wSUBC,wSUB}; // SUB`
220			`4'h3: {rRES_ADDC,rRES_ADD} <= #1 {wCMPC,wCMP}; // CMP`
221	78	sybreon	`default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};`
222			`endcase // case ({rOPC[3],rOPC[0],rIMM[0]})`
223
224	80	sybreon	`/*`
225			`LOGIC`
226
227			`This can be combined with the shifter below.`
228			`*/`
229	78	sybreon
230	80	sybreon	`reg [31:0] rRES_LOG;`
231	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB or rOPC)`
232	80	sybreon	`case (rOPC[2:0])`
233	78	sybreon	`2'o0: rRES_LOG <= #1 rOPA \| rOPB;`
234			`2'o1: rRES_LOG <= #1 rOPA & rOPB;`
235			`2'o2: rRES_LOG <= #1 rOPA ^ rOPB;`
236	80	sybreon	`2'o3: rRES_LOG <= #1 rOPA & ~rOPB;`
237			`endcase // case (rOPC[2:0])`
238	78	sybreon
239	80	sybreon	`/*`
240			`SIMPLE SHIFTER`
241
242			`Implemented as wiring and registers.`
243			`*/`
244	78	sybreon
245	80	sybreon	`reg [31:0] rRES_SFT;`
246			`reg rRES_SFTC;`
247	78	sybreon
248			`always @(/AUTOSENSE/rIMM or rMSR_C or rOPA)`
249			`case (rIMM[6:5])`
250	80	sybreon	`2'o0: rRES_SFT <= {rOPA[31],rOPA[31:1]}; // SRA`
251			`2'o1: rRES_SFT <= {rMSR_C,rOPA[31:1]}; // SRC`
252			`2'o2: rRES_SFT <= {1'b0,rOPA[31:1]}; // SRL`
253			`2'o3: rRES_SFT <= (rIMM[0]) ?`
254			`{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16`
255			`{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8`
256	78	sybreon	`endcase // case (rIMM[6:5])`
257
258	80	sybreon	`always @(/AUTOSENSE/rIMM or rMSR_C or rOPA)`
259			`rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];`
260	81	sybreon
261	80	sybreon	`/*`
262	81	sybreon	`MOVER`
263	80	sybreon	`*/`
264	78	sybreon
265	80	sybreon	`wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];`
266			`wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];`
267			`reg [31:0] rRES_MOV;`
268	81	sybreon
269	80	sybreon	`always @(/AUTOSENSE/fMFSR or rOPA or rOPB or rRA or wMSR)`
270	81	sybreon	`case ({fMFSR, rRA[3]})`
271			`2'o0: rRES_MOV <= rOPA; // MFS rpc`
272			`2'o1: rRES_MOV <= rOPB; // BRA`
273			`2'o2: rRES_MOV <= wMSR; // MFS rmsr`
274			`default: rRES_MOV <= 32'hX;`
275			`endcase // case ({fMFSR, rRA[3]})`
276	82	sybreon
277
278			`/*`
279			`COMBINED SHIFT/LOGIC/MOVE`
280
281			`*/`
282	78	sybreon
283	82	sybreon	`reg [31:0] rRES_SLM;`
284
285			`always @(/AUTOSENSE/fMFSR or rIMM or rMSR_C or rOPA or rOPB`
286			`or rOPC or rRA or wMSR)`
287			`case (rOPC[2:0])`
288			`3'o0: rRES_SLM <= #1 rOPA \| rOPB;`
289			`3'o1: rRES_SLM <= #1 rOPA & rOPB;`
290			`3'o2: rRES_SLM <= #1 rOPA ^ rOPB;`
291			`3'o3: rRES_SLM <= #1 rOPA & ~rOPB;`
292			`3'o4: case (rIMM[6:5])`
293	86	sybreon	`2'o0: rRES_SLM <= #1 {rOPA[31],rOPA[31:1]}; // SRA`
294			`2'o1: rRES_SLM <= #1 {rMSR_C,rOPA[31:1]}; // SRC`
295			`2'o2: rRES_SLM <= #1 {1'b0,rOPA[31:1]}; // SRL`
296			`2'o3: rRES_SLM <= #1 (rIMM[0]) ?`
297	82	sybreon	`{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16`
298			`{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8`
299			`endcase // case (rIMM[6:5])`
300			`3'o5: case ({fMFSR, rRA[3]})`
301	86	sybreon	`2'o0: rRES_SLM <= #1 rOPA; // MFS rpc`
302			`2'o1: rRES_SLM <= #1 rOPB; // BRA`
303			`2'o2: rRES_SLM <= #1 wMSR; // MFS rmsr`
304			`default: rRES_MOV <= #1 32'hX;`
305	82	sybreon	`endcase // case ({fMFSR, rRA[3]})`
306	86	sybreon	`3'o6: rRES_SLM <= #1 rOPB;`
307			`default: rRES_SLM <= #1 32'hX;`
308	82	sybreon	`endcase // case (rOPC[2:0])`
309
310
311	80	sybreon	`/*`
312			`MULTIPLIER`
313
314			`Implemented as a 2-stage multiplier in order to increase clock`
315			`speed. */`
316	78	sybreon
317			`reg [31:0] rRES_MUL;`
318	101	sybreon	`always @(posedge clk_i) if (ena_i) begin`
319			`rMUL_MA <= #1 rRES_MUL;`
320			`rRES_MUL <= #1 (rOPA * rOPB);`
321			`end`
322	100	sybreon
323	80	sybreon	`/*`
324			`BARREL SHIFTER`
325
326	81	sybreon	`This can be potentially made 2-stage if it is a`
327			`bottleneck. Doesn't seem necessary at the moment as the critical`
328			`path runs through the adder. */`
329	78	sybreon
330			`reg [31:0] rRES_BSF;`
331			`reg [31:0] xBSRL, xBSRA, xBSLL;`
332
333	80	sybreon	`/* logical left barrel shifter */`
334	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
335			`xBSLL <= rOPA << rOPB[4:0];`
336
337	80	sybreon	`/* logical right barrel shifter */`
338	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
339			`xBSRL <= rOPA >> rOPB[4:0];`
340
341	80	sybreon	`/* arithmetic right barrel shifter */`
342	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
343			`case (rOPB[4:0])`
344			`5'd00: xBSRA <= rOPA;`
345			`5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};`
346			`5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};`
347			`5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};`
348			`5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};`
349			`5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};`
350			`5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};`
351			`5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};`
352			`5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};`
353			`5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};`
354			`5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};`
355			`5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};`
356			`5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};`
357			`5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};`
358			`5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};`
359			`5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};`
360			`5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};`
361			`5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};`
362			`5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};`
363			`5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};`
364			`5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};`
365			`5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};`
366			`5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};`
367			`5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};`
368			`5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};`
369			`5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};`
370			`5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};`
371			`5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};`
372			`5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};`
373			`5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};`
374			`5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};`
375			`5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};`
376			`endcase // case (rOPB[4:0])`
377
378	80	sybreon	`/* select the shift result (2nd stage) */`
379	78	sybreon	`always @(/AUTOSENSE/rALT or xBSLL or xBSRA or xBSRL)`
380			`case (rALT[10:9])`
381			`2'd0: rRES_BSF <= xBSRL;`
382			`2'd1: rRES_BSF <= xBSRA;`
383			`2'd2: rRES_BSF <= xBSLL;`
384			`default: rRES_BSF <= 32'hX;`
385			`endcase // case (rALT[10:9])`
386	82	sybreon
387
388			`/*`
389			`RESULTS`
390			`*/`
391	81	sybreon
392	82	sybreon	`// RESULT`
393			`always @(posedge clk_i)`
394			`if (rst_i) begin`
395			`/AUTORESET/`
396			`// Beginning of autoreset for uninitialized flops`
397			`rRES_EX <= 32'h0;`
398			`rRES_MA <= 32'h0;`
399			`// End of automatics`
400			`end else if (ena_i) begin`
401			`rRES_MA <= #1 rRES_EX;`
402			`/*`
403			`case (rALU_OF)`
404			`3'o0: rRES_EX <= #1 rRES_ADD;`
405			`3'o1: rRES_EX <= #1 rRES_LOG;`
406			`3'o2: rRES_EX <= #1 rRES_SFT;`
407			`3'o3: rRES_EX <= #1 rRES_MOV;`
408			`3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;`
409			`default: rRES_EX <= #1 32'hX;`
410			`endcase // case (rALU_OF)`
411			`*/`
412			`case (rALU_OF[1:0])`
413	86	sybreon	`//case (rOPC[5:4])`
414	82	sybreon	`2'o0: rRES_EX <= #1 rRES_ADD;`
415	86	sybreon	`2'o2: rRES_EX <= #1 rRES_SLM;`
416			`2'o1: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;`
417	82	sybreon	`default: rRES_EX <= #1 32'hX;`
418			`endcase // case (rALU_OF[1:0])`
419
420			`end // if (ena_i)`
421
422
423	80	sybreon	`/*`
424			`MSR REGISTER`
425
426			`Move data to the MSR or change due to break/returns. */`
427
428	78	sybreon	`reg xMSR_C;`
429
430			`// C`
431	80	sybreon	`wire fMTS = (rOPC == 6'o45) & rIMM[14];`
432			`wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);`
433	78	sybreon
434	88	sybreon	`always @(/AUTOSENSE/fADDC or rALU_OF or rIMM or rMSR_C or rOPC`
435			`or rRES_ADDC or rRES_SFTC)`
436			`case (rALU_OF[1:0])`
437			`//case (rOPC[5:4])`
438	82	sybreon	`3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB`
439	86	sybreon	`3'o2: case (rOPC[2:0])`
440	90	sybreon	`3'o5: xMSR_C <= (rIMM[14]) ? rOPA[2] : rMSR_C; // MTS`
441	82	sybreon	`3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX`
442			`default: xMSR_C <= rMSR_C;`
443			`endcase // case (rOPC[2:0])`
444			`default: xMSR_C <= rMSR_C;`
445	86	sybreon	`endcase // case (rOPC[5:4])`
446	82	sybreon
447			`/*`
448	78	sybreon	`case (rALU_OF)`
449			`3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;`
450			`3'o1: xMSR_C <= rMSR_C; // LOGIC`
451			`3'o2: xMSR_C <= rRES_SFTC; // SHIFT`
452			`3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;`
453			`3'o4: xMSR_C <= rMSR_C;`
454			`3'o5: xMSR_C <= rMSR_C;`
455			`default: xMSR_C <= 1'hX;`
456	80	sybreon	`endcase // case (rALU_OF)`
457	82	sybreon	`*/`
458
459	78	sybreon	`always @(posedge clk_i)`
460			`if (rst_i) begin`
461			`/AUTORESET/`
462			`// Beginning of autoreset for uninitialized flops`
463			`rMSR_C0 <= 1'h0;`
464			`rMSR_C1 <= 1'h0;`
465			`// End of automatics`
466	81	sybreon	`end else if (ena_i) begin`
467			`if (pha_i)`
468	78	sybreon	`rMSR_C1 <= #1 xMSR_C;`
469	81	sybreon	`else`
470	78	sybreon	`rMSR_C0 <= #1 xMSR_C;`
471	86	sybreon	`end`
472	78	sybreon
473			`// IE/BIP/BE`
474			`wire fRTID = (rOPC == 6'o55) & rRD[0];`
475			`wire fRTBD = (rOPC == 6'o55) & rRD[1];`
476			`wire fBRK = ((rOPC == 6'o56) \| (rOPC == 6'o66)) & (rRA == 5'hC);`
477			`wire fINT = ((rOPC == 6'o56) \| (rOPC == 6'o66)) & (rRA == 5'hE);`
478	81	sybreon
479	78	sybreon	`always @(posedge clk_i)`
480			`if (rst_i) begin`
481			`/AUTORESET/`
482			`// Beginning of autoreset for uninitialized flops`
483	81	sybreon	`dwb_tga_o <= 1'h0;`
484			`iwb_tga_o <= 1'h0;`
485	78	sybreon	`rMSR_BE <= 1'h0;`
486			`rMSR_BIP <= 1'h0;`
487			`rMSR_IE <= 1'h0;`
488			`// End of automatics`
489			`end else if (ena_i) begin`
490
491	80	sybreon	`// Interrupt enable (compatible)`
492	78	sybreon	`rMSR_IE <= #1`
493			`(fINT) ? 1'b0 :`
494			`(fRTID) ? 1'b1 :`
495			`(fMTS) ? rOPA[1] :`
496			`rMSR_IE;`
497	80	sybreon
498			`// Break in progress (compatible)`
499	78	sybreon	`rMSR_BIP <= #1`
500			`(fBRK) ? 1'b1 :`

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