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/* $Id: aeMB2_aslu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $
**
** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aeMB2_aslu (/*AUTOARG*/
   // Outputs
   dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
   iwb_tga_o, dwb_tga_o, rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE,
   rMSR_BIP,
   // Inputs
   rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,
   rOPB_OF, pha_i, clk_i, rst_i, ena_i
   );
 
   parameter DWB = 32;
   parameter TXE = 1;
 
   parameter MUL = 0;
   parameter BSF = 1;
   parameter FSL = 1;
 
   // DWB
   output [DWB-1:2] dwb_adr_o;
   output [3:0]     dwb_sel_o;
   output [3:0]     rSEL_MA;
 
   // FSL
   output [6:2]     cwb_adr_o;
   output [1:0]     cwb_tga_o;
   output [3:0]     cwb_sel_o;
 
   // CACHE ENABLE
   output           iwb_tga_o,
                    dwb_tga_o;
 
   // PIPELINE
   output [31:0]    rMUL_MA;
   output [31:0]    rRES_MA,
                    rRES_EX;
 
   output           rMSR_IE,
                    rMSR_BE,
                    //rMSR_TXE,
                    //rMSR_DCE,
                    //rMSR_ICE,             
                    rMSR_BIP;
 
   input [15:0]     rIMM_OF;
   input [2:0]       rALU_OF;
   input [5:0]       rOPC_OF,
                    rOPC_IF;
 
   input [4:0]       rRA_OF,
                    rRD_OF;
 
   input [31:0]     rOPA_OF, // RA, PC
                    rOPB_OF; // RB, IMM
 
   // SYSTEM
   input            pha_i,
                    clk_i,
                    rst_i,
                    ena_i;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [6:2]            cwb_adr_o;
   reg [3:0]             cwb_sel_o;
   reg [1:0]             cwb_tga_o;
   reg [DWB-1:2]        dwb_adr_o;
   reg [3:0]             dwb_sel_o;
   reg                  dwb_tga_o;
   reg                  iwb_tga_o;
   reg                  rMSR_BE;
   reg                  rMSR_BIP;
   reg                  rMSR_IE;
   reg [31:0]            rMUL_MA;
   reg [31:0]            rRES_EX;
   reg [31:0]            rRES_MA;
   reg [3:0]             rSEL_MA;
   // End of automatics
 
   reg                  rMSR_C0,
                        rMSR_C1,
                        rMSR_C,
                        rMSR_CL[0:1];
 
 
   wire [4:0]            rRD = rRD_OF;
   wire [31:0]           rOPA = rOPA_OF;
   wire [31:0]           rOPB = rOPB_OF;
   wire [5:0]            rOPC = rOPC_OF;
   wire [4:0]            rRA = rRA_OF;
   wire [15:0]           rIMM = rIMM_OF;
   wire [10:0]           rALT = rIMM_OF[10:0];
 
   /*
    MSR REGISTER
 
    We should keep common configuration bits in the lower 16-bits of
    the MSR in order to avoid using the IMMI instruction.
 
    MSR bits
    31 - CC (carry copy)
 
    10 - HTE (hardware thread enabled)
     9 - PHA (current phase)
     8 - TXE (enable threads)
 
     7 - DCE (data cache enable)
     5 - ICE (instruction cache enable)
     4 - FSL (FSL available)
 
     3 - BIP (break in progress)
     2 - C (carry flag)
     1 - IE (interrupt enable)
 
 
    */
 
   wire [31:0]           wMSR = {rMSR_C, // MSR_CC
 
                                20'd0, // Reserved
 
                                TXE[0], // (PVR)
                                pha_i, // (EIP)
                                TXE[0], // (EE)
 
                                dwb_tga_o, // MSR_DCE
                                1'b0, // reserved for DZ
                                iwb_tga_o, // MSR_ICE
                                FSL[0], // GET/PUT available
 
                                rMSR_BIP, // MSR_BIP
                                rMSR_C, // MSR_C
                                rMSR_IE, // MSR_IE
                                rMSR_BE}; // MSR_BE
 
 
   /*
    C SELECTOR
 
    Preselects the C to speed things up.  */
 
   // TODO: Optimise
 
   wire                 wMSR_CX, wMSR_C;
   assign               wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;
   assign               wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
                                 (rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
                                 (rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMSR_C <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
        rMSR_C <= #1 wMSR_C;
     end
 
   /*
    ADD/SUB SELECTOR
 
    Current implementation is a clutz. It needs to be
    re-implemented. It is also in the critical path.  */
 
   // FIXME: Redesign
   // TODO: Verify signed compare   
 
   wire                 wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
   wire [31:0]           wADD, wSUB, wRES_A, wCMP, wOPX;
 
   wire                 wCMPU = (rOPA > rOPB);
   wire                 wCMPF = (rIMM[1]) ? wCMPU :
                        ((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
 
   assign               {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
   assign               wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
   //assign             wOPC = ((wMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
   assign               wOPC = rMSR_C;
 
   assign               {wSUBC,wSUB} = {wADDC,wADD};
   assign               {wADDC,wADD} = (rOPB + wOPX) + wOPC;
 
   reg                  rRES_ADDC;
   reg [31:0]            rRES_ADD;
   always @(rIMM or rOPC or wADD or wADDC or wCMP
            or wCMPC or wSUB or wSUBC)
     case ({rOPC[3],rOPC[0],rIMM[0]})
       4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
       4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
       default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
     endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
 
   /*
    LOGIC
 
    This can be combined with the shifter below.
    */
 
   reg [31:0]            rRES_LOG;
   always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
     case (rOPC[2:0])
       2'o0: rRES_LOG <= #1 rOPA | rOPB;
       2'o1: rRES_LOG <= #1 rOPA & rOPB;
       2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
       2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
     endcase // case (rOPC[2:0])
 
   /*
    SIMPLE SHIFTER
 
    Implemented as wiring and registers.
    */
 
   reg [31:0]            rRES_SFT;
   reg                  rRES_SFTC;
 
   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
     case (rIMM[6:5])
       2'o0: rRES_SFT <= {rOPA[31],rOPA[31:1]}; // SRA
       2'o1: rRES_SFT <= {rMSR_C,rOPA[31:1]}; // SRC
       2'o2: rRES_SFT <= {1'b0,rOPA[31:1]}; // SRL
       2'o3: rRES_SFT <= (rIMM[0]) ?
                         {{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
                         {{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
     endcase // case (rIMM[6:5])
 
   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
     rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];
 
   /*
    MOVER
    */
 
   wire                 fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
   wire                 fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
   reg [31:0]            rRES_MOV;
 
   always @(/*AUTOSENSE*/fMFSR or rOPA or rOPB or rRA or wMSR)
     case ({fMFSR, rRA[3]})
       2'o0: rRES_MOV <= rOPA; // MFS rpc
       2'o1: rRES_MOV <= rOPB; // BRA       
       2'o2: rRES_MOV <= wMSR; // MFS rmsr
       default: rRES_MOV <= 32'hX;
     endcase // case ({fMFSR, rRA[3]})
   //rRES_MOV <= (fMFSR) ? wMSR : //(fMFPC) ? rOPA : (rRA[3]) ? rOPB :  rOPA;   
 
   /*
    MULTIPLIER
 
    Implemented as a 2-stage multiplier in order to increase clock
    speed. */
 
   reg [31:0]        rRES_MUL;
   always @(posedge clk_i) begin
      rMUL_MA <= #1 rRES_MUL;
      rRES_MUL <= #1 (rOPA * rOPB);
   end
 
   /*
    BARREL SHIFTER
 
    This can be potentially made 2-stage if it is a
    bottleneck. Doesn't seem necessary at the moment as the critical
    path runs through the adder. */
 
   reg [31:0]     rRES_BSF;
   reg [31:0]     xBSRL, xBSRA, xBSLL;
 
   /* logical left barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     xBSLL <= rOPA << rOPB[4:0];
 
   /* logical right barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     xBSRL <= rOPA >> rOPB[4:0];
 
   /* arithmetic right barrel shifter */
   always @(/*AUTOSENSE*/rOPA or rOPB)
     case (rOPB[4:0])
       5'd00: xBSRA <= rOPA;
       5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
       5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
       5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
       5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
       5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
       5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
       5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
       5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
       5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
       5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
       5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
       5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
       5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
       5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
       5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
       5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
       5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
       5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
       5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
       5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
       5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
       5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
       5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
       5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
       5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
       5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
       5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
       5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
       5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
       5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
       5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
     endcase // case (rOPB[4:0])
 
   /* select the shift result (2nd stage) */
   always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
     case (rALT[10:9])
       2'd0: rRES_BSF <= xBSRL;
       2'd1: rRES_BSF <= xBSRA;
       2'd2: rRES_BSF <= xBSLL;
       default: rRES_BSF <= 32'hX;
     endcase // case (rALT[10:9])
 
   /*
    MSR REGISTER
 
    Move data to the MSR or change due to break/returns. */
 
   reg           xMSR_C;
 
   // C
   wire          fMTS = (rOPC == 6'o45) & rIMM[14];
   wire          fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
 
   always @(/*AUTOSENSE*/fADDC or fMTS or rALU_OF or rMSR_C or rOPA
            or rRES_ADDC or rRES_SFTC)
     case (rALU_OF)
       3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
       3'o1: xMSR_C <= rMSR_C; // LOGIC       
       3'o2: xMSR_C <= rRES_SFTC; // SHIFT
       3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
       3'o4: xMSR_C <= rMSR_C;
       3'o5: xMSR_C <= rMSR_C;
       default: xMSR_C <= 1'hX;
     endcase // case (rALU_OF)
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMSR_C0 <= 1'h0;
        rMSR_C1 <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
        if (pha_i)
          rMSR_C1 <= #1 xMSR_C;
        else
          rMSR_C0 <= #1 xMSR_C;
     end // else: !if(rst_i)
 
   // IE/BIP/BE
   wire             fRTID = (rOPC == 6'o55) & rRD[0];
   wire             fRTBD = (rOPC == 6'o55) & rRD[1];
   wire             fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
   wire             fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_tga_o <= 1'h0;
        iwb_tga_o <= 1'h0;
        rMSR_BE <= 1'h0;
        rMSR_BIP <= 1'h0;
        rMSR_IE <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
 
        // Interrupt enable (compatible)
        rMSR_IE <= #1
                   (fINT) ? 1'b0 :
                   (fRTID) ? 1'b1 :
                   (fMTS) ? rOPA[1] :
                   rMSR_IE;
 
        // Break in progress (compatible)
        rMSR_BIP <= #1
                    (fBRK) ? 1'b1 :
                    (fRTBD) ? 1'b0 :
                    (fMTS) ? rOPA[3] :
                    rMSR_BIP;
 
        // Forcibly assert dwb_cyc_o signal     
        rMSR_BE <= #1
                   (fMTS) ? rOPA[0] : rMSR_BE;
 
        // Enable the thread extension
        //rMSR_TXE <= #1 TXE[0];        
 
        // Enable the caches
        dwb_tga_o <= #1 (fMTS) ?
                     rOPA[7] :
                     dwb_tga_o;
        iwb_tga_o <= #1 (fMTS) ?
                     rOPA[5] :
                     iwb_tga_o;
 
     end // if (ena_i)
 
   /*
    RESULTS
    */
 
   // RESULT   
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rRES_EX <= 32'h0;
        rRES_MA <= 32'h0;
        // End of automatics
     end else if (ena_i) begin
        rRES_MA <= #1 rRES_EX;
        case (rALU_OF)
          3'o0: rRES_EX <= #1 rRES_ADD;
          3'o1: rRES_EX <= #1 rRES_LOG;
          3'o2: rRES_EX <= #1 rRES_SFT;
          3'o3: rRES_EX <= #1 rRES_MOV;
          //3'o4: rRES_EX <= (MUL) ? rRES_MUL : 32'hX;   
          3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
          default: rRES_EX <= #1 32'hX;
        endcase // case (rALU_OF)
     end // if (ena_i)
 
   /*
    DATA/FSL WISHBONE
 
    Asserts the data address as calculated by the adder and the
    appropriate byte select lanes depending on the byte offset of the
    address. It does not check for mis-aligned addresses.  */
 
   // TODO: Check for mis-alignment
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        cwb_adr_o <= 5'h0;
        cwb_sel_o <= 4'h0;
        cwb_tga_o <= 2'h0;
        dwb_adr_o <= {(1+(DWB-1)-(2)){1'b0}};
        dwb_sel_o <= 4'h0;
        rSEL_MA <= 4'h0;
        // End of automatics
     end else if (ena_i) begin // if (rst_i)
        rSEL_MA <= #1 dwb_sel_o;
 
        dwb_adr_o <= #1 wADD[DWB-1:2];
        case (rOPC[1:0])
          2'o0: case (wADD[1:0]) // 8'bit
                  2'o0: dwb_sel_o <= #1 4'h8;
                  2'o1: dwb_sel_o <= #1 4'h4;
                  2'o2: dwb_sel_o <= #1 4'h2;
                  2'o3: dwb_sel_o <= #1 4'h1;
                endcase // case (wADD[1:0])
          2'o1: dwb_sel_o <= #1 (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
          2'o2: dwb_sel_o <= #1 4'hF; // 32'bit
          2'o3: dwb_sel_o <= #1 4'h0; // FSL
        endcase // case (rOPC[1:0])
 
        {cwb_adr_o, cwb_tga_o} <= #1 {rIMM_OF[4:0], rIMM_OF[15:14]};
        cwb_sel_o <= #1 {(4){ &rOPC[1:0]}};
 
     end // if (ena_i)
 
endmodule // aeMB2_aslu
 
/* $Log: not supported by cvs2svn $
/* Revision 1.2  2007/12/12 19:16:59  sybreon
/* Minor optimisations (~10% faster)
/*
/* Revision 1.1  2007/12/11 00:43:17  sybreon
/* initial import
/* */

Line No.	Rev	Author	Line
1	81	sybreon	`/* $Id: aeMB2_aslu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $`
2	78	sybreon	`**`
3			`** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT`
4			`**`
5			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`**`
7			`** This file is part of AEMB.`
8			`**`
9			`** AEMB is free software: you can redistribute it and/or modify it`
10			`** under the terms of the GNU Lesser General Public License as`
11			`** published by the Free Software Foundation, either version 3 of the`
12			`** License, or (at your option) any later version.`
13			`**`
14			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21			`*/`
22
23			`module aeMB2_aslu (/AUTOARG/`
24			`// Outputs`
25			`dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,`
26	81	sybreon	`iwb_tga_o, dwb_tga_o, rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE,`
27			`rMSR_BIP,`
28	78	sybreon	`// Inputs`
29	80	sybreon	`rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,`
30	78	sybreon	`rOPB_OF, pha_i, clk_i, rst_i, ena_i`
31			`);`
32
33			`parameter DWB = 32;`
34	80	sybreon	`parameter TXE = 1;`
35	78	sybreon
36			`parameter MUL = 0;`
37			`parameter BSF = 1;`
38			`parameter FSL = 1;`
39
40			`// DWB`
41			`output [DWB-1:2] dwb_adr_o;`
42			`output [3:0] dwb_sel_o;`
43	81	sybreon	`output [3:0] rSEL_MA;`
44
45	78	sybreon	`// FSL`
46			`output [6:2] cwb_adr_o;`
47			`output [1:0] cwb_tga_o;`
48			`output [3:0] cwb_sel_o;`
49
50	81	sybreon	`// CACHE ENABLE`
51			`output iwb_tga_o,`
52			`dwb_tga_o;`
53
54	78	sybreon	`// PIPELINE`
55			`output [31:0] rMUL_MA;`
56			`output [31:0] rRES_MA,`
57			`rRES_EX;`
58	81	sybreon
59	78	sybreon	`output rMSR_IE,`
60			`rMSR_BE,`
61	81	sybreon	`//rMSR_TXE,`
62			`//rMSR_DCE,`
63			`//rMSR_ICE,`
64	78	sybreon	`rMSR_BIP;`
65
66			`input [15:0] rIMM_OF;`
67			`input [2:0] rALU_OF;`
68	80	sybreon	`input [5:0] rOPC_OF,`
69			`rOPC_IF;`
70
71	78	sybreon	`input [4:0] rRA_OF,`
72			`rRD_OF;`
73	80	sybreon
74	78	sybreon	`input [31:0] rOPA_OF, // RA, PC`
75			`rOPB_OF; // RB, IMM`
76
77			`// SYSTEM`
78			`input pha_i,`
79			`clk_i,`
80			`rst_i,`
81			`ena_i;`
82
83			`/AUTOREG/`
84			`// Beginning of automatic regs (for this module's undeclared outputs)`
85			`reg [6:2] cwb_adr_o;`
86			`reg [3:0] cwb_sel_o;`
87			`reg [1:0] cwb_tga_o;`
88			`reg [DWB-1:2] dwb_adr_o;`
89			`reg [3:0] dwb_sel_o;`
90	81	sybreon	`reg dwb_tga_o;`
91			`reg iwb_tga_o;`
92	78	sybreon	`reg rMSR_BE;`
93			`reg rMSR_BIP;`
94			`reg rMSR_IE;`
95			`reg [31:0] rMUL_MA;`
96			`reg [31:0] rRES_EX;`
97			`reg [31:0] rRES_MA;`
98			`reg [3:0] rSEL_MA;`
99			`// End of automatics`
100
101			`reg rMSR_C0,`
102			`rMSR_C1,`
103	81	sybreon	`rMSR_C,`
104	80	sybreon	`rMSR_CL[0:1];`
105	78	sybreon
106
107	80	sybreon	`wire [4:0] rRD = rRD_OF;`
108			`wire [31:0] rOPA = rOPA_OF;`
109			`wire [31:0] rOPB = rOPB_OF;`
110			`wire [5:0] rOPC = rOPC_OF;`
111			`wire [4:0] rRA = rRA_OF;`
112			`wire [15:0] rIMM = rIMM_OF;`
113			`wire [10:0] rALT = rIMM_OF[10:0];`
114
115			`/*`
116	81	sybreon	`MSR REGISTER`
117
118			`We should keep common configuration bits in the lower 16-bits of`
119			`the MSR in order to avoid using the IMMI instruction.`
120
121			`MSR bits`
122			`31 - CC (carry copy)`
123
124			`10 - HTE (hardware thread enabled)`
125			`9 - PHA (current phase)`
126			`8 - TXE (enable threads)`
127
128			`7 - DCE (data cache enable)`
129			`5 - ICE (instruction cache enable)`
130			`4 - FSL (FSL available)`
131
132			`3 - BIP (break in progress)`
133			`2 - C (carry flag)`
134			`1 - IE (interrupt enable)`
135
136
137			`*/`
138
139			`wire [31:0] wMSR = {rMSR_C, // MSR_CC`
140
141			`20'd0, // Reserved`
142
143			`TXE[0], // (PVR)`
144			`pha_i, // (EIP)`
145			`TXE[0], // (EE)`
146
147			`dwb_tga_o, // MSR_DCE`
148			`1'b0, // reserved for DZ`
149			`iwb_tga_o, // MSR_ICE`
150			`FSL[0], // GET/PUT available`
151
152			`rMSR_BIP, // MSR_BIP`
153			`rMSR_C, // MSR_C`
154			`rMSR_IE, // MSR_IE`
155			`rMSR_BE}; // MSR_BE`
156
157
158			`/*`
159	80	sybreon	`C SELECTOR`
160
161	81	sybreon	`Preselects the C to speed things up. */`
162	80	sybreon
163			`// TODO: Optimise`
164	78	sybreon
165	80	sybreon	`wire wMSR_CX, wMSR_C;`
166	81	sybreon	`assign wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;`
167	80	sybreon	`assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX \| // SRX`
168			`(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX \| // ADDC/RSUBC`
169			`(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB`
170	81	sybreon
171	80	sybreon	`always @(posedge clk_i)`
172			`if (rst_i) begin`
173			`/AUTORESET/`
174			`// Beginning of autoreset for uninitialized flops`
175			`rMSR_C <= 1'h0;`
176			`// End of automatics`
177			`end else if (ena_i) begin`
178			`rMSR_C <= #1 wMSR_C;`
179			`end`
180
181			`/*`
182			`ADD/SUB SELECTOR`
183
184			`Current implementation is a clutz. It needs to be`
185			`re-implemented. It is also in the critical path. */`
186
187	78	sybreon	`// FIXME: Redesign`
188	80	sybreon	`// TODO: Verify signed compare`
189
190			`wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;`
191			`wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;`
192	78	sybreon
193	80	sybreon	`wire wCMPU = (rOPA > rOPB);`
194			`wire wCMPF = (rIMM[1]) ? wCMPU :`
195			`((wCMPU & ~(rOPB[31] ^ rOPA[31])) \| (rOPB[31] & ~rOPA[31]));`
196	78	sybreon
197	80	sybreon	`assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};`
198			`assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;`
199			`//assign wOPC = ((wMSR_C & rOPC[1]) \| (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);`
200			`assign wOPC = rMSR_C;`
201	78	sybreon
202	80	sybreon	`assign {wSUBC,wSUB} = {wADDC,wADD};`
203			`assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;`
204	78	sybreon
205	80	sybreon	`reg rRES_ADDC;`
206			`reg [31:0] rRES_ADD;`
207	78	sybreon	`always @(rIMM or rOPC or wADD or wADDC or wCMP`
208			`or wCMPC or wSUB or wSUBC)`
209			`case ({rOPC[3],rOPC[0],rIMM[0]})`
210			`4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB`
211			`4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP`
212			`default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};`
213			`endcase // case ({rOPC[3],rOPC[0],rIMM[0]})`
214
215	80	sybreon	`/*`
216			`LOGIC`
217
218			`This can be combined with the shifter below.`
219			`*/`
220	78	sybreon
221	80	sybreon	`reg [31:0] rRES_LOG;`
222	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB or rOPC)`
223	80	sybreon	`case (rOPC[2:0])`
224	78	sybreon	`2'o0: rRES_LOG <= #1 rOPA \| rOPB;`
225			`2'o1: rRES_LOG <= #1 rOPA & rOPB;`
226			`2'o2: rRES_LOG <= #1 rOPA ^ rOPB;`
227	80	sybreon	`2'o3: rRES_LOG <= #1 rOPA & ~rOPB;`
228			`endcase // case (rOPC[2:0])`
229	78	sybreon
230	80	sybreon	`/*`
231			`SIMPLE SHIFTER`
232
233			`Implemented as wiring and registers.`
234			`*/`
235	78	sybreon
236	80	sybreon	`reg [31:0] rRES_SFT;`
237			`reg rRES_SFTC;`
238	78	sybreon
239			`always @(/AUTOSENSE/rIMM or rMSR_C or rOPA)`
240			`case (rIMM[6:5])`
241	80	sybreon	`2'o0: rRES_SFT <= {rOPA[31],rOPA[31:1]}; // SRA`
242			`2'o1: rRES_SFT <= {rMSR_C,rOPA[31:1]}; // SRC`
243			`2'o2: rRES_SFT <= {1'b0,rOPA[31:1]}; // SRL`
244			`2'o3: rRES_SFT <= (rIMM[0]) ?`
245			`{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16`
246			`{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8`
247	78	sybreon	`endcase // case (rIMM[6:5])`
248
249	80	sybreon	`always @(/AUTOSENSE/rIMM or rMSR_C or rOPA)`
250			`rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];`
251	81	sybreon
252	80	sybreon	`/*`
253	81	sybreon	`MOVER`
254	80	sybreon	`*/`
255	78	sybreon
256	80	sybreon	`wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];`
257			`wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];`
258			`reg [31:0] rRES_MOV;`
259	81	sybreon
260	80	sybreon	`always @(/AUTOSENSE/fMFSR or rOPA or rOPB or rRA or wMSR)`
261	81	sybreon	`case ({fMFSR, rRA[3]})`
262			`2'o0: rRES_MOV <= rOPA; // MFS rpc`
263			`2'o1: rRES_MOV <= rOPB; // BRA`
264			`2'o2: rRES_MOV <= wMSR; // MFS rmsr`
265			`default: rRES_MOV <= 32'hX;`
266			`endcase // case ({fMFSR, rRA[3]})`
267			`//rRES_MOV <= (fMFSR) ? wMSR : //(fMFPC) ? rOPA : (rRA[3]) ? rOPB : rOPA;`
268	78	sybreon
269	80	sybreon	`/*`
270			`MULTIPLIER`
271
272			`Implemented as a 2-stage multiplier in order to increase clock`
273			`speed. */`
274	78	sybreon
275			`reg [31:0] rRES_MUL;`
276			`always @(posedge clk_i) begin`
277	81	sybreon	`rMUL_MA <= #1 rRES_MUL;`
278			`rRES_MUL <= #1 (rOPA * rOPB);`
279	78	sybreon	`end`
280
281	80	sybreon	`/*`
282			`BARREL SHIFTER`
283
284	81	sybreon	`This can be potentially made 2-stage if it is a`
285			`bottleneck. Doesn't seem necessary at the moment as the critical`
286			`path runs through the adder. */`
287	78	sybreon
288			`reg [31:0] rRES_BSF;`
289			`reg [31:0] xBSRL, xBSRA, xBSLL;`
290
291	80	sybreon	`/* logical left barrel shifter */`
292	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
293			`xBSLL <= rOPA << rOPB[4:0];`
294
295	80	sybreon	`/* logical right barrel shifter */`
296	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
297			`xBSRL <= rOPA >> rOPB[4:0];`
298
299	80	sybreon	`/* arithmetic right barrel shifter */`
300	78	sybreon	`always @(/AUTOSENSE/rOPA or rOPB)`
301			`case (rOPB[4:0])`
302			`5'd00: xBSRA <= rOPA;`
303			`5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};`
304			`5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};`
305			`5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};`
306			`5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};`
307			`5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};`
308			`5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};`
309			`5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};`
310			`5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};`
311			`5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};`
312			`5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};`
313			`5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};`
314			`5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};`
315			`5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};`
316			`5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};`
317			`5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};`
318			`5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};`
319			`5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};`
320			`5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};`
321			`5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};`
322			`5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};`
323			`5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};`
324			`5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};`
325			`5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};`
326			`5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};`
327			`5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};`
328			`5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};`
329			`5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};`
330			`5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};`
331			`5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};`
332			`5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};`
333			`5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};`
334			`endcase // case (rOPB[4:0])`
335
336	80	sybreon	`/* select the shift result (2nd stage) */`
337	78	sybreon	`always @(/AUTOSENSE/rALT or xBSLL or xBSRA or xBSRL)`
338			`case (rALT[10:9])`
339			`2'd0: rRES_BSF <= xBSRL;`
340			`2'd1: rRES_BSF <= xBSRA;`
341			`2'd2: rRES_BSF <= xBSLL;`
342			`default: rRES_BSF <= 32'hX;`
343			`endcase // case (rALT[10:9])`
344	81	sybreon
345	80	sybreon	`/*`
346			`MSR REGISTER`
347
348			`Move data to the MSR or change due to break/returns. */`
349
350	78	sybreon	`reg xMSR_C;`
351
352			`// C`
353	80	sybreon	`wire fMTS = (rOPC == 6'o45) & rIMM[14];`
354			`wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);`
355	78	sybreon
356			`always @(/AUTOSENSE/fADDC or fMTS or rALU_OF or rMSR_C or rOPA`
357			`or rRES_ADDC or rRES_SFTC)`
358			`case (rALU_OF)`
359			`3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;`
360			`3'o1: xMSR_C <= rMSR_C; // LOGIC`
361			`3'o2: xMSR_C <= rRES_SFTC; // SHIFT`
362			`3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;`
363			`3'o4: xMSR_C <= rMSR_C;`
364			`3'o5: xMSR_C <= rMSR_C;`
365			`default: xMSR_C <= 1'hX;`
366	80	sybreon	`endcase // case (rALU_OF)`
367	78	sybreon
368			`always @(posedge clk_i)`
369			`if (rst_i) begin`
370			`/AUTORESET/`
371			`// Beginning of autoreset for uninitialized flops`
372			`rMSR_C0 <= 1'h0;`
373			`rMSR_C1 <= 1'h0;`
374			`// End of automatics`
375	81	sybreon	`end else if (ena_i) begin`
376			`if (pha_i)`
377	78	sybreon	`rMSR_C1 <= #1 xMSR_C;`
378	81	sybreon	`else`
379	78	sybreon	`rMSR_C0 <= #1 xMSR_C;`
380	80	sybreon	`end // else: !if(rst_i)`
381	78	sybreon
382			`// IE/BIP/BE`
383			`wire fRTID = (rOPC == 6'o55) & rRD[0];`
384			`wire fRTBD = (rOPC == 6'o55) & rRD[1];`
385			`wire fBRK = ((rOPC == 6'o56) \| (rOPC == 6'o66)) & (rRA == 5'hC);`
386			`wire fINT = ((rOPC == 6'o56) \| (rOPC == 6'o66)) & (rRA == 5'hE);`
387	81	sybreon
388	78	sybreon	`always @(posedge clk_i)`
389			`if (rst_i) begin`
390			`/AUTORESET/`
391			`// Beginning of autoreset for uninitialized flops`
392	81	sybreon	`dwb_tga_o <= 1'h0;`
393			`iwb_tga_o <= 1'h0;`
394	78	sybreon	`rMSR_BE <= 1'h0;`
395			`rMSR_BIP <= 1'h0;`
396			`rMSR_IE <= 1'h0;`
397			`// End of automatics`
398			`end else if (ena_i) begin`
399
400	80	sybreon	`// Interrupt enable (compatible)`
401	78	sybreon	`rMSR_IE <= #1`
402			`(fINT) ? 1'b0 :`
403			`(fRTID) ? 1'b1 :`
404			`(fMTS) ? rOPA[1] :`
405			`rMSR_IE;`
406	80	sybreon
407			`// Break in progress (compatible)`
408	78	sybreon	`rMSR_BIP <= #1`
409			`(fBRK) ? 1'b1 :`
410			`(fRTBD) ? 1'b0 :`
411			`(fMTS) ? rOPA[3] :`
412			`rMSR_BIP;`
413	80	sybreon
414			`// Forcibly assert dwb_cyc_o signal`
415	78	sybreon	`rMSR_BE <= #1`
416	80	sybreon	`(fMTS) ? rOPA[0] : rMSR_BE;`
417	78	sybreon
418	80	sybreon	`// Enable the thread extension`
419	81	sybreon	`//rMSR_TXE <= #1 TXE[0];`
420
421			`// Enable the caches`
422			`dwb_tga_o <= #1 (fMTS) ?`
423			`rOPA[7] :`
424			`dwb_tga_o;`
425			`iwb_tga_o <= #1 (fMTS) ?`
426			`rOPA[5] :`
427			`iwb_tga_o;`
428	80	sybreon
429			`end // if (ena_i)`
430	78	sybreon
431	80	sybreon	`/*`
432			`RESULTS`
433			`*/`
434
435	78	sybreon	`// RESULT`
436			`always @(posedge clk_i)`
437			`if (rst_i) begin`
438			`/AUTORESET/`
439			`// Beginning of autoreset for uninitialized flops`
440			`rRES_EX <= 32'h0;`
441			`rRES_MA <= 32'h0;`
442			`// End of automatics`
443			`end else if (ena_i) begin`
444			`rRES_MA <= #1 rRES_EX;`
445			`case (rALU_OF)`
446			`3'o0: rRES_EX <= #1 rRES_ADD;`
447			`3'o1: rRES_EX <= #1 rRES_LOG;`
448			`3'o2: rRES_EX <= #1 rRES_SFT;`
449			`3'o3: rRES_EX <= #1 rRES_MOV;`
450			`//3'o4: rRES_EX <= (MUL) ? rRES_MUL : 32'hX;`
451			`3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;`
452			`default: rRES_EX <= #1 32'hX;`
453			`endcase // case (rALU_OF)`
454			`end // if (ena_i)`
455
456	80	sybreon	`/*`
457			`DATA/FSL WISHBONE`
458
459			`Asserts the data address as calculated by the adder and the`
460			`appropriate byte select lanes depending on the byte offset of the`
461			`address. It does not check for mis-aligned addresses. */`
462	78	sybreon
463	80	sybreon	`// TODO: Check for mis-alignment`
464
465	78	sybreon	`always @(posedge clk_i)`
466			`if (rst_i) begin`
467			`/AUTORESET/`
468			`// Beginning of autoreset for uninitialized flops`
469			`cwb_adr_o <= 5'h0;`
470			`cwb_sel_o <= 4'h0;`
471			`cwb_tga_o <= 2'h0;`
472			`dwb_adr_o <= {(1+(DWB-1)-(2)){1'b0}};`
473			`dwb_sel_o <= 4'h0;`
474			`rSEL_MA <= 4'h0;`
475			`// End of automatics`
476	80	sybreon	`end else if (ena_i) begin // if (rst_i)`
477	78	sybreon	`rSEL_MA <= #1 dwb_sel_o;`
478
479			`dwb_adr_o <= #1 wADD[DWB-1:2];`
480			`case (rOPC[1:0])`
481			`2'o0: case (wADD[1:0]) // 8'bit`
482			`2'o0: dwb_sel_o <= #1 4'h8;`
483			`2'o1: dwb_sel_o <= #1 4'h4;`
484			`2'o2: dwb_sel_o <= #1 4'h2;`
485			`2'o3: dwb_sel_o <= #1 4'h1;`
486			`endcase // case (wADD[1:0])`
487			`2'o1: dwb_sel_o <= #1 (wADD[1]) ? 4'h3 : 4'hC; // 16'bit`
488			`2'o2: dwb_sel_o <= #1 4'hF; // 32'bit`
489			`2'o3: dwb_sel_o <= #1 4'h0; // FSL`
490			`endcase // case (rOPC[1:0])`
491
492			`{cwb_adr_o, cwb_tga_o} <= #1 {rIMM_OF[4:0], rIMM_OF[15:14]};`
493			`cwb_sel_o <= #1 {(4){ &rOPC[1:0]}};`
494
495			`end // if (ena_i)`
496
497			`endmodule // aeMB2_aslu`
498
499	80	sybreon	`/* $Log: not supported by cvs2svn $`
500	81	sybreon	`/* Revision 1.2 2007/12/12 19:16:59 sybreon`

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