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/* $Id: aeMB2_edk32.v,v 1.8 2007-12-18 18:54:36 sybreon Exp $
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**
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** AEMB2 HI-PERFORMANCE CPU
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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module aeMB2_edk32 (/*AUTOARG*/
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// Outputs
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iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
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dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
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cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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dwb_ack_i, cwb_dat_i, cwb_ack_i
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);
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parameter IWB = 32; // instruction wishbone address space
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parameter DWB = 32; // data wishbone address space
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parameter TXE = 1; // thread execution extension
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parameter MUL = 1; // enable multiply instruction
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parameter BSF = 1; // enable barrel shift instructions
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parameter FSL = 1; // enable get/put instructions
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [6:2] cwb_adr_o; // From aslu of aeMB2_aslu.v
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output [31:0] cwb_dat_o; // From regf of aeMB2_regf.v
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output [3:0] cwb_sel_o; // From aslu of aeMB2_aslu.v
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output cwb_stb_o; // From sysc of aeMB2_sysc.v
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output [1:0] cwb_tga_o; // From aslu of aeMB2_aslu.v
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output cwb_wre_o; // From sysc of aeMB2_sysc.v
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output [DWB-1:2] dwb_adr_o; // From aslu of aeMB2_aslu.v
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output dwb_cyc_o; // From sysc of aeMB2_sysc.v
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output [31:0] dwb_dat_o; // From regf of aeMB2_regf.v
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output [3:0] dwb_sel_o; // From aslu of aeMB2_aslu.v
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output dwb_stb_o; // From sysc of aeMB2_sysc.v
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output dwb_tga_o; // From aslu of aeMB2_aslu.v
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output dwb_wre_o; // From sysc of aeMB2_sysc.v
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output [IWB-1:2] iwb_adr_o; // From bpcu of aeMB2_bpcu.v
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output iwb_stb_o; // From sysc of aeMB2_sysc.v
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output iwb_tga_o; // From aslu of aeMB2_aslu.v
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output iwb_wre_o; // From sysc of aeMB2_sysc.v
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// End of automatics
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input cwb_ack_i; // To sysc of aeMB2_sysc.v, ...
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input [31:0] cwb_dat_i; // To regf of aeMB2_regf.v
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input dwb_ack_i; // To sysc of aeMB2_sysc.v, ...
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input [31:0] dwb_dat_i; // To regf of aeMB2_regf.v
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input iwb_ack_i; // To sysc of aeMB2_sysc.v, ...
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input [31:0] iwb_dat_i; // To bpcu of aeMB2_bpcu.v
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input sys_clk_i; // To sysc of aeMB2_sysc.v
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input sys_int_i; // To sysc of aeMB2_sysc.v
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input sys_rst_i; // To sysc of aeMB2_sysc.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire clk_i; // From sysc of aeMB2_sysc.v
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wire ena_i; // From sysc of aeMB2_sysc.v
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wire pha_i; // From sysc of aeMB2_sysc.v
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wire [10:0] rALT_IF; // From bpcu of aeMB2_bpcu.v
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wire [2:0] rALU_OF; // From ofid of aeMB2_ofid.v
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wire [1:0] rBRA; // From bpcu of aeMB2_bpcu.v
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wire [15:0] rIMM_IF; // From bpcu of aeMB2_bpcu.v
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wire [15:0] rIMM_OF; // From ofid of aeMB2_ofid.v
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wire rINT; // From sysc of aeMB2_sysc.v
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wire rMSR_BE; // From aslu of aeMB2_aslu.v
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wire rMSR_BIP; // From aslu of aeMB2_aslu.v
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wire rMSR_IE; // From aslu of aeMB2_aslu.v
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wire [31:0] rMUL_MA; // From aslu of aeMB2_aslu.v
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wire [31:0] rOPA_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPB_OF; // From ofid of aeMB2_ofid.v
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wire [5:0] rOPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [5:0] rOPC_OF; // From ofid of aeMB2_ofid.v
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wire [2:0] rOPD_EX; // From ofid of aeMB2_ofid.v
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wire [2:0] rOPD_MA; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPM_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPX_OF; // From ofid of aeMB2_ofid.v
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wire [31:2] rPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [31:2] rPC_MA; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRA_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRA_OF; // From ofid of aeMB2_ofid.v
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wire [4:0] rRB_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRD_EX; // From ofid of aeMB2_ofid.v
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wire [4:0] rRD_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRD_MA; // From ofid of aeMB2_ofid.v
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wire [4:0] rRD_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rREGA_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGB_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGD_OF; // From regf of aeMB2_regf.v
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wire [31:0] rRES_EX; // From aslu of aeMB2_aslu.v
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wire [31:0] rRES_MA; // From aslu of aeMB2_aslu.v
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wire [3:0] rSEL_MA; // From aslu of aeMB2_aslu.v
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wire rXCE; // From sysc of aeMB2_sysc.v
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wire rst_i; // From sysc of aeMB2_sysc.v
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// End of automatics
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/* aeMB2_sysc AUTO_TEMPLATE (
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.clk_o(clk_i),
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.rst_o(rst_i),
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.ena_o(ena_i),
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.pha_o(pha_i),
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)*/
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/* System/Interrupt Control */
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aeMB2_sysc
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#(/*AUTOINSTPARAM*/
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// Parameters
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.TXE (TXE),
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.FSL (FSL))
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sysc (/*AUTOINST*/
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// Outputs
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.rINT (rINT),
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.rXCE (rXCE),
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.pha_o (pha_i), // Templated
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.clk_o (clk_i), // Templated
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.rst_o (rst_i), // Templated
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.ena_o (ena_i), // Templated
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.iwb_stb_o (iwb_stb_o),
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.iwb_wre_o (iwb_wre_o),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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.cwb_stb_o (cwb_stb_o),
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.cwb_wre_o (cwb_wre_o),
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// Inputs
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.rIMM_OF (rIMM_OF[15:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rRA_OF (rRA_OF[4:0]),
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.rMSR_BE (rMSR_BE),
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.rMSR_BIP (rMSR_BIP),
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.rMSR_IE (rMSR_IE),
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.rOPC_IF (rOPC_IF[5:0]),
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.iwb_ack_i (iwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.cwb_ack_i (cwb_ack_i),
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.sys_int_i (sys_int_i),
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.sys_clk_i (sys_clk_i),
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.sys_rst_i (sys_rst_i));
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/* Register file */
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aeMB2_regf
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#(/*AUTOINSTPARAM*/
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// Parameters
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.TXE (TXE),
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.MUL (MUL))
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regf (/*AUTOINST*/
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// Outputs
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.dwb_dat_o (dwb_dat_o[31:0]),
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.cwb_dat_o (cwb_dat_o[31:0]),
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.rREGD_OF (rREGD_OF[31:0]),
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.rREGA_OF (rREGA_OF[31:0]),
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.rREGB_OF (rREGB_OF[31:0]),
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// Inputs
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_ack_i (dwb_ack_i),
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.cwb_dat_i (cwb_dat_i[31:0]),
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.cwb_ack_i (cwb_ack_i),
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.rRA_IF (rRA_IF[4:0]),
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.rRB_IF (rRB_IF[4:0]),
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.rRD_IF (rRD_IF[4:0]),
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.rRD_MA (rRD_MA[4:0]),
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.rOPM_OF (rOPM_OF[31:0]),
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.rOPA_OF (rOPA_OF[31:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rPC_MA (rPC_MA[31:2]),
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.rMUL_MA (rMUL_MA[31:0]),
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.rRES_MA (rRES_MA[31:0]),
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.rOPD_MA (rOPD_MA[2:0]),
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.rSEL_MA (rSEL_MA[3:0]),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.ena_i (ena_i),
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.pha_i (pha_i));
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/* Branch/Programme Counter Unit */
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aeMB2_bpcu
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#(/*AUTOINSTPARAM*/
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// Parameters
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.IWB (IWB),
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.TXE (TXE))
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bpcu (/*AUTOINST*/
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// Outputs
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.iwb_adr_o (iwb_adr_o[IWB-1:2]),
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.rPC_MA (rPC_MA[31:2]),
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.rPC_IF (rPC_IF[31:2]),
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.rIMM_IF (rIMM_IF[15:0]),
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.rALT_IF (rALT_IF[10:0]),
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.rOPC_IF (rOPC_IF[5:0]),
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.rRD_IF (rRD_IF[4:0]),
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.rRA_IF (rRA_IF[4:0]),
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.rRB_IF (rRB_IF[4:0]),
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.rBRA (rBRA[1:0]),
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// Inputs
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.rOPX_OF (rOPX_OF[31:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rRA_OF (rRA_OF[4:0]),
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.rRD_OF (rRD_OF[4:0]),
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.rRES_EX (rRES_EX[31:0]),
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.rRD_EX (rRD_EX[4:0]),
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.rOPD_EX (rOPD_EX[2:0]),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.ena_i (ena_i),
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.pha_i (pha_i));
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/* Operand Fetch Mux */
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aeMB2_ofid
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#(/*AUTOINSTPARAM*/
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// Parameters
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.TXE (TXE),
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.MUL (MUL),
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.BSF (BSF),
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.FSL (FSL))
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ofid (/*AUTOINST*/
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// Outputs
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.rOPM_OF (rOPM_OF[31:0]),
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.rOPX_OF (rOPX_OF[31:0]),
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.rOPA_OF (rOPA_OF[31:0]),
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.rOPB_OF (rOPB_OF[31:0]),
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.rIMM_OF (rIMM_OF[15:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rRA_OF (rRA_OF[4:0]),
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.rRD_OF (rRD_OF[4:0]),
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.rRD_EX (rRD_EX[4:0]),
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.rRD_MA (rRD_MA[4:0]),
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.rOPD_EX (rOPD_EX[2:0]),
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.rOPD_MA (rOPD_MA[2:0]),
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.rALU_OF (rALU_OF[2:0]),
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// Inputs
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.rRES_EX (rRES_EX[31:0]),
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.rREGD_OF (rREGD_OF[31:0]),
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.rREGA_OF (rREGA_OF[31:0]),
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.rREGB_OF (rREGB_OF[31:0]),
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.rBRA (rBRA[1:0]),
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.rXCE (rXCE),
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.rINT (rINT),
|
| 261 |
85 |
sybreon |
.rPC_IF (rPC_IF[31:2]),
|
| 262 |
78 |
sybreon |
.rIMM_IF (rIMM_IF[15:0]),
|
| 263 |
|
|
.rALT_IF (rALT_IF[10:0]),
|
| 264 |
|
|
.rOPC_IF (rOPC_IF[5:0]),
|
| 265 |
|
|
.rRA_IF (rRA_IF[4:0]),
|
| 266 |
|
|
.rRB_IF (rRB_IF[4:0]),
|
| 267 |
|
|
.rRD_IF (rRD_IF[4:0]),
|
| 268 |
|
|
.pha_i (pha_i),
|
| 269 |
|
|
.clk_i (clk_i),
|
| 270 |
|
|
.rst_i (rst_i),
|
| 271 |
85 |
sybreon |
.ena_i (ena_i));
|
| 272 |
|
|
|
| 273 |
|
|
|
| 274 |
78 |
sybreon |
/* Arithmetic Shift Logic Unit */
|
| 275 |
|
|
|
| 276 |
|
|
aeMB2_aslu
|
| 277 |
|
|
#(/*AUTOINSTPARAM*/
|
| 278 |
|
|
// Parameters
|
| 279 |
|
|
.DWB (DWB),
|
| 280 |
80 |
sybreon |
.TXE (TXE),
|
| 281 |
78 |
sybreon |
.MUL (MUL),
|
| 282 |
|
|
.BSF (BSF),
|
| 283 |
80 |
sybreon |
.FSL (FSL))
|
| 284 |
78 |
sybreon |
aslu (/*AUTOINST*/
|
| 285 |
|
|
// Outputs
|
| 286 |
|
|
.dwb_adr_o (dwb_adr_o[DWB-1:2]),
|
| 287 |
|
|
.dwb_sel_o (dwb_sel_o[3:0]),
|
| 288 |
|
|
.rSEL_MA (rSEL_MA[3:0]),
|
| 289 |
|
|
.cwb_adr_o (cwb_adr_o[6:2]),
|
| 290 |
|
|
.cwb_tga_o (cwb_tga_o[1:0]),
|
| 291 |
|
|
.cwb_sel_o (cwb_sel_o[3:0]),
|
| 292 |
81 |
sybreon |
.iwb_tga_o (iwb_tga_o),
|
| 293 |
|
|
.dwb_tga_o (dwb_tga_o),
|
| 294 |
78 |
sybreon |
.rMUL_MA (rMUL_MA[31:0]),
|
| 295 |
|
|
.rRES_MA (rRES_MA[31:0]),
|
| 296 |
|
|
.rRES_EX (rRES_EX[31:0]),
|
| 297 |
|
|
.rMSR_IE (rMSR_IE),
|
| 298 |
|
|
.rMSR_BE (rMSR_BE),
|
| 299 |
|
|
.rMSR_BIP (rMSR_BIP),
|
| 300 |
|
|
// Inputs
|
| 301 |
|
|
.rIMM_OF (rIMM_OF[15:0]),
|
| 302 |
|
|
.rALU_OF (rALU_OF[2:0]),
|
| 303 |
|
|
.rOPC_OF (rOPC_OF[5:0]),
|
| 304 |
80 |
sybreon |
.rOPC_IF (rOPC_IF[5:0]),
|
| 305 |
78 |
sybreon |
.rRA_OF (rRA_OF[4:0]),
|
| 306 |
|
|
.rRD_OF (rRD_OF[4:0]),
|
| 307 |
|
|
.rOPA_OF (rOPA_OF[31:0]),
|
| 308 |
|
|
.rOPB_OF (rOPB_OF[31:0]),
|
| 309 |
|
|
.pha_i (pha_i),
|
| 310 |
|
|
.clk_i (clk_i),
|
| 311 |
|
|
.rst_i (rst_i),
|
| 312 |
|
|
.ena_i (ena_i));
|
| 313 |
80 |
sybreon |
|
| 314 |
78 |
sybreon |
|
| 315 |
76 |
sybreon |
endmodule // aeMB2_edk32
|
| 316 |
|
|
|
| 317 |
78 |
sybreon |
/* $Log: not supported by cvs2svn $
|
| 318 |
92 |
sybreon |
/* Revision 1.7 2007/12/17 12:53:13 sybreon
|
| 319 |
|
|
/* Changed simulation kernel.
|
| 320 |
|
|
/*
|
| 321 |
89 |
sybreon |
/* Revision 1.6 2007/12/16 03:25:22 sybreon
|
| 322 |
|
|
/* Replaced OF/ID blocks with combined block.
|
| 323 |
|
|
/*
|
| 324 |
85 |
sybreon |
/* Revision 1.5 2007/12/13 21:25:41 sybreon
|
| 325 |
|
|
/* Further optimisations (speed + size).
|
| 326 |
|
|
/*
|
| 327 |
82 |
sybreon |
/* Revision 1.4 2007/12/13 20:12:11 sybreon
|
| 328 |
|
|
/* Code cleanup + minor speed regression.
|
| 329 |
|
|
/*
|
| 330 |
81 |
sybreon |
/* Revision 1.3 2007/12/12 19:16:59 sybreon
|
| 331 |
|
|
/* Minor optimisations (~10% faster)
|
| 332 |
|
|
/*
|
| 333 |
80 |
sybreon |
/* Revision 1.2 2007/12/11 00:43:17 sybreon
|
| 334 |
|
|
/* initial import
|
| 335 |
|
|
/*
|
| 336 |
78 |
sybreon |
/* Revision 1.1 2007/12/07 18:58:51 sybreon
|
| 337 |
|
|
/* initial
|
| 338 |
|
|
/* */
|
