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/* $Id: aeMB2_edk32.v,v 1.2 2007-12-11 00:43:17 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aeMB2_edk32 (/*AUTOARG*/
   // Outputs
   iwb_wre_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o,
   dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o, cwb_tga_o, cwb_stb_o,
   cwb_sel_o, cwb_dat_o, cwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
   dwb_ack_i, cwb_dat_i, cwb_ack_i
   );
   parameter IWB = 32; ///< instruction wishbone address space
   parameter DWB = 32; ///< data wishbone address space
 
   parameter TXE = 1; ///< thread execution extension
   parameter LUT = 1; ///< further speed optimisation
 
   parameter MUL = 1; ///< enable hardware multiplier
   parameter BSF = 1; ///< enable barrel shifter
   parameter FSL = 1; ///< enable FSL bus
   parameter DIV = 0; ///< enable hardware divider
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [6:2]         cwb_adr_o;              // From aslu of aeMB2_aslu.v
   output [31:0] cwb_dat_o;              // From regf of aeMB2_regf.v
   output [3:0]          cwb_sel_o;              // From aslu of aeMB2_aslu.v
   output               cwb_stb_o;              // From sysc of aeMB2_sysc.v
   output [1:0]          cwb_tga_o;              // From aslu of aeMB2_aslu.v
   output               cwb_wre_o;              // From sysc of aeMB2_sysc.v
   output [DWB-1:2]     dwb_adr_o;              // From aslu of aeMB2_aslu.v
   output               dwb_cyc_o;              // From sysc of aeMB2_sysc.v
   output [31:0] dwb_dat_o;              // From regf of aeMB2_regf.v
   output [3:0]          dwb_sel_o;              // From aslu of aeMB2_aslu.v
   output               dwb_stb_o;              // From sysc of aeMB2_sysc.v
   output               dwb_wre_o;              // From sysc of aeMB2_sysc.v
   output [IWB-1:2]     iwb_adr_o;              // From bpcu of aeMB2_bpcu.v
   output               iwb_stb_o;              // From sysc of aeMB2_sysc.v
   output               iwb_wre_o;              // From sysc of aeMB2_sysc.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                cwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          cwb_dat_i;              // To regf of aeMB2_regf.v
   input                dwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          dwb_dat_i;              // To regf of aeMB2_regf.v
   input                iwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          iwb_dat_i;              // To bpcu of aeMB2_bpcu.v
   input                sys_clk_i;              // To sysc of aeMB2_sysc.v
   input                sys_int_i;              // To sysc of aeMB2_sysc.v
   input                sys_rst_i;              // To sysc of aeMB2_sysc.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 clk_i;                  // From sysc of aeMB2_sysc.v
   wire                 ena_i;                  // From sysc of aeMB2_sysc.v
   wire                 pha_i;                  // From sysc of aeMB2_sysc.v
   wire [10:0]           rALT_IF;                // From bpcu of aeMB2_bpcu.v
   wire [2:0]            rALU_OF;                // From idmx of aeMB2_idmx.v
   wire [1:0]            rBRA;                   // From bpcu of aeMB2_bpcu.v
   wire [15:0]           rIMM_IF;                // From bpcu of aeMB2_bpcu.v
   wire [15:0]           rIMM_OF;                // From idmx of aeMB2_idmx.v
   wire                 rINT;                   // From sysc of aeMB2_sysc.v
   wire                 rMSR_BE;                // From aslu of aeMB2_aslu.v
   wire                 rMSR_BIP;               // From aslu of aeMB2_aslu.v
   wire                 rMSR_IE;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rMUL_MA;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rOPA_OF;                // From opmx of aeMB2_opmx.v
   wire [31:0]           rOPB_OF;                // From opmx of aeMB2_opmx.v
   wire [5:0]            rOPC_IF;                // From bpcu of aeMB2_bpcu.v
   wire [5:0]            rOPC_OF;                // From idmx of aeMB2_idmx.v
   wire [2:0]            rOPD_EX;                // From idmx of aeMB2_idmx.v
   wire [2:0]            rOPD_MA;                // From idmx of aeMB2_idmx.v
   wire [31:0]           rOPM_OF;                // From opmx of aeMB2_opmx.v
   wire [31:0]           rOPX_OF;                // From opmx of aeMB2_opmx.v
   wire [31:2]          rPC_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [31:2]          rPC_MA;                 // From bpcu of aeMB2_bpcu.v
   wire [31:2]          rPC_OF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRA_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRA_OF;                 // From idmx of aeMB2_idmx.v
   wire [4:0]            rRB_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRD_EX;                 // From idmx of aeMB2_idmx.v
   wire [4:0]            rRD_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRD_MA;                 // From idmx of aeMB2_idmx.v
   wire [4:0]            rRD_OF;                 // From idmx of aeMB2_idmx.v
   wire [31:0]           rREGA_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rREGB_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rREGD_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rRES_EX;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rRES_MA;                // From aslu of aeMB2_aslu.v
   wire [3:0]            rSEL_MA;                // From aslu of aeMB2_aslu.v
   wire                 rXCE;                   // From sysc of aeMB2_sysc.v
   wire                 rst_i;                  // From sysc of aeMB2_sysc.v
   // End of automatics
 
   /* aeMB2_sysc AUTO_TEMPLATE (
    .clk_o(clk_i),
    .rst_o(rst_i),
    .ena_o(ena_i),
    .pha_o(pha_i),
    )*/
 
   /* System/Interrupt Control */
 
   aeMB2_sysc
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE))
   sysc (/*AUTOINST*/
         // Outputs
         .iwb_stb_o                     (iwb_stb_o),
         .iwb_wre_o                     (iwb_wre_o),
         .dwb_cyc_o                     (dwb_cyc_o),
         .dwb_stb_o                     (dwb_stb_o),
         .dwb_wre_o                     (dwb_wre_o),
         .cwb_stb_o                     (cwb_stb_o),
         .cwb_wre_o                     (cwb_wre_o),
         .rINT                          (rINT),
         .rXCE                          (rXCE),
         .pha_o                         (pha_i),                 // Templated
         .clk_o                         (clk_i),                 // Templated
         .rst_o                         (rst_i),                 // Templated
         .ena_o                         (ena_i),                 // Templated
         // Inputs
         .rOPC_IF                       (rOPC_IF[5:0]),
         .iwb_ack_i                     (iwb_ack_i),
         .dwb_ack_i                     (dwb_ack_i),
         .cwb_ack_i                     (cwb_ack_i),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rMSR_BE                       (rMSR_BE),
         .rMSR_BIP                      (rMSR_BIP),
         .rMSR_IE                       (rMSR_IE),
         .sys_int_i                     (sys_int_i),
         .sys_clk_i                     (sys_clk_i),
         .sys_rst_i                     (sys_rst_i));
 
   /* Register file */
 
   aeMB2_regf
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE))
   regf (/*AUTOINST*/
         // Outputs
         .dwb_dat_o                     (dwb_dat_o[31:0]),
         .cwb_dat_o                     (cwb_dat_o[31:0]),
         .rREGD_OF                      (rREGD_OF[31:0]),
         .rREGA_OF                      (rREGA_OF[31:0]),
         .rREGB_OF                      (rREGB_OF[31:0]),
         // Inputs
         .dwb_dat_i                     (dwb_dat_i[31:0]),
         .dwb_ack_i                     (dwb_ack_i),
         .cwb_dat_i                     (cwb_dat_i[31:0]),
         .cwb_ack_i                     (cwb_ack_i),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .rRD_MA                        (rRD_MA[4:0]),
         .rOPM_OF                       (rOPM_OF[31:0]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rPC_MA                        (rPC_MA[31:2]),
         .rMUL_MA                       (rMUL_MA[31:0]),
         .rRES_MA                       (rRES_MA[31:0]),
         .rOPD_MA                       (rOPD_MA[2:0]),
         .rSEL_MA                       (rSEL_MA[3:0]),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i),
         .pha_i                         (pha_i));
 
   /* Branch/Programme Counter Unit */
 
   aeMB2_bpcu
     #(/*AUTOINSTPARAM*/
       // Parameters
       .IWB                             (IWB),
       .TXE                             (TXE),
       .LUT                             (LUT))
   bpcu (/*AUTOINST*/
         // Outputs
         .iwb_adr_o                     (iwb_adr_o[IWB-1:2]),
         .rPC_OF                        (rPC_OF[31:2]),
         .rPC_MA                        (rPC_MA[31:2]),
         .rPC_IF                        (rPC_IF[31:2]),
         .rIMM_IF                       (rIMM_IF[15:0]),
         .rALT_IF                       (rALT_IF[10:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rBRA                          (rBRA[1:0]),
         // Inputs
         .iwb_dat_i                     (iwb_dat_i[31:0]),
         .iwb_ack_i                     (iwb_ack_i),
         .rOPX_OF                       (rOPX_OF[31:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rRES_EX                       (rRES_EX[31:0]),
         .rRD_EX                        (rRD_EX[4:0]),
         .rOPD_EX                       (rOPD_EX[2:0]),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i),
         .pha_i                         (pha_i));
 
   /* Operand Fetch Mux */
 
   aeMB2_opmx
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE),
       .LUT                             (LUT))
   opmx (/*AUTOINST*/
         // Outputs
         .rOPM_OF                       (rOPM_OF[31:0]),
         .rOPX_OF                       (rOPX_OF[31:0]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPB_OF                       (rOPB_OF[31:0]),
         // Inputs
         .rRES_EX                       (rRES_EX[31:0]),
         .rRD_EX                        (rRD_EX[4:0]),
         .rOPD_EX                       (rOPD_EX[1:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rIMM_IF                       (rIMM_IF[15:0]),
         .rPC_IF                        (rPC_IF[31:2]),
         .rRD_IF                        (rRD_IF[4:0]),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rREGD_OF                      (rREGD_OF[31:0]),
         .rREGA_OF                      (rREGA_OF[31:0]),
         .rREGB_OF                      (rREGB_OF[31:0]),
         .rBRA                          (rBRA[1:0]),
         .pha_i                         (pha_i),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i));
 
   /* Instruction Decode Mux */
 
   aeMB2_idmx
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE),
       .MUL                             (MUL),
       .BSF                             (BSF),
       .DIV                             (DIV),
       .FSL                             (FSL))
   idmx (/*AUTOINST*/
         // Outputs
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rRD_EX                        (rRD_EX[4:0]),
         .rRD_MA                        (rRD_MA[4:0]),
         .rOPD_EX                       (rOPD_EX[2:0]),
         .rOPD_MA                       (rOPD_MA[2:0]),
         .rALU_OF                       (rALU_OF[2:0]),
         // Inputs
         .rBRA                          (rBRA[1:0]),
         .rXCE                          (rXCE),
         .rINT                          (rINT),
         .rIMM_IF                       (rIMM_IF[15:0]),
         .rALT_IF                       (rALT_IF[10:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .pha_i                         (pha_i),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i));
 
 
   /* Arithmetic Shift Logic Unit */
 
   aeMB2_aslu
     #(/*AUTOINSTPARAM*/
       // Parameters
       .DWB                             (DWB),
       .MUL                             (MUL),
       .BSF                             (BSF),
       .FSL                             (FSL),
       .TXE                             (TXE),
       .LUT                             (LUT))
   aslu (/*AUTOINST*/
         // Outputs
         .dwb_adr_o                     (dwb_adr_o[DWB-1:2]),
         .dwb_sel_o                     (dwb_sel_o[3:0]),
         .rSEL_MA                       (rSEL_MA[3:0]),
         .cwb_adr_o                     (cwb_adr_o[6:2]),
         .cwb_tga_o                     (cwb_tga_o[1:0]),
         .cwb_sel_o                     (cwb_sel_o[3:0]),
         .rMUL_MA                       (rMUL_MA[31:0]),
         .rRES_MA                       (rRES_MA[31:0]),
         .rRES_EX                       (rRES_EX[31:0]),
         .rMSR_IE                       (rMSR_IE),
         .rMSR_BE                       (rMSR_BE),
         .rMSR_BIP                      (rMSR_BIP),
         // Inputs
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rALU_OF                       (rALU_OF[2:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rPC_OF                        (rPC_OF[31:2]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPB_OF                       (rOPB_OF[31:0]),
         .pha_i                         (pha_i),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i));
 
   // synopsys translate_off
`ifdef AEMB2_SIMULATION_KERNEL
   wire [31:0]           iwb_adr = {iwb_adr_o, 2'd0};
   wire [31:0]           dwb_adr = {dwb_adr_o, 2'd0};
   wire [3:0]            wMSR = dut.aslu.wMSR[3:0];
 
   always @(posedge clk_i) if (ena_i) begin
 
      $write ("\n", ($stime/10));
      $writeh (" T", pha_i);
      $writeh(" PC=", iwb_adr);
 
      $writeh ("\t| ");
 
      case (rOPC_IF)
        6'o00: if (rRD_IF == 0) $write("   "); else $write("ADD");
        6'o01: $write("RSUB");
        6'o02: $write("ADDC");
        6'o03: $write("RSUBC");
        6'o04: $write("ADDK");
        6'o05: case (rIMM_IF[1:0])
                 2'o0: $write("RSUBK");
                 2'o1: $write("CMP");
                 2'o3: $write("CMPU");
                 default: $write("XXX");
               endcase // case (rIMM_IF[1:0])
        6'o06: $write("ADDKC");
        6'o07: $write("RSUBKC");
 
        6'o10: $write("ADDI");
        6'o11: $write("RSUBI");
        6'o12: $write("ADDIC");
        6'o13: $write("RSUBIC");
        6'o14: $write("ADDIK");
        6'o15: $write("RSUBIK");
        6'o16: $write("ADDIKC");
        6'o17: $write("RSUBIKC");
 
        6'o20: $write("MUL");
        6'o21: case (rALT_IF[10:9])
                 2'o0: $write("BSRL");
                 2'o1: $write("BSRA");
                 2'o2: $write("BSLL");
                 default: $write("XXX");
               endcase // case (rALT_IF[10:9])
        6'o22: $write("IDIV");
 
        6'o30: $write("MULI");
        6'o31: case (rALT_IF[10:9])
                 2'o0: $write("BSRLI");
                 2'o1: $write("BSRAI");
                 2'o2: $write("BSLLI");
                 default: $write("XXX");
               endcase // case (rALT_IF[10:9])
        6'o33: case (rRB_IF[4:2])
                 3'o0: $write("GET");
                 3'o4: $write("PUT");
                 3'o2: $write("NGET");
                 3'o6: $write("NPUT");
                 3'o1: $write("CGET");
                 3'o5: $write("CPUT");
                 3'o3: $write("NCGET");
                 3'o7: $write("NCPUT");
               endcase // case (rRB_IF[4:2])
 
        6'o40: $write("OR");
        6'o41: $write("AND");
        6'o42: if (rRD_IF == 0) $write("   "); else $write("XOR");
        6'o43: $write("ANDN");
        6'o44: case (rIMM_IF[6:5])
                 2'o0: $write("SRA");
                 2'o1: $write("SRC");
                 2'o2: $write("SRL");
                 2'o3: if (rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
               endcase // case (rIMM_IF[6:5])
 
        6'o45: $write("MOV");
        6'o46: case (rRA_IF[3:2])
                 3'o0: $write("BR");
                 3'o1: $write("BRL");
                 3'o2: $write("BRA");
                 3'o3: $write("BRAL");
               endcase // case (rRA_IF[3:2])
 
        6'o47: case (rRD_IF[2:0])
                 3'o0: $write("BEQ");
                 3'o1: $write("BNE");
                 3'o2: $write("BLT");
                 3'o3: $write("BLE");
                 3'o4: $write("BGT");
                 3'o5: $write("BGE");
                 default: $write("XXX");
               endcase // case (rRD_IF[2:0])
 
        6'o50: $write("ORI");
        6'o51: $write("ANDI");
        6'o52: $write("XORI");
        6'o53: $write("ANDNI");
        6'o54: $write("IMMI");
        6'o55: case (rRD_IF[1:0])
                 2'o0: $write("RTSD");
                 2'o1: $write("RTID");
                 2'o2: $write("RTBD");
                 default: $write("XXX");
               endcase // case (rRD_IF[1:0])
        6'o56: case (rRA_IF[3:2])
                 3'o0: $write("BRI");
                 3'o1: $write("BRLI");
                 3'o2: $write("BRAI");
                 3'o3: $write("BRALI");
               endcase // case (rRA_IF[3:2])
        6'o57: case (rRD_IF[2:0])
                 3'o0: $write("BEQI");
                 3'o1: $write("BNEI");
                 3'o2: $write("BLTI");
                 3'o3: $write("BLEI");
                 3'o4: $write("BGTI");
                 3'o5: $write("BGEI");
                 default: $write("XXX");
               endcase // case (rRD_IF[2:0])
 
        6'o60: $write("LBU");
        6'o61: $write("LHU");
        6'o62: $write("LW");
        6'o64: $write("SB");
        6'o65: $write("SH");
        6'o66: $write("SW");
 
        6'o70: $write("LBUI");
        6'o71: $write("LHUI");
        6'o72: $write("LWI");
        6'o74: $write("SBI");
        6'o75: $write("SHI");
        6'o76: $write("SWI");
 
        default: $write("XXX");
      endcase // case (rOPC_IF)
 
      case (rOPC_IF[3])
        1'b1: $writeh("\t r",rRD_IF,", r",rRA_IF,", h",rIMM_IF);
        1'b0: $writeh("\t r",rRD_IF,", r",rRA_IF,", r",rRB_IF,"  ");
      endcase // case (rOPC_IF[3])
 
      if (dut.bpcu.fHAZARD)
        $write ("*");
 
      // ALU
      $write("\t|");
      $writeh(" A=",rOPA_OF);
      $writeh(" B=",rOPB_OF);
      $writeh(" C=",rOPX_OF);
      $writeh(" M=",rOPM_OF);
 
      $writeh(" MSR=", wMSR," ");
 
      case (rALU_OF)
        3'o0: if (dwb_stb_o)
          $write(" RAM");
        else
          $write(" ADD");
        3'o1: $write(" LOG");
        3'o2: $write(" SFT");
        3'o3: $write(" MOV");
        3'o4: $write(" MUL");
        3'o5: $write(" BSF");
        default: $write(" XXX");
      endcase // case (rALU_OF)
 
      // MA
      $write ("\t| ");
      if (dwb_stb_o)
        $writeh("@",rRES_EX);
      else
        $writeh("=",rRES_EX);
 
 
      case (rBRA)
        2'b00: $write(" ");
        2'b01: $write(".");
        2'b10: $write("-");
        2'b11: $write("+");
      endcase // case (rBRA)
 
      // WRITEBACK
      $write("\t|");
 
      if (regf.fWRE) begin
         case (rOPD_MA)
           2'o2: begin
              if (rSEL_MA != 4'h0) $writeh("R",rRD_MA,"=RAM(",regf.rREGD,")");
              if (rSEL_MA == 4'h0) $writeh("R",rRD_MA,"=FSL(",regf.rREGD,")");
           end
           2'o1: $writeh("R",rRD_MA,"=LNK(",regf.rREGD,")");
           2'o0: $writeh("R",rRD_MA,"=ALU(",regf.rREGD,")");
         endcase // case (rOPD_MA)
      end
 
      /*
      // STORE
      if (dwb_stb_o & dwb_wre_o) begin
         $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
         case (dwb_sel_o)
           4'hF: $write(":L");
           4'h3,4'hC: $write(":W");
           4'h1,4'h2,4'h4,4'h8: $write(":B");
         endcase // case (dwb_sel_o)
 
      end
       */
   end // if (ena_i)
 
`endif //  `ifdef AEMB_SIMULATION_KERNEL
   // synopsys translate_on
 
 
endmodule // aeMB2_edk32
 
/* $Log: not supported by cvs2svn $
/* Revision 1.1  2007/12/07 18:58:51  sybreon
/* initial
/* */

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1	78	sybreon	`/* $Id: aeMB2_edk32.v,v 1.2 2007-12-11 00:43:17 sybreon Exp $`
2	76	sybreon	`**`
3			`** AEMB2 HI-PERFORMANCE CPU`
4			`**`
5			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`**`
7			`** This file is part of AEMB.`
8			`**`
9			`** AEMB is free software: you can redistribute it and/or modify it`
10			`** under the terms of the GNU Lesser General Public License as`
11			`** published by the Free Software Foundation, either version 3 of the`
12			`** License, or (at your option) any later version.`
13			`**`
14			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20	78	sybreon	`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	76	sybreon	`*/`
22
23	78	sybreon	`module aeMB2_edk32 (/AUTOARG/`
24			`// Outputs`
25			`iwb_wre_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o,`
26			`dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o, cwb_tga_o, cwb_stb_o,`
27			`cwb_sel_o, cwb_dat_o, cwb_adr_o,`
28			`// Inputs`
29			`sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,`
30			`dwb_ack_i, cwb_dat_i, cwb_ack_i`
31			`);`
32	76	sybreon	`parameter IWB = 32; ///< instruction wishbone address space`
33			`parameter DWB = 32; ///< data wishbone address space`
34	78	sybreon
35			`parameter TXE = 1; ///< thread execution extension`
36			`parameter LUT = 1; ///< further speed optimisation`
37
38	76	sybreon	`parameter MUL = 1; ///< enable hardware multiplier`
39			`parameter BSF = 1; ///< enable barrel shifter`
40	78	sybreon	`parameter FSL = 1; ///< enable FSL bus`
41	76	sybreon	`parameter DIV = 0; ///< enable hardware divider`
42	78	sybreon
43			`/AUTOOUTPUT/`
44			`// Beginning of automatic outputs (from unused autoinst outputs)`
45			`output [6:2] cwb_adr_o; // From aslu of aeMB2_aslu.v`
46			`output [31:0] cwb_dat_o; // From regf of aeMB2_regf.v`
47			`output [3:0] cwb_sel_o; // From aslu of aeMB2_aslu.v`
48			`output cwb_stb_o; // From sysc of aeMB2_sysc.v`
49			`output [1:0] cwb_tga_o; // From aslu of aeMB2_aslu.v`
50			`output cwb_wre_o; // From sysc of aeMB2_sysc.v`
51			`output [DWB-1:2] dwb_adr_o; // From aslu of aeMB2_aslu.v`
52			`output dwb_cyc_o; // From sysc of aeMB2_sysc.v`
53			`output [31:0] dwb_dat_o; // From regf of aeMB2_regf.v`
54			`output [3:0] dwb_sel_o; // From aslu of aeMB2_aslu.v`
55			`output dwb_stb_o; // From sysc of aeMB2_sysc.v`
56			`output dwb_wre_o; // From sysc of aeMB2_sysc.v`
57			`output [IWB-1:2] iwb_adr_o; // From bpcu of aeMB2_bpcu.v`
58			`output iwb_stb_o; // From sysc of aeMB2_sysc.v`
59			`output iwb_wre_o; // From sysc of aeMB2_sysc.v`
60			`// End of automatics`
61			`/AUTOINPUT/`
62			`// Beginning of automatic inputs (from unused autoinst inputs)`
63			`input cwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
64			`input [31:0] cwb_dat_i; // To regf of aeMB2_regf.v`
65			`input dwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
66			`input [31:0] dwb_dat_i; // To regf of aeMB2_regf.v`
67			`input iwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
68			`input [31:0] iwb_dat_i; // To bpcu of aeMB2_bpcu.v`
69			`input sys_clk_i; // To sysc of aeMB2_sysc.v`
70			`input sys_int_i; // To sysc of aeMB2_sysc.v`
71			`input sys_rst_i; // To sysc of aeMB2_sysc.v`
72			`// End of automatics`
73			`/AUTOWIRE/`
74			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
75			`wire clk_i; // From sysc of aeMB2_sysc.v`
76			`wire ena_i; // From sysc of aeMB2_sysc.v`
77			`wire pha_i; // From sysc of aeMB2_sysc.v`
78			`wire [10:0] rALT_IF; // From bpcu of aeMB2_bpcu.v`
79			`wire [2:0] rALU_OF; // From idmx of aeMB2_idmx.v`
80			`wire [1:0] rBRA; // From bpcu of aeMB2_bpcu.v`
81			`wire [15:0] rIMM_IF; // From bpcu of aeMB2_bpcu.v`
82			`wire [15:0] rIMM_OF; // From idmx of aeMB2_idmx.v`
83			`wire rINT; // From sysc of aeMB2_sysc.v`
84			`wire rMSR_BE; // From aslu of aeMB2_aslu.v`
85			`wire rMSR_BIP; // From aslu of aeMB2_aslu.v`
86			`wire rMSR_IE; // From aslu of aeMB2_aslu.v`
87			`wire [31:0] rMUL_MA; // From aslu of aeMB2_aslu.v`
88			`wire [31:0] rOPA_OF; // From opmx of aeMB2_opmx.v`
89			`wire [31:0] rOPB_OF; // From opmx of aeMB2_opmx.v`
90			`wire [5:0] rOPC_IF; // From bpcu of aeMB2_bpcu.v`
91			`wire [5:0] rOPC_OF; // From idmx of aeMB2_idmx.v`
92			`wire [2:0] rOPD_EX; // From idmx of aeMB2_idmx.v`
93			`wire [2:0] rOPD_MA; // From idmx of aeMB2_idmx.v`
94			`wire [31:0] rOPM_OF; // From opmx of aeMB2_opmx.v`
95			`wire [31:0] rOPX_OF; // From opmx of aeMB2_opmx.v`
96			`wire [31:2] rPC_IF; // From bpcu of aeMB2_bpcu.v`
97			`wire [31:2] rPC_MA; // From bpcu of aeMB2_bpcu.v`
98			`wire [31:2] rPC_OF; // From bpcu of aeMB2_bpcu.v`
99			`wire [4:0] rRA_IF; // From bpcu of aeMB2_bpcu.v`
100			`wire [4:0] rRA_OF; // From idmx of aeMB2_idmx.v`
101			`wire [4:0] rRB_IF; // From bpcu of aeMB2_bpcu.v`
102			`wire [4:0] rRD_EX; // From idmx of aeMB2_idmx.v`
103			`wire [4:0] rRD_IF; // From bpcu of aeMB2_bpcu.v`
104			`wire [4:0] rRD_MA; // From idmx of aeMB2_idmx.v`
105			`wire [4:0] rRD_OF; // From idmx of aeMB2_idmx.v`
106			`wire [31:0] rREGA_OF; // From regf of aeMB2_regf.v`
107			`wire [31:0] rREGB_OF; // From regf of aeMB2_regf.v`
108			`wire [31:0] rREGD_OF; // From regf of aeMB2_regf.v`
109			`wire [31:0] rRES_EX; // From aslu of aeMB2_aslu.v`
110			`wire [31:0] rRES_MA; // From aslu of aeMB2_aslu.v`
111			`wire [3:0] rSEL_MA; // From aslu of aeMB2_aslu.v`
112			`wire rXCE; // From sysc of aeMB2_sysc.v`
113			`wire rst_i; // From sysc of aeMB2_sysc.v`
114			`// End of automatics`
115	76	sybreon
116	78	sybreon	`/* aeMB2_sysc AUTO_TEMPLATE (`
117			`.clk_o(clk_i),`
118			`.rst_o(rst_i),`
119			`.ena_o(ena_i),`
120			`.pha_o(pha_i),`
121			`)*/`
122
123			`/* System/Interrupt Control */`
124	76	sybreon
125	78	sybreon	`aeMB2_sysc`
126			`#(/AUTOINSTPARAM/`
127			`// Parameters`
128			`.TXE (TXE))`
129			`sysc (/AUTOINST/`
130			`// Outputs`
131			`.iwb_stb_o (iwb_stb_o),`
132			`.iwb_wre_o (iwb_wre_o),`
133			`.dwb_cyc_o (dwb_cyc_o),`
134			`.dwb_stb_o (dwb_stb_o),`
135			`.dwb_wre_o (dwb_wre_o),`
136			`.cwb_stb_o (cwb_stb_o),`
137			`.cwb_wre_o (cwb_wre_o),`
138			`.rINT (rINT),`
139			`.rXCE (rXCE),`
140			`.pha_o (pha_i), // Templated`
141			`.clk_o (clk_i), // Templated`
142			`.rst_o (rst_i), // Templated`
143			`.ena_o (ena_i), // Templated`
144			`// Inputs`
145			`.rOPC_IF (rOPC_IF[5:0]),`
146			`.iwb_ack_i (iwb_ack_i),`
147			`.dwb_ack_i (dwb_ack_i),`
148			`.cwb_ack_i (cwb_ack_i),`
149			`.rOPC_OF (rOPC_OF[5:0]),`
150			`.rRA_OF (rRA_OF[4:0]),`
151			`.rIMM_OF (rIMM_OF[15:0]),`
152			`.rMSR_BE (rMSR_BE),`
153			`.rMSR_BIP (rMSR_BIP),`
154			`.rMSR_IE (rMSR_IE),`
155			`.sys_int_i (sys_int_i),`
156			`.sys_clk_i (sys_clk_i),`
157			`.sys_rst_i (sys_rst_i));`
158
159			`/* Register file */`
160
161			`aeMB2_regf`
162			`#(/AUTOINSTPARAM/`
163			`// Parameters`
164			`.TXE (TXE))`
165			`regf (/AUTOINST/`
166			`// Outputs`
167			`.dwb_dat_o (dwb_dat_o[31:0]),`
168			`.cwb_dat_o (cwb_dat_o[31:0]),`
169			`.rREGD_OF (rREGD_OF[31:0]),`
170			`.rREGA_OF (rREGA_OF[31:0]),`
171			`.rREGB_OF (rREGB_OF[31:0]),`
172			`// Inputs`
173			`.dwb_dat_i (dwb_dat_i[31:0]),`
174			`.dwb_ack_i (dwb_ack_i),`
175			`.cwb_dat_i (cwb_dat_i[31:0]),`
176			`.cwb_ack_i (cwb_ack_i),`
177			`.rRA_IF (rRA_IF[4:0]),`
178			`.rRB_IF (rRB_IF[4:0]),`
179			`.rRD_IF (rRD_IF[4:0]),`
180			`.rRD_MA (rRD_MA[4:0]),`
181			`.rOPM_OF (rOPM_OF[31:0]),`
182			`.rOPA_OF (rOPA_OF[31:0]),`
183			`.rOPC_OF (rOPC_OF[5:0]),`
184			`.rPC_MA (rPC_MA[31:2]),`
185			`.rMUL_MA (rMUL_MA[31:0]),`
186			`.rRES_MA (rRES_MA[31:0]),`
187			`.rOPD_MA (rOPD_MA[2:0]),`
188			`.rSEL_MA (rSEL_MA[3:0]),`
189			`.clk_i (clk_i),`
190			`.rst_i (rst_i),`
191			`.ena_i (ena_i),`
192			`.pha_i (pha_i));`
193
194			`/* Branch/Programme Counter Unit */`
195	76	sybreon
196	78	sybreon	`aeMB2_bpcu`
197			`#(/AUTOINSTPARAM/`
198			`// Parameters`
199			`.IWB (IWB),`
200			`.TXE (TXE),`
201			`.LUT (LUT))`
202			`bpcu (/AUTOINST/`
203			`// Outputs`
204			`.iwb_adr_o (iwb_adr_o[IWB-1:2]),`
205			`.rPC_OF (rPC_OF[31:2]),`
206			`.rPC_MA (rPC_MA[31:2]),`
207			`.rPC_IF (rPC_IF[31:2]),`
208			`.rIMM_IF (rIMM_IF[15:0]),`
209			`.rALT_IF (rALT_IF[10:0]),`
210			`.rOPC_IF (rOPC_IF[5:0]),`
211			`.rRD_IF (rRD_IF[4:0]),`
212			`.rRA_IF (rRA_IF[4:0]),`
213			`.rRB_IF (rRB_IF[4:0]),`
214			`.rBRA (rBRA[1:0]),`
215			`// Inputs`
216			`.iwb_dat_i (iwb_dat_i[31:0]),`
217			`.iwb_ack_i (iwb_ack_i),`
218			`.rOPX_OF (rOPX_OF[31:0]),`
219			`.rOPC_OF (rOPC_OF[5:0]),`
220			`.rRA_OF (rRA_OF[4:0]),`
221			`.rRD_OF (rRD_OF[4:0]),`
222			`.rRES_EX (rRES_EX[31:0]),`
223			`.rRD_EX (rRD_EX[4:0]),`
224			`.rOPD_EX (rOPD_EX[2:0]),`
225			`.clk_i (clk_i),`
226			`.rst_i (rst_i),`
227			`.ena_i (ena_i),`
228			`.pha_i (pha_i));`
229
230			`/* Operand Fetch Mux */`
231
232			`aeMB2_opmx`
233			`#(/AUTOINSTPARAM/`
234			`// Parameters`
235			`.TXE (TXE),`
236			`.LUT (LUT))`
237			`opmx (/AUTOINST/`
238			`// Outputs`
239			`.rOPM_OF (rOPM_OF[31:0]),`
240			`.rOPX_OF (rOPX_OF[31:0]),`
241			`.rOPA_OF (rOPA_OF[31:0]),`
242			`.rOPB_OF (rOPB_OF[31:0]),`
243			`// Inputs`
244			`.rRES_EX (rRES_EX[31:0]),`
245			`.rRD_EX (rRD_EX[4:0]),`
246			`.rOPD_EX (rOPD_EX[1:0]),`
247			`.rOPC_IF (rOPC_IF[5:0]),`
248			`.rIMM_IF (rIMM_IF[15:0]),`
249			`.rPC_IF (rPC_IF[31:2]),`
250			`.rRD_IF (rRD_IF[4:0]),`
251			`.rRA_IF (rRA_IF[4:0]),`
252			`.rRB_IF (rRB_IF[4:0]),`
253			`.rREGD_OF (rREGD_OF[31:0]),`
254			`.rREGA_OF (rREGA_OF[31:0]),`
255			`.rREGB_OF (rREGB_OF[31:0]),`
256			`.rBRA (rBRA[1:0]),`
257			`.pha_i (pha_i),`
258			`.clk_i (clk_i),`
259			`.rst_i (rst_i),`
260			`.ena_i (ena_i));`
261
262			`/* Instruction Decode Mux */`
263
264			`aeMB2_idmx`
265			`#(/AUTOINSTPARAM/`
266			`// Parameters`
267			`.TXE (TXE),`
268			`.MUL (MUL),`
269			`.BSF (BSF),`
270			`.DIV (DIV),`
271			`.FSL (FSL))`
272			`idmx (/AUTOINST/`
273			`// Outputs`
274			`.rIMM_OF (rIMM_OF[15:0]),`
275			`.rOPC_OF (rOPC_OF[5:0]),`
276			`.rRA_OF (rRA_OF[4:0]),`
277			`.rRD_OF (rRD_OF[4:0]),`
278			`.rRD_EX (rRD_EX[4:0]),`
279			`.rRD_MA (rRD_MA[4:0]),`
280			`.rOPD_EX (rOPD_EX[2:0]),`
281			`.rOPD_MA (rOPD_MA[2:0]),`
282			`.rALU_OF (rALU_OF[2:0]),`
283			`// Inputs`
284			`.rBRA (rBRA[1:0]),`
285			`.rXCE (rXCE),`
286			`.rINT (rINT),`
287			`.rIMM_IF (rIMM_IF[15:0]),`
288			`.rALT_IF (rALT_IF[10:0]),`
289			`.rOPC_IF (rOPC_IF[5:0]),`
290			`.rRA_IF (rRA_IF[4:0]),`
291			`.rRB_IF (rRB_IF[4:0]),`
292			`.rRD_IF (rRD_IF[4:0]),`
293			`.pha_i (pha_i),`
294			`.clk_i (clk_i),`
295			`.rst_i (rst_i),`
296			`.ena_i (ena_i));`
297
298
299			`/* Arithmetic Shift Logic Unit */`
300
301			`aeMB2_aslu`
302			`#(/AUTOINSTPARAM/`
303			`// Parameters`
304			`.DWB (DWB),`
305			`.MUL (MUL),`
306			`.BSF (BSF),`
307			`.FSL (FSL),`
308			`.TXE (TXE),`
309			`.LUT (LUT))`
310			`aslu (/AUTOINST/`
311			`// Outputs`
312			`.dwb_adr_o (dwb_adr_o[DWB-1:2]),`
313			`.dwb_sel_o (dwb_sel_o[3:0]),`
314			`.rSEL_MA (rSEL_MA[3:0]),`
315			`.cwb_adr_o (cwb_adr_o[6:2]),`
316			`.cwb_tga_o (cwb_tga_o[1:0]),`
317			`.cwb_sel_o (cwb_sel_o[3:0]),`
318			`.rMUL_MA (rMUL_MA[31:0]),`
319			`.rRES_MA (rRES_MA[31:0]),`
320			`.rRES_EX (rRES_EX[31:0]),`
321			`.rMSR_IE (rMSR_IE),`
322			`.rMSR_BE (rMSR_BE),`
323			`.rMSR_BIP (rMSR_BIP),`
324			`// Inputs`
325			`.rIMM_OF (rIMM_OF[15:0]),`
326			`.rALU_OF (rALU_OF[2:0]),`
327			`.rOPC_OF (rOPC_OF[5:0]),`
328			`.rRA_OF (rRA_OF[4:0]),`
329			`.rRD_OF (rRD_OF[4:0]),`
330			`.rPC_OF (rPC_OF[31:2]),`
331			`.rOPA_OF (rOPA_OF[31:0]),`
332			`.rOPB_OF (rOPB_OF[31:0]),`
333			`.pha_i (pha_i),`
334			`.clk_i (clk_i),`
335			`.rst_i (rst_i),`
336			`.ena_i (ena_i));`
337
338			`// synopsys translate_off`
339			`ifdef AEMB2_SIMULATION_KERNEL
340			`wire [31:0] iwb_adr = {iwb_adr_o, 2'd0};`
341			`wire [31:0] dwb_adr = {dwb_adr_o, 2'd0};`
342			`wire [3:0] wMSR = dut.aslu.wMSR[3:0];`
343
344			`always @(posedge clk_i) if (ena_i) begin`
345
346			`$write ("\n", ($stime/10));`
347			`$writeh (" T", pha_i);`
348			`$writeh(" PC=", iwb_adr);`
349
350			`$writeh ("\t\| ");`
351
352			`case (rOPC_IF)`
353			`6'o00: if (rRD_IF == 0) $write(" "); else $write("ADD");`
354			`6'o01: $write("RSUB");`
355			`6'o02: $write("ADDC");`
356			`6'o03: $write("RSUBC");`
357			`6'o04: $write("ADDK");`
358			`6'o05: case (rIMM_IF[1:0])`
359			`2'o0: $write("RSUBK");`
360			`2'o1: $write("CMP");`
361			`2'o3: $write("CMPU");`
362			`default: $write("XXX");`
363			`endcase // case (rIMM_IF[1:0])`
364			`6'o06: $write("ADDKC");`
365			`6'o07: $write("RSUBKC");`
366
367			`6'o10: $write("ADDI");`
368			`6'o11: $write("RSUBI");`
369			`6'o12: $write("ADDIC");`
370			`6'o13: $write("RSUBIC");`
371			`6'o14: $write("ADDIK");`
372			`6'o15: $write("RSUBIK");`
373			`6'o16: $write("ADDIKC");`
374			`6'o17: $write("RSUBIKC");`
375
376			`6'o20: $write("MUL");`
377			`6'o21: case (rALT_IF[10:9])`
378			`2'o0: $write("BSRL");`
379			`2'o1: $write("BSRA");`
380			`2'o2: $write("BSLL");`
381			`default: $write("XXX");`
382			`endcase // case (rALT_IF[10:9])`
383			`6'o22: $write("IDIV");`
384
385			`6'o30: $write("MULI");`
386			`6'o31: case (rALT_IF[10:9])`
387			`2'o0: $write("BSRLI");`
388			`2'o1: $write("BSRAI");`
389			`2'o2: $write("BSLLI");`
390			`default: $write("XXX");`
391			`endcase // case (rALT_IF[10:9])`
392			`6'o33: case (rRB_IF[4:2])`
393			`3'o0: $write("GET");`
394			`3'o4: $write("PUT");`
395			`3'o2: $write("NGET");`
396			`3'o6: $write("NPUT");`
397			`3'o1: $write("CGET");`
398			`3'o5: $write("CPUT");`
399			`3'o3: $write("NCGET");`
400			`3'o7: $write("NCPUT");`
401			`endcase // case (rRB_IF[4:2])`
402
403			`6'o40: $write("OR");`
404			`6'o41: $write("AND");`
405			`6'o42: if (rRD_IF == 0) $write(" "); else $write("XOR");`
406			`6'o43: $write("ANDN");`
407			`6'o44: case (rIMM_IF[6:5])`
408			`2'o0: $write("SRA");`
409			`2'o1: $write("SRC");`
410			`2'o2: $write("SRL");`
411			`2'o3: if (rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");`
412			`endcase // case (rIMM_IF[6:5])`
413
414			`6'o45: $write("MOV");`
415			`6'o46: case (rRA_IF[3:2])`
416			`3'o0: $write("BR");`
417			`3'o1: $write("BRL");`
418			`3'o2: $write("BRA");`
419			`3'o3: $write("BRAL");`
420			`endcase // case (rRA_IF[3:2])`
421
422			`6'o47: case (rRD_IF[2:0])`
423			`3'o0: $write("BEQ");`
424			`3'o1: $write("BNE");`
425			`3'o2: $write("BLT");`
426			`3'o3: $write("BLE");`
427			`3'o4: $write("BGT");`
428			`3'o5: $write("BGE");`
429			`default: $write("XXX");`
430			`endcase // case (rRD_IF[2:0])`
431
432			`6'o50: $write("ORI");`
433			`6'o51: $write("ANDI");`
434			`6'o52: $write("XORI");`
435			`6'o53: $write("ANDNI");`
436			`6'o54: $write("IMMI");`
437			`6'o55: case (rRD_IF[1:0])`
438			`2'o0: $write("RTSD");`
439			`2'o1: $write("RTID");`
440			`2'o2: $write("RTBD");`
441			`default: $write("XXX");`
442			`endcase // case (rRD_IF[1:0])`
443			`6'o56: case (rRA_IF[3:2])`
444			`3'o0: $write("BRI");`
445			`3'o1: $write("BRLI");`
446			`3'o2: $write("BRAI");`
447			`3'o3: $write("BRALI");`
448			`endcase // case (rRA_IF[3:2])`
449			`6'o57: case (rRD_IF[2:0])`
450			`3'o0: $write("BEQI");`
451			`3'o1: $write("BNEI");`
452			`3'o2: $write("BLTI");`
453			`3'o3: $write("BLEI");`
454			`3'o4: $write("BGTI");`
455			`3'o5: $write("BGEI");`
456			`default: $write("XXX");`
457			`endcase // case (rRD_IF[2:0])`
458
459			`6'o60: $write("LBU");`
460			`6'o61: $write("LHU");`
461			`6'o62: $write("LW");`
462			`6'o64: $write("SB");`
463			`6'o65: $write("SH");`
464			`6'o66: $write("SW");`
465
466			`6'o70: $write("LBUI");`
467			`6'o71: $write("LHUI");`
468			`6'o72: $write("LWI");`
469			`6'o74: $write("SBI");`
470			`6'o75: $write("SHI");`
471			`6'o76: $write("SWI");`
472
473			`default: $write("XXX");`
474			`endcase // case (rOPC_IF)`
475
476			`case (rOPC_IF[3])`
477			`1'b1: $writeh("\t r",rRD_IF,", r",rRA_IF,", h",rIMM_IF);`
478			`1'b0: $writeh("\t r",rRD_IF,", r",rRA_IF,", r",rRB_IF," ");`
479			`endcase // case (rOPC_IF[3])`
480
481			`if (dut.bpcu.fHAZARD)`
482			`$write ("*");`
483
484			`// ALU`
485			`$write("\t\|");`
486			`$writeh(" A=",rOPA_OF);`
487			`$writeh(" B=",rOPB_OF);`
488			`$writeh(" C=",rOPX_OF);`
489			`$writeh(" M=",rOPM_OF);`
490
491			`$writeh(" MSR=", wMSR," ");`
492
493			`case (rALU_OF)`
494			`3'o0: if (dwb_stb_o)`
495			`$write(" RAM");`
496			`else`
497			`$write(" ADD");`
498			`3'o1: $write(" LOG");`
499			`3'o2: $write(" SFT");`
500			`3'o3: $write(" MOV");`
501			`3'o4: $write(" MUL");`
502			`3'o5: $write(" BSF");`
503			`default: $write(" XXX");`
504			`endcase // case (rALU_OF)`
505
506			`// MA`
507			`$write ("\t\| ");`
508			`if (dwb_stb_o)`
509			`$writeh("@",rRES_EX);`
510			`else`
511			`$writeh("=",rRES_EX);`
512
513
514			`case (rBRA)`
515			`2'b00: $write(" ");`
516			`2'b01: $write(".");`
517			`2'b10: $write("-");`
518			`2'b11: $write("+");`
519			`endcase // case (rBRA)`
520
521			`// WRITEBACK`
522			`$write("\t\|");`
523
524			`if (regf.fWRE) begin`
525			`case (rOPD_MA)`
526			`2'o2: begin`
527			`if (rSEL_MA != 4'h0) $writeh("R",rRD_MA,"=RAM(",regf.rREGD,")");`
528			`if (rSEL_MA == 4'h0) $writeh("R",rRD_MA,"=FSL(",regf.rREGD,")");`
529			`end`
530			`2'o1: $writeh("R",rRD_MA,"=LNK(",regf.rREGD,")");`
531			`2'o0: $writeh("R",rRD_MA,"=ALU(",regf.rREGD,")");`
532			`endcase // case (rOPD_MA)`
533			`end`
534
535			`/*`
536			`// STORE`
537			`if (dwb_stb_o & dwb_wre_o) begin`
538			`$writeh("RAM(", dwb_adr ,")=", dwb_dat_o);`
539			`case (dwb_sel_o)`
540			`4'hF: $write(":L");`
541			`4'h3,4'hC: $write(":W");`
542			`4'h1,4'h2,4'h4,4'h8: $write(":B");`
543			`endcase // case (dwb_sel_o)`
544
545			`end`
546			`*/`
547			`end // if (ena_i)`
548
549			`endif // `ifdef AEMB_SIMULATION_KERNEL
550			`// synopsys translate_on`
551
552
553	76	sybreon	`endmodule // aeMB2_edk32`
554
555	78	sybreon	`/* $Log: not supported by cvs2svn $`
556			`/* Revision 1.1 2007/12/07 18:58:51 sybreon`
557			`/* initial`
558			`/* */`