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/* $Id: aeMB2_edk32.v,v 1.6 2007-12-16 03:25:22 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aeMB2_edk32 (/*AUTOARG*/
   // Outputs
   iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
   dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
   cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
   dwb_ack_i, cwb_dat_i, cwb_ack_i
   );
   parameter IWB = 32; // instruction wishbone address space
   parameter DWB = 32; // data wishbone address space
 
   parameter TXE = 1; // thread execution extension
 
   parameter MUL = 1; // enable multiply instruction
   parameter BSF = 1; // enable barrel shift instructions
   parameter FSL = 1; // enable get/put instructions
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [6:2]         cwb_adr_o;              // From aslu of aeMB2_aslu.v
   output [31:0] cwb_dat_o;              // From regf of aeMB2_regf.v
   output [3:0]          cwb_sel_o;              // From aslu of aeMB2_aslu.v
   output               cwb_stb_o;              // From sysc of aeMB2_sysc.v
   output [1:0]          cwb_tga_o;              // From aslu of aeMB2_aslu.v
   output               cwb_wre_o;              // From sysc of aeMB2_sysc.v
   output [DWB-1:2]     dwb_adr_o;              // From aslu of aeMB2_aslu.v
   output               dwb_cyc_o;              // From sysc of aeMB2_sysc.v
   output [31:0] dwb_dat_o;              // From regf of aeMB2_regf.v
   output [3:0]          dwb_sel_o;              // From aslu of aeMB2_aslu.v
   output               dwb_stb_o;              // From sysc of aeMB2_sysc.v
   output               dwb_tga_o;              // From aslu of aeMB2_aslu.v
   output               dwb_wre_o;              // From sysc of aeMB2_sysc.v
   output [IWB-1:2]     iwb_adr_o;              // From bpcu of aeMB2_bpcu.v
   output               iwb_stb_o;              // From sysc of aeMB2_sysc.v
   output               iwb_tga_o;              // From aslu of aeMB2_aslu.v
   output               iwb_wre_o;              // From sysc of aeMB2_sysc.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                cwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          cwb_dat_i;              // To regf of aeMB2_regf.v
   input                dwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          dwb_dat_i;              // To regf of aeMB2_regf.v
   input                iwb_ack_i;              // To sysc of aeMB2_sysc.v, ...
   input [31:0]          iwb_dat_i;              // To bpcu of aeMB2_bpcu.v
   input                sys_clk_i;              // To sysc of aeMB2_sysc.v
   input                sys_int_i;              // To sysc of aeMB2_sysc.v
   input                sys_rst_i;              // To sysc of aeMB2_sysc.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 clk_i;                  // From sysc of aeMB2_sysc.v
   wire                 ena_i;                  // From sysc of aeMB2_sysc.v
   wire                 pha_i;                  // From sysc of aeMB2_sysc.v
   wire [10:0]           rALT_IF;                // From bpcu of aeMB2_bpcu.v
   wire [2:0]            rALU_OF;                // From ofid of aeMB2_ofid.v
   wire [1:0]            rBRA;                   // From bpcu of aeMB2_bpcu.v
   wire [15:0]           rIMM_IF;                // From bpcu of aeMB2_bpcu.v
   wire [15:0]           rIMM_OF;                // From ofid of aeMB2_ofid.v
   wire                 rINT;                   // From sysc of aeMB2_sysc.v
   wire                 rMSR_BE;                // From aslu of aeMB2_aslu.v
   wire                 rMSR_BIP;               // From aslu of aeMB2_aslu.v
   wire                 rMSR_IE;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rMUL_MA;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rOPA_OF;                // From ofid of aeMB2_ofid.v
   wire [31:0]           rOPB_OF;                // From ofid of aeMB2_ofid.v
   wire [5:0]            rOPC_IF;                // From bpcu of aeMB2_bpcu.v
   wire [5:0]            rOPC_OF;                // From ofid of aeMB2_ofid.v
   wire [2:0]            rOPD_EX;                // From ofid of aeMB2_ofid.v
   wire [2:0]            rOPD_MA;                // From ofid of aeMB2_ofid.v
   wire [31:0]           rOPM_OF;                // From ofid of aeMB2_ofid.v
   wire [31:0]           rOPX_OF;                // From ofid of aeMB2_ofid.v
   wire [31:2]          rPC_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [31:2]          rPC_MA;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRA_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRA_OF;                 // From ofid of aeMB2_ofid.v
   wire [4:0]            rRB_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRD_EX;                 // From ofid of aeMB2_ofid.v
   wire [4:0]            rRD_IF;                 // From bpcu of aeMB2_bpcu.v
   wire [4:0]            rRD_MA;                 // From ofid of aeMB2_ofid.v
   wire [4:0]            rRD_OF;                 // From ofid of aeMB2_ofid.v
   wire [31:0]           rREGA_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rREGB_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rREGD_OF;               // From regf of aeMB2_regf.v
   wire [31:0]           rRES_EX;                // From aslu of aeMB2_aslu.v
   wire [31:0]           rRES_MA;                // From aslu of aeMB2_aslu.v
   wire [3:0]            rSEL_MA;                // From aslu of aeMB2_aslu.v
   wire                 rXCE;                   // From sysc of aeMB2_sysc.v
   wire                 rst_i;                  // From sysc of aeMB2_sysc.v
   // End of automatics
 
   /* aeMB2_sysc AUTO_TEMPLATE (
    .clk_o(clk_i),
    .rst_o(rst_i),
    .ena_o(ena_i),
    .pha_o(pha_i),
    )*/
 
   /* System/Interrupt Control */
 
   aeMB2_sysc
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE),
       .FSL                             (FSL))
   sysc (/*AUTOINST*/
         // Outputs
         .rINT                          (rINT),
         .rXCE                          (rXCE),
         .pha_o                         (pha_i),                 // Templated
         .clk_o                         (clk_i),                 // Templated
         .rst_o                         (rst_i),                 // Templated
         .ena_o                         (ena_i),                 // Templated
         .iwb_stb_o                     (iwb_stb_o),
         .iwb_wre_o                     (iwb_wre_o),
         .dwb_cyc_o                     (dwb_cyc_o),
         .dwb_stb_o                     (dwb_stb_o),
         .dwb_wre_o                     (dwb_wre_o),
         .cwb_stb_o                     (cwb_stb_o),
         .cwb_wre_o                     (cwb_wre_o),
         // Inputs
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rMSR_BE                       (rMSR_BE),
         .rMSR_BIP                      (rMSR_BIP),
         .rMSR_IE                       (rMSR_IE),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .iwb_ack_i                     (iwb_ack_i),
         .dwb_ack_i                     (dwb_ack_i),
         .cwb_ack_i                     (cwb_ack_i),
         .sys_int_i                     (sys_int_i),
         .sys_clk_i                     (sys_clk_i),
         .sys_rst_i                     (sys_rst_i));
 
   /* Register file */
 
   aeMB2_regf
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE),
       .MUL                             (MUL))
   regf (/*AUTOINST*/
         // Outputs
         .dwb_dat_o                     (dwb_dat_o[31:0]),
         .cwb_dat_o                     (cwb_dat_o[31:0]),
         .rREGD_OF                      (rREGD_OF[31:0]),
         .rREGA_OF                      (rREGA_OF[31:0]),
         .rREGB_OF                      (rREGB_OF[31:0]),
         // Inputs
         .dwb_dat_i                     (dwb_dat_i[31:0]),
         .dwb_ack_i                     (dwb_ack_i),
         .cwb_dat_i                     (cwb_dat_i[31:0]),
         .cwb_ack_i                     (cwb_ack_i),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .rRD_MA                        (rRD_MA[4:0]),
         .rOPM_OF                       (rOPM_OF[31:0]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rPC_MA                        (rPC_MA[31:2]),
         .rMUL_MA                       (rMUL_MA[31:0]),
         .rRES_MA                       (rRES_MA[31:0]),
         .rOPD_MA                       (rOPD_MA[2:0]),
         .rSEL_MA                       (rSEL_MA[3:0]),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i),
         .pha_i                         (pha_i));
 
   /* Branch/Programme Counter Unit */
 
   aeMB2_bpcu
     #(/*AUTOINSTPARAM*/
       // Parameters
       .IWB                             (IWB),
       .TXE                             (TXE))
   bpcu (/*AUTOINST*/
         // Outputs
         .iwb_adr_o                     (iwb_adr_o[IWB-1:2]),
         .rPC_MA                        (rPC_MA[31:2]),
         .rPC_IF                        (rPC_IF[31:2]),
         .rIMM_IF                       (rIMM_IF[15:0]),
         .rALT_IF                       (rALT_IF[10:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rBRA                          (rBRA[1:0]),
         // Inputs
         .iwb_dat_i                     (iwb_dat_i[31:0]),
         .iwb_ack_i                     (iwb_ack_i),
         .rOPX_OF                       (rOPX_OF[31:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rRES_EX                       (rRES_EX[31:0]),
         .rRD_EX                        (rRD_EX[4:0]),
         .rOPD_EX                       (rOPD_EX[2:0]),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i),
         .pha_i                         (pha_i));
 
   /* Operand Fetch Mux */
 
   aeMB2_ofid
     #(/*AUTOINSTPARAM*/
       // Parameters
       .TXE                             (TXE),
       .MUL                             (MUL),
       .BSF                             (BSF),
       .FSL                             (FSL))
   ofid (/*AUTOINST*/
         // Outputs
         .rOPM_OF                       (rOPM_OF[31:0]),
         .rOPX_OF                       (rOPX_OF[31:0]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPB_OF                       (rOPB_OF[31:0]),
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rRD_EX                        (rRD_EX[4:0]),
         .rRD_MA                        (rRD_MA[4:0]),
         .rOPD_EX                       (rOPD_EX[2:0]),
         .rOPD_MA                       (rOPD_MA[2:0]),
         .rALU_OF                       (rALU_OF[2:0]),
         // Inputs
         .rRES_EX                       (rRES_EX[31:0]),
         .rREGD_OF                      (rREGD_OF[31:0]),
         .rREGA_OF                      (rREGA_OF[31:0]),
         .rREGB_OF                      (rREGB_OF[31:0]),
         .rBRA                          (rBRA[1:0]),
         .rXCE                          (rXCE),
         .rINT                          (rINT),
         .rPC_IF                        (rPC_IF[31:2]),
         .rIMM_IF                       (rIMM_IF[15:0]),
         .rALT_IF                       (rALT_IF[10:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rRA_IF                        (rRA_IF[4:0]),
         .rRB_IF                        (rRB_IF[4:0]),
         .rRD_IF                        (rRD_IF[4:0]),
         .pha_i                         (pha_i),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i));
 
 
   /* Arithmetic Shift Logic Unit */
 
   aeMB2_aslu
     #(/*AUTOINSTPARAM*/
       // Parameters
       .DWB                             (DWB),
       .TXE                             (TXE),
       .MUL                             (MUL),
       .BSF                             (BSF),
       .FSL                             (FSL))
   aslu (/*AUTOINST*/
         // Outputs
         .dwb_adr_o                     (dwb_adr_o[DWB-1:2]),
         .dwb_sel_o                     (dwb_sel_o[3:0]),
         .rSEL_MA                       (rSEL_MA[3:0]),
         .cwb_adr_o                     (cwb_adr_o[6:2]),
         .cwb_tga_o                     (cwb_tga_o[1:0]),
         .cwb_sel_o                     (cwb_sel_o[3:0]),
         .iwb_tga_o                     (iwb_tga_o),
         .dwb_tga_o                     (dwb_tga_o),
         .rMUL_MA                       (rMUL_MA[31:0]),
         .rRES_MA                       (rRES_MA[31:0]),
         .rRES_EX                       (rRES_EX[31:0]),
         .rMSR_IE                       (rMSR_IE),
         .rMSR_BE                       (rMSR_BE),
         .rMSR_BIP                      (rMSR_BIP),
         // Inputs
         .rIMM_OF                       (rIMM_OF[15:0]),
         .rALU_OF                       (rALU_OF[2:0]),
         .rOPC_OF                       (rOPC_OF[5:0]),
         .rOPC_IF                       (rOPC_IF[5:0]),
         .rRA_OF                        (rRA_OF[4:0]),
         .rRD_OF                        (rRD_OF[4:0]),
         .rOPA_OF                       (rOPA_OF[31:0]),
         .rOPB_OF                       (rOPB_OF[31:0]),
         .pha_i                         (pha_i),
         .clk_i                         (clk_i),
         .rst_i                         (rst_i),
         .ena_i                         (ena_i));
 
   // synopsys translate_off
   wire [31:0]           iwb_adr = {iwb_adr_o, 2'd0};
   wire [31:0]           dwb_adr = {dwb_adr_o, 2'd0};
   wire [31:0]           wMSR = aslu.wMSR[31:0];
 
   always @(posedge clk_i) if (ena_i) begin
 
      $write ("\n", ($stime/10));
      $writeh (" T", pha_i);
      $writeh(" PC=", iwb_adr);
 
      $writeh ("\t| ");
 
      case (rOPC_IF)
        6'o00: if (rRD_IF == 0) $write("   "); else $write("ADD");
        6'o01: $write("SUB");
        6'o02: $write("ADDC");
        6'o03: $write("SUBC");
        6'o04: $write("ADDK");
        6'o05: case (rIMM_IF[1:0])
                 2'o0: $write("SUBK");
                 2'o1: $write("CMP");
                 2'o3: $write("CMPU");
                 default: $write("XXX");
               endcase // case (rIMM_IF[1:0])
        6'o06: $write("ADDKC");
        6'o07: $write("SUBKC");
 
        6'o10: $write("ADDI");
        6'o11: $write("SUBI");
        6'o12: $write("ADDIC");
        6'o13: $write("SUBIC");
        6'o14: $write("ADDIK");
        6'o15: $write("SUBIK");
        6'o16: $write("ADDIKC");
        6'o17: $write("SUBIKC");
 
        6'o20: $write("MUL");
        6'o21: case (rALT_IF[10:9])
                 2'o0: $write("BSRL");
                 2'o1: $write("BSRA");
                 2'o2: $write("BSLL");
                 default: $write("XXX");
               endcase // case (rALT_IF[10:9])
        6'o22: $write("IDIV");
 
        6'o30: $write("MULI");
        6'o31: case (rALT_IF[10:9])
                 2'o0: $write("BSRLI");
                 2'o1: $write("BSRAI");
                 2'o2: $write("BSLLI");
                 default: $write("XXX");
               endcase // case (rALT_IF[10:9])
        6'o33: case (rRB_IF[4:2])
                 3'o0: $write("GET");
                 3'o4: $write("PUT");
                 3'o2: $write("NGET");
                 3'o6: $write("NPUT");
                 3'o1: $write("CGET");
                 3'o5: $write("CPUT");
                 3'o3: $write("NCGET");
                 3'o7: $write("NCPUT");
               endcase // case (rRB_IF[4:2])
 
        6'o40: $write("OR");
        6'o41: $write("AND");
        6'o42: if (rRD_IF == 0) $write("   "); else $write("XOR");
        6'o43: $write("ANDN");
        6'o44: case (rIMM_IF[6:5])
                 2'o0: $write("SRA");
                 2'o1: $write("SRC");
                 2'o2: $write("SRL");
                 2'o3: if (rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
               endcase // case (rIMM_IF[6:5])
 
        6'o45: $write("MOV");
        6'o46: case (rRA_IF[3:2])
                 3'o0: $write("BR");
                 3'o1: $write("BRL");
                 3'o2: $write("BRA");
                 3'o3: $write("BRAL");
               endcase // case (rRA_IF[3:2])
 
        6'o47: case (rRD_IF[2:0])
                 3'o0: $write("BEQ");
                 3'o1: $write("BNE");
                 3'o2: $write("BLT");
                 3'o3: $write("BLE");
                 3'o4: $write("BGT");
                 3'o5: $write("BGE");
                 default: $write("XXX");
               endcase // case (rRD_IF[2:0])
 
        6'o50: $write("ORI");
        6'o51: $write("ANDI");
        6'o52: $write("XORI");
        6'o53: $write("ANDNI");
        6'o54: $write("IMMI");
        6'o55: case (rRD_IF[1:0])
                 2'o0: $write("RTSD");
                 2'o1: $write("RTID");
                 2'o2: $write("RTBD");
                 default: $write("XXX");
               endcase // case (rRD_IF[1:0])
        6'o56: case (rRA_IF[3:2])
                 3'o0: $write("BRI");
                 3'o1: $write("BRLI");
                 3'o2: $write("BRAI");
                 3'o3: $write("BRALI");
               endcase // case (rRA_IF[3:2])
        6'o57: case (rRD_IF[2:0])
                 3'o0: $write("BEQI");
                 3'o1: $write("BNEI");
                 3'o2: $write("BLTI");
                 3'o3: $write("BLEI");
                 3'o4: $write("BGTI");
                 3'o5: $write("BGEI");
                 default: $write("XXX");
               endcase // case (rRD_IF[2:0])
 
        6'o60: $write("LBU");
        6'o61: $write("LHU");
        6'o62: $write("LW");
        6'o64: $write("SB");
        6'o65: $write("SH");
        6'o66: $write("SW");
 
        6'o70: $write("LBUI");
        6'o71: $write("LHUI");
        6'o72: $write("LWI");
        6'o74: $write("SBI");
        6'o75: $write("SHI");
        6'o76: $write("SWI");
 
        default: $write("XXX");
      endcase // case (rOPC_IF)
 
      case (rOPC_IF[3])
        1'b1: $writeh("\t r",rRD_IF,", r",rRA_IF,", h",rIMM_IF);
        1'b0: $writeh("\t r",rRD_IF,", r",rRA_IF,", r",rRB_IF,"  ");
      endcase // case (rOPC_IF[3])
 
      if (bpcu.fHZD)
        $write ("*");
 
      // ALU
      $write("\t|");
      $writeh(" A=",rOPA_OF);
      $writeh(" B=",rOPB_OF);
      $writeh(" C=",rOPX_OF);
      $writeh(" M=",rOPM_OF);
 
      $writeh(" MSR=", wMSR," ");
 
      case (rALU_OF)
        3'o0: if (dwb_stb_o)
          $write(" RAM");
        else
          $write(" ADD");
        3'o1: $write(" LOG");
        3'o2: $write(" SFT");
        3'o3: $write(" MOV");
        3'o4: $write(" MUL");
        3'o5: $write(" BSF");
        default: $write(" XXX");
      endcase // case (rALU_OF)
 
      // MA
      $write ("\t| ");
      if (dwb_stb_o)
        $writeh("@",rRES_EX);
      else
        $writeh("=",rRES_EX);
 
 
      case (rBRA)
        2'b00: $write(" ");
        2'b01: $write(".");
        2'b10: $write("-");
        2'b11: $write("+");
      endcase // case (rBRA)
 
      // WRITEBACK
      $write("\t|");
 
      if (|rRD_MA) begin
         case (rOPD_MA)
           2'o2: begin
              if (rSEL_MA != 4'h0) $writeh("R",rRD_MA,"=RAM(",regf.rREGD,")");
              if (rSEL_MA == 4'h0) $writeh("R",rRD_MA,"=FSL(",regf.rREGD,")");
           end
           2'o1: $writeh("R",rRD_MA,"=LNK(",regf.rREGD,")");
           2'o0: $writeh("R",rRD_MA,"=ALU(",regf.rREGD,")");
         endcase // case (rOPD_MA)
      end
 
      /*
      // STORE
      if (dwb_stb_o & dwb_wre_o) begin
         $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
         case (dwb_sel_o)
           4'hF: $write(":L");
           4'h3,4'hC: $write(":W");
           4'h1,4'h2,4'h4,4'h8: $write(":B");
         endcase // case (dwb_sel_o)
 
      end
       */
   end // if (ena_i)
 
   // synopsys translate_on
 
endmodule // aeMB2_edk32
 
/* $Log: not supported by cvs2svn $
/* Revision 1.5  2007/12/13 21:25:41  sybreon
/* Further optimisations (speed + size).
/*
/* Revision 1.4  2007/12/13 20:12:11  sybreon
/* Code cleanup + minor speed regression.
/*
/* Revision 1.3  2007/12/12 19:16:59  sybreon
/* Minor optimisations (~10% faster)
/*
/* Revision 1.2  2007/12/11 00:43:17  sybreon
/* initial import
/*
/* Revision 1.1  2007/12/07 18:58:51  sybreon
/* initial
/* */

Line No.	Rev	Author	Line
1	85	sybreon	`/* $Id: aeMB2_edk32.v,v 1.6 2007-12-16 03:25:22 sybreon Exp $`
2	76	sybreon	`**`
3			`** AEMB2 HI-PERFORMANCE CPU`
4			`**`
5			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`**`
7			`** This file is part of AEMB.`
8			`**`
9			`** AEMB is free software: you can redistribute it and/or modify it`
10			`** under the terms of the GNU Lesser General Public License as`
11			`** published by the Free Software Foundation, either version 3 of the`
12			`** License, or (at your option) any later version.`
13			`**`
14			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20	78	sybreon	`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	76	sybreon	`*/`
22
23	78	sybreon	`module aeMB2_edk32 (/AUTOARG/`
24			`// Outputs`
25	81	sybreon	`iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,`
26			`dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,`
27			`cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,`
28	78	sybreon	`// Inputs`
29			`sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,`
30			`dwb_ack_i, cwb_dat_i, cwb_ack_i`
31			`);`
32	82	sybreon	`parameter IWB = 32; // instruction wishbone address space`
33			`parameter DWB = 32; // data wishbone address space`
34	78	sybreon
35	82	sybreon	`parameter TXE = 1; // thread execution extension`
36	78	sybreon
37	82	sybreon	`parameter MUL = 1; // enable multiply instruction`
38			`parameter BSF = 1; // enable barrel shift instructions`
39			`parameter FSL = 1; // enable get/put instructions`
40	78	sybreon
41			`/AUTOOUTPUT/`
42			`// Beginning of automatic outputs (from unused autoinst outputs)`
43			`output [6:2] cwb_adr_o; // From aslu of aeMB2_aslu.v`
44			`output [31:0] cwb_dat_o; // From regf of aeMB2_regf.v`
45			`output [3:0] cwb_sel_o; // From aslu of aeMB2_aslu.v`
46			`output cwb_stb_o; // From sysc of aeMB2_sysc.v`
47			`output [1:0] cwb_tga_o; // From aslu of aeMB2_aslu.v`
48			`output cwb_wre_o; // From sysc of aeMB2_sysc.v`
49			`output [DWB-1:2] dwb_adr_o; // From aslu of aeMB2_aslu.v`
50			`output dwb_cyc_o; // From sysc of aeMB2_sysc.v`
51			`output [31:0] dwb_dat_o; // From regf of aeMB2_regf.v`
52			`output [3:0] dwb_sel_o; // From aslu of aeMB2_aslu.v`
53			`output dwb_stb_o; // From sysc of aeMB2_sysc.v`
54	81	sybreon	`output dwb_tga_o; // From aslu of aeMB2_aslu.v`
55	78	sybreon	`output dwb_wre_o; // From sysc of aeMB2_sysc.v`
56			`output [IWB-1:2] iwb_adr_o; // From bpcu of aeMB2_bpcu.v`
57			`output iwb_stb_o; // From sysc of aeMB2_sysc.v`
58	81	sybreon	`output iwb_tga_o; // From aslu of aeMB2_aslu.v`
59	78	sybreon	`output iwb_wre_o; // From sysc of aeMB2_sysc.v`
60			`// End of automatics`
61			`/AUTOINPUT/`
62			`// Beginning of automatic inputs (from unused autoinst inputs)`
63			`input cwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
64			`input [31:0] cwb_dat_i; // To regf of aeMB2_regf.v`
65			`input dwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
66			`input [31:0] dwb_dat_i; // To regf of aeMB2_regf.v`
67			`input iwb_ack_i; // To sysc of aeMB2_sysc.v, ...`
68			`input [31:0] iwb_dat_i; // To bpcu of aeMB2_bpcu.v`
69			`input sys_clk_i; // To sysc of aeMB2_sysc.v`
70			`input sys_int_i; // To sysc of aeMB2_sysc.v`
71			`input sys_rst_i; // To sysc of aeMB2_sysc.v`
72			`// End of automatics`
73			`/AUTOWIRE/`
74			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
75			`wire clk_i; // From sysc of aeMB2_sysc.v`
76			`wire ena_i; // From sysc of aeMB2_sysc.v`
77			`wire pha_i; // From sysc of aeMB2_sysc.v`
78			`wire [10:0] rALT_IF; // From bpcu of aeMB2_bpcu.v`
79	85	sybreon	`wire [2:0] rALU_OF; // From ofid of aeMB2_ofid.v`
80	78	sybreon	`wire [1:0] rBRA; // From bpcu of aeMB2_bpcu.v`
81			`wire [15:0] rIMM_IF; // From bpcu of aeMB2_bpcu.v`
82	85	sybreon	`wire [15:0] rIMM_OF; // From ofid of aeMB2_ofid.v`
83	78	sybreon	`wire rINT; // From sysc of aeMB2_sysc.v`
84			`wire rMSR_BE; // From aslu of aeMB2_aslu.v`
85			`wire rMSR_BIP; // From aslu of aeMB2_aslu.v`
86			`wire rMSR_IE; // From aslu of aeMB2_aslu.v`
87			`wire [31:0] rMUL_MA; // From aslu of aeMB2_aslu.v`
88	85	sybreon	`wire [31:0] rOPA_OF; // From ofid of aeMB2_ofid.v`
89			`wire [31:0] rOPB_OF; // From ofid of aeMB2_ofid.v`
90	78	sybreon	`wire [5:0] rOPC_IF; // From bpcu of aeMB2_bpcu.v`
91	85	sybreon	`wire [5:0] rOPC_OF; // From ofid of aeMB2_ofid.v`
92			`wire [2:0] rOPD_EX; // From ofid of aeMB2_ofid.v`
93			`wire [2:0] rOPD_MA; // From ofid of aeMB2_ofid.v`
94			`wire [31:0] rOPM_OF; // From ofid of aeMB2_ofid.v`
95			`wire [31:0] rOPX_OF; // From ofid of aeMB2_ofid.v`
96	78	sybreon	`wire [31:2] rPC_IF; // From bpcu of aeMB2_bpcu.v`
97			`wire [31:2] rPC_MA; // From bpcu of aeMB2_bpcu.v`
98			`wire [4:0] rRA_IF; // From bpcu of aeMB2_bpcu.v`
99	85	sybreon	`wire [4:0] rRA_OF; // From ofid of aeMB2_ofid.v`
100	78	sybreon	`wire [4:0] rRB_IF; // From bpcu of aeMB2_bpcu.v`
101	85	sybreon	`wire [4:0] rRD_EX; // From ofid of aeMB2_ofid.v`
102	78	sybreon	`wire [4:0] rRD_IF; // From bpcu of aeMB2_bpcu.v`
103	85	sybreon	`wire [4:0] rRD_MA; // From ofid of aeMB2_ofid.v`
104			`wire [4:0] rRD_OF; // From ofid of aeMB2_ofid.v`
105	78	sybreon	`wire [31:0] rREGA_OF; // From regf of aeMB2_regf.v`
106			`wire [31:0] rREGB_OF; // From regf of aeMB2_regf.v`
107			`wire [31:0] rREGD_OF; // From regf of aeMB2_regf.v`
108			`wire [31:0] rRES_EX; // From aslu of aeMB2_aslu.v`
109			`wire [31:0] rRES_MA; // From aslu of aeMB2_aslu.v`
110			`wire [3:0] rSEL_MA; // From aslu of aeMB2_aslu.v`
111			`wire rXCE; // From sysc of aeMB2_sysc.v`
112			`wire rst_i; // From sysc of aeMB2_sysc.v`
113			`// End of automatics`
114	76	sybreon
115	78	sybreon	`/* aeMB2_sysc AUTO_TEMPLATE (`
116			`.clk_o(clk_i),`
117			`.rst_o(rst_i),`
118			`.ena_o(ena_i),`
119			`.pha_o(pha_i),`
120			`)*/`
121
122			`/* System/Interrupt Control */`
123	76	sybreon
124	78	sybreon	`aeMB2_sysc`
125			`#(/AUTOINSTPARAM/`
126			`// Parameters`
127	80	sybreon	`.TXE (TXE),`
128			`.FSL (FSL))`
129	78	sybreon	`sysc (/AUTOINST/`
130			`// Outputs`
131	81	sybreon	`.rINT (rINT),`
132			`.rXCE (rXCE),`
133			`.pha_o (pha_i), // Templated`
134			`.clk_o (clk_i), // Templated`
135			`.rst_o (rst_i), // Templated`
136			`.ena_o (ena_i), // Templated`
137	78	sybreon	`.iwb_stb_o (iwb_stb_o),`
138			`.iwb_wre_o (iwb_wre_o),`
139			`.dwb_cyc_o (dwb_cyc_o),`
140			`.dwb_stb_o (dwb_stb_o),`
141			`.dwb_wre_o (dwb_wre_o),`
142			`.cwb_stb_o (cwb_stb_o),`
143			`.cwb_wre_o (cwb_wre_o),`
144			`// Inputs`
145	80	sybreon	`.rIMM_OF (rIMM_OF[15:0]),`
146	78	sybreon	`.rOPC_OF (rOPC_OF[5:0]),`
147			`.rRA_OF (rRA_OF[4:0]),`
148			`.rMSR_BE (rMSR_BE),`
149			`.rMSR_BIP (rMSR_BIP),`
150			`.rMSR_IE (rMSR_IE),`
151	81	sybreon	`.rOPC_IF (rOPC_IF[5:0]),`
152			`.iwb_ack_i (iwb_ack_i),`
153			`.dwb_ack_i (dwb_ack_i),`
154			`.cwb_ack_i (cwb_ack_i),`
155	78	sybreon	`.sys_int_i (sys_int_i),`
156			`.sys_clk_i (sys_clk_i),`
157			`.sys_rst_i (sys_rst_i));`
158
159			`/* Register file */`
160
161			`aeMB2_regf`
162			`#(/AUTOINSTPARAM/`
163			`// Parameters`
164	81	sybreon	`.TXE (TXE),`
165			`.MUL (MUL))`
166	78	sybreon	`regf (/AUTOINST/`
167			`// Outputs`
168			`.dwb_dat_o (dwb_dat_o[31:0]),`
169			`.cwb_dat_o (cwb_dat_o[31:0]),`
170			`.rREGD_OF (rREGD_OF[31:0]),`
171			`.rREGA_OF (rREGA_OF[31:0]),`
172			`.rREGB_OF (rREGB_OF[31:0]),`
173			`// Inputs`
174			`.dwb_dat_i (dwb_dat_i[31:0]),`
175			`.dwb_ack_i (dwb_ack_i),`
176			`.cwb_dat_i (cwb_dat_i[31:0]),`
177			`.cwb_ack_i (cwb_ack_i),`
178			`.rRA_IF (rRA_IF[4:0]),`
179			`.rRB_IF (rRB_IF[4:0]),`
180			`.rRD_IF (rRD_IF[4:0]),`
181			`.rRD_MA (rRD_MA[4:0]),`
182			`.rOPM_OF (rOPM_OF[31:0]),`
183			`.rOPA_OF (rOPA_OF[31:0]),`
184			`.rOPC_OF (rOPC_OF[5:0]),`
185			`.rPC_MA (rPC_MA[31:2]),`
186			`.rMUL_MA (rMUL_MA[31:0]),`
187			`.rRES_MA (rRES_MA[31:0]),`
188			`.rOPD_MA (rOPD_MA[2:0]),`
189			`.rSEL_MA (rSEL_MA[3:0]),`
190			`.clk_i (clk_i),`
191			`.rst_i (rst_i),`
192			`.ena_i (ena_i),`
193			`.pha_i (pha_i));`
194
195			`/* Branch/Programme Counter Unit */`
196	76	sybreon
197	78	sybreon	`aeMB2_bpcu`
198			`#(/AUTOINSTPARAM/`
199			`// Parameters`
200			`.IWB (IWB),`
201	80	sybreon	`.TXE (TXE))`
202	78	sybreon	`bpcu (/AUTOINST/`
203			`// Outputs`
204			`.iwb_adr_o (iwb_adr_o[IWB-1:2]),`
205			`.rPC_MA (rPC_MA[31:2]),`
206			`.rPC_IF (rPC_IF[31:2]),`
207			`.rIMM_IF (rIMM_IF[15:0]),`
208			`.rALT_IF (rALT_IF[10:0]),`
209			`.rOPC_IF (rOPC_IF[5:0]),`
210			`.rRD_IF (rRD_IF[4:0]),`
211			`.rRA_IF (rRA_IF[4:0]),`
212			`.rRB_IF (rRB_IF[4:0]),`
213			`.rBRA (rBRA[1:0]),`
214			`// Inputs`
215			`.iwb_dat_i (iwb_dat_i[31:0]),`
216			`.iwb_ack_i (iwb_ack_i),`
217			`.rOPX_OF (rOPX_OF[31:0]),`
218			`.rOPC_OF (rOPC_OF[5:0]),`
219			`.rRA_OF (rRA_OF[4:0]),`
220			`.rRD_OF (rRD_OF[4:0]),`
221			`.rRES_EX (rRES_EX[31:0]),`
222			`.rRD_EX (rRD_EX[4:0]),`
223			`.rOPD_EX (rOPD_EX[2:0]),`
224			`.clk_i (clk_i),`
225			`.rst_i (rst_i),`
226			`.ena_i (ena_i),`
227			`.pha_i (pha_i));`
228
229			`/* Operand Fetch Mux */`
230
231	85	sybreon	`aeMB2_ofid`
232	78	sybreon	`#(/AUTOINSTPARAM/`
233			`// Parameters`
234	85	sybreon	`.TXE (TXE),`
235			`.MUL (MUL),`
236			`.BSF (BSF),`
237			`.FSL (FSL))`
238			`ofid (/AUTOINST/`
239	78	sybreon	`// Outputs`
240			`.rOPM_OF (rOPM_OF[31:0]),`
241			`.rOPX_OF (rOPX_OF[31:0]),`
242			`.rOPA_OF (rOPA_OF[31:0]),`
243			`.rOPB_OF (rOPB_OF[31:0]),`
244			`.rIMM_OF (rIMM_OF[15:0]),`
245			`.rOPC_OF (rOPC_OF[5:0]),`
246			`.rRA_OF (rRA_OF[4:0]),`
247			`.rRD_OF (rRD_OF[4:0]),`
248			`.rRD_EX (rRD_EX[4:0]),`
249			`.rRD_MA (rRD_MA[4:0]),`
250			`.rOPD_EX (rOPD_EX[2:0]),`
251			`.rOPD_MA (rOPD_MA[2:0]),`
252			`.rALU_OF (rALU_OF[2:0]),`
253			`// Inputs`
254	85	sybreon	`.rRES_EX (rRES_EX[31:0]),`
255			`.rREGD_OF (rREGD_OF[31:0]),`
256			`.rREGA_OF (rREGA_OF[31:0]),`
257			`.rREGB_OF (rREGB_OF[31:0]),`
258	78	sybreon	`.rBRA (rBRA[1:0]),`
259			`.rXCE (rXCE),`
260			`.rINT (rINT),`
261	85	sybreon	`.rPC_IF (rPC_IF[31:2]),`
262	78	sybreon	`.rIMM_IF (rIMM_IF[15:0]),`
263			`.rALT_IF (rALT_IF[10:0]),`
264			`.rOPC_IF (rOPC_IF[5:0]),`
265			`.rRA_IF (rRA_IF[4:0]),`
266			`.rRB_IF (rRB_IF[4:0]),`
267			`.rRD_IF (rRD_IF[4:0]),`
268			`.pha_i (pha_i),`
269			`.clk_i (clk_i),`
270			`.rst_i (rst_i),`
271	85	sybreon	`.ena_i (ena_i));`
272
273
274	78	sybreon	`/* Arithmetic Shift Logic Unit */`
275
276			`aeMB2_aslu`
277			`#(/AUTOINSTPARAM/`
278			`// Parameters`
279			`.DWB (DWB),`
280	80	sybreon	`.TXE (TXE),`
281	78	sybreon	`.MUL (MUL),`
282			`.BSF (BSF),`
283	80	sybreon	`.FSL (FSL))`
284	78	sybreon	`aslu (/AUTOINST/`
285			`// Outputs`
286			`.dwb_adr_o (dwb_adr_o[DWB-1:2]),`
287			`.dwb_sel_o (dwb_sel_o[3:0]),`
288			`.rSEL_MA (rSEL_MA[3:0]),`
289			`.cwb_adr_o (cwb_adr_o[6:2]),`
290			`.cwb_tga_o (cwb_tga_o[1:0]),`
291			`.cwb_sel_o (cwb_sel_o[3:0]),`
292	81	sybreon	`.iwb_tga_o (iwb_tga_o),`
293			`.dwb_tga_o (dwb_tga_o),`
294	78	sybreon	`.rMUL_MA (rMUL_MA[31:0]),`
295			`.rRES_MA (rRES_MA[31:0]),`
296			`.rRES_EX (rRES_EX[31:0]),`
297			`.rMSR_IE (rMSR_IE),`
298			`.rMSR_BE (rMSR_BE),`
299			`.rMSR_BIP (rMSR_BIP),`
300			`// Inputs`
301			`.rIMM_OF (rIMM_OF[15:0]),`
302			`.rALU_OF (rALU_OF[2:0]),`
303			`.rOPC_OF (rOPC_OF[5:0]),`
304	80	sybreon	`.rOPC_IF (rOPC_IF[5:0]),`
305	78	sybreon	`.rRA_OF (rRA_OF[4:0]),`
306			`.rRD_OF (rRD_OF[4:0]),`
307			`.rOPA_OF (rOPA_OF[31:0]),`
308			`.rOPB_OF (rOPB_OF[31:0]),`
309			`.pha_i (pha_i),`
310			`.clk_i (clk_i),`
311			`.rst_i (rst_i),`
312			`.ena_i (ena_i));`
313	80	sybreon
314	78	sybreon	`// synopsys translate_off`
315			`wire [31:0] iwb_adr = {iwb_adr_o, 2'd0};`
316			`wire [31:0] dwb_adr = {dwb_adr_o, 2'd0};`
317	81	sybreon	`wire [31:0] wMSR = aslu.wMSR[31:0];`
318	78	sybreon
319			`always @(posedge clk_i) if (ena_i) begin`
320
321			`$write ("\n", ($stime/10));`
322			`$writeh (" T", pha_i);`
323			`$writeh(" PC=", iwb_adr);`
324
325			`$writeh ("\t\| ");`
326
327			`case (rOPC_IF)`
328			`6'o00: if (rRD_IF == 0) $write(" "); else $write("ADD");`
329	85	sybreon	`6'o01: $write("SUB");`
330	78	sybreon	`6'o02: $write("ADDC");`
331	85	sybreon	`6'o03: $write("SUBC");`
332	78	sybreon	`6'o04: $write("ADDK");`
333			`6'o05: case (rIMM_IF[1:0])`
334	85	sybreon	`2'o0: $write("SUBK");`
335	78	sybreon	`2'o1: $write("CMP");`
336			`2'o3: $write("CMPU");`
337			`default: $write("XXX");`
338			`endcase // case (rIMM_IF[1:0])`
339			`6'o06: $write("ADDKC");`
340	85	sybreon	`6'o07: $write("SUBKC");`
341	78	sybreon
342			`6'o10: $write("ADDI");`
343	85	sybreon	`6'o11: $write("SUBI");`
344	78	sybreon	`6'o12: $write("ADDIC");`
345	85	sybreon	`6'o13: $write("SUBIC");`
346	78	sybreon	`6'o14: $write("ADDIK");`
347	85	sybreon	`6'o15: $write("SUBIK");`
348	78	sybreon	`6'o16: $write("ADDIKC");`
349	85	sybreon	`6'o17: $write("SUBIKC");`
350	78	sybreon
351			`6'o20: $write("MUL");`
352			`6'o21: case (rALT_IF[10:9])`
353			`2'o0: $write("BSRL");`
354			`2'o1: $write("BSRA");`
355			`2'o2: $write("BSLL");`
356			`default: $write("XXX");`
357			`endcase // case (rALT_IF[10:9])`
358			`6'o22: $write("IDIV");`
359
360			`6'o30: $write("MULI");`
361			`6'o31: case (rALT_IF[10:9])`
362			`2'o0: $write("BSRLI");`
363			`2'o1: $write("BSRAI");`
364			`2'o2: $write("BSLLI");`
365			`default: $write("XXX");`
366			`endcase // case (rALT_IF[10:9])`
367			`6'o33: case (rRB_IF[4:2])`
368			`3'o0: $write("GET");`
369			`3'o4: $write("PUT");`
370			`3'o2: $write("NGET");`
371			`3'o6: $write("NPUT");`
372			`3'o1: $write("CGET");`
373			`3'o5: $write("CPUT");`
374			`3'o3: $write("NCGET");`
375			`3'o7: $write("NCPUT");`
376			`endcase // case (rRB_IF[4:2])`
377
378			`6'o40: $write("OR");`
379			`6'o41: $write("AND");`
380			`6'o42: if (rRD_IF == 0) $write(" "); else $write("XOR");`
381			`6'o43: $write("ANDN");`
382			`6'o44: case (rIMM_IF[6:5])`
383			`2'o0: $write("SRA");`
384			`2'o1: $write("SRC");`
385			`2'o2: $write("SRL");`
386			`2'o3: if (rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");`
387			`endcase // case (rIMM_IF[6:5])`
388
389			`6'o45: $write("MOV");`
390			`6'o46: case (rRA_IF[3:2])`
391			`3'o0: $write("BR");`
392			`3'o1: $write("BRL");`
393			`3'o2: $write("BRA");`
394			`3'o3: $write("BRAL");`
395			`endcase // case (rRA_IF[3:2])`
396
397			`6'o47: case (rRD_IF[2:0])`
398			`3'o0: $write("BEQ");`
399			`3'o1: $write("BNE");`
400			`3'o2: $write("BLT");`
401			`3'o3: $write("BLE");`
402			`3'o4: $write("BGT");`
403			`3'o5: $write("BGE");`
404			`default: $write("XXX");`
405			`endcase // case (rRD_IF[2:0])`
406
407			`6'o50: $write("ORI");`
408			`6'o51: $write("ANDI");`
409			`6'o52: $write("XORI");`
410			`6'o53: $write("ANDNI");`
411			`6'o54: $write("IMMI");`
412			`6'o55: case (rRD_IF[1:0])`
413			`2'o0: $write("RTSD");`
414			`2'o1: $write("RTID");`
415			`2'o2: $write("RTBD");`
416			`default: $write("XXX");`
417			`endcase // case (rRD_IF[1:0])`
418			`6'o56: case (rRA_IF[3:2])`
419			`3'o0: $write("BRI");`
420			`3'o1: $write("BRLI");`
421			`3'o2: $write("BRAI");`
422			`3'o3: $write("BRALI");`
423			`endcase // case (rRA_IF[3:2])`
424			`6'o57: case (rRD_IF[2:0])`
425			`3'o0: $write("BEQI");`
426			`3'o1: $write("BNEI");`
427			`3'o2: $write("BLTI");`
428			`3'o3: $write("BLEI");`
429			`3'o4: $write("BGTI");`
430			`3'o5: $write("BGEI");`
431			`default: $write("XXX");`
432			`endcase // case (rRD_IF[2:0])`
433
434			`6'o60: $write("LBU");`
435			`6'o61: $write("LHU");`
436			`6'o62: $write("LW");`
437			`6'o64: $write("SB");`
438			`6'o65: $write("SH");`
439			`6'o66: $write("SW");`
440
441			`6'o70: $write("LBUI");`
442			`6'o71: $write("LHUI");`
443			`6'o72: $write("LWI");`
444			`6'o74: $write("SBI");`
445			`6'o75: $write("SHI");`
446			`6'o76: $write("SWI");`
447
448			`default: $write("XXX");`
449			`endcase // case (rOPC_IF)`
450
451			`case (rOPC_IF[3])`
452			`1'b1: $writeh("\t r",rRD_IF,", r",rRA_IF,", h",rIMM_IF);`
453			`1'b0: $writeh("\t r",rRD_IF,", r",rRA_IF,", r",rRB_IF," ");`
454			`endcase // case (rOPC_IF[3])`
455
456	81	sybreon	`if (bpcu.fHZD)`
457	78	sybreon	`$write ("*");`
458
459			`// ALU`
460			`$write("\t\|");`
461			`$writeh(" A=",rOPA_OF);`
462			`$writeh(" B=",rOPB_OF);`
463			`$writeh(" C=",rOPX_OF);`
464			`$writeh(" M=",rOPM_OF);`
465
466			`$writeh(" MSR=", wMSR," ");`
467
468			`case (rALU_OF)`
469			`3'o0: if (dwb_stb_o)`
470			`$write(" RAM");`
471			`else`
472			`$write(" ADD");`
473			`3'o1: $write(" LOG");`
474			`3'o2: $write(" SFT");`
475			`3'o3: $write(" MOV");`
476			`3'o4: $write(" MUL");`
477			`3'o5: $write(" BSF");`
478			`default: $write(" XXX");`
479			`endcase // case (rALU_OF)`
480
481			`// MA`
482			`$write ("\t\| ");`
483			`if (dwb_stb_o)`
484			`$writeh("@",rRES_EX);`
485			`else`
486			`$writeh("=",rRES_EX);`
487
488
489			`case (rBRA)`
490			`2'b00: $write(" ");`
491			`2'b01: $write(".");`
492			`2'b10: $write("-");`
493			`2'b11: $write("+");`
494			`endcase // case (rBRA)`
495
496			`// WRITEBACK`
497			`$write("\t\|");`
498
499	82	sybreon	`if (\|rRD_MA) begin`
500	78	sybreon	`case (rOPD_MA)`

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