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/* $Id: aeMB2_idmx.v,v 1.5 2007-12-16 03:25:02 sybreon Exp $
**
** AEMB2 INSTRUCTION DECODE MUX
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aeMB2_idmx (/*AUTOARG*/
   // Outputs
   rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,
   rALU_OF,
   // Inputs
   rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,
   rRD_IF, pha_i, clk_i, rst_i, ena_i
   );
   parameter TXE = 1;
 
   parameter MUL = 1;
   parameter BSF = 1;
   parameter FSL = 1;
 
   output [15:0] rIMM_OF;
   output [5:0]  rOPC_OF;
   output [4:0]  rRA_OF,
                 rRD_OF;
 
   output [4:0]  rRD_EX,
                 rRD_MA;
   output [2:0]  rOPD_EX,
                 rOPD_MA;
 
   output [2:0]  rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst
 
 
   input [1:0]    rBRA;
   input         rXCE,
                 //rMSR_TXE,
                 rINT;
 
   input [15:0]  rIMM_IF;
   input [10:0]  rALT_IF;
   input [5:0]    rOPC_IF;
   input [4:0]    rRA_IF,
                 rRB_IF,
                 rRD_IF;
 
   input         pha_i,
                 clk_i,
                 rst_i,
                 ena_i;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [2:0]             rALU_OF;
   reg [15:0]            rIMM_OF;
   reg [5:0]             rOPC_OF;
   reg [2:0]             rOPD_EX;
   reg [2:0]             rOPD_MA;
   reg [4:0]             rRA_OF;
   reg [4:0]             rRD_EX;
   reg [4:0]             rRD_MA;
   reg [4:0]             rRD_OF;
   // End of automatics
 
   //wire [31:0]                wXCEOP = 32'hBA2D0020; // Vector 0x20
   wire [31:0]           wINTOP = 32'hB9CE0010; // Vector 0x10   
   wire [31:0]           wNOPOP = 32'h88000000; // branch-no-delay/stall
 
   /* Partial decoding */
   wire [5:0]            rOPC = rOPC_IF;
   wire [4:0]            rRA = rRA_IF;
   wire [4:0]            rRB = rRB_IF;
   wire                 fSFT = (rOPC == 6'o44);
   wire                 fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
   wire                 fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire                 fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire                 fDIV = (rOPC == 6'o22);
   wire                 fRTD = (rOPC == 6'o55);
   wire                 fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire                 fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire                 fBRA = fBRU & rRA[3];
   wire                 fIMM = (rOPC == 6'o54);
   wire                 fMOV = (rOPC == 6'o45);
   wire                 fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire                 fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire                 fLDST = (rOPC[5:4] == 2'o3);
   wire                 fPUT = (rOPC == 6'o33) & rRB[4];
   wire                 fGET = (rOPC == 6'o33) & !rRB[4];
 
   /* Hazard detection */
 
   wire                 fLOAD = (rOPD_EX == 3'o2);
   wire                 fMULT = (rOPD_EX == 3'o3);
   wire                 fWRE = |rRD_EX;
   wire                 fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
   wire                 fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
   wire                 fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
   wire                 fHAZARD = fOPBHZD | fOPAHZD | fOPDHZD;
 
   wire                 fSKIP = (rBRA == 2'o2) | // non-delay branch
                        !(TXE | pha_i) |
                        fOPBHZD | fOPAHZD; // hazards
 
   /*
    PARTIAL IMMI
 
    Replicated from OPMX and used for checking atomicity for
    interrupts. */
 
   reg                  rFIM0, rFIM1, rFIML[0:1];
   wire                 rFIM = (pha_i) ? rFIM0 : rFIM1;
   wire                 fSKP = rBRA == 2'b10;
   wire                 fINT = !rFIM & !rBRA[1] & rINT & pha_i;
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFIM0 <= 1'h0;
        rFIM1 <= 1'h0;
        // End of automatics
     end else if (ena_i) begin
        if (pha_i)
          rFIM0 <= #1 fIMM & !fSKP;
        else
          rFIM1 <= #1 fIMM & !fSKP;
     end
 
 
 
   /* ALU Selector */
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rALU_OF <= 3'h0;
        // End of automatics
     end else if (ena_i) begin
        /*
        rALU_OF <= #1
                   (fSKIP) ? 3'o1 : // NOP
                   (fBRA | fMOV) ? 3'o3 :
                   (fSFT) ? 3'o2 :
                   (fLOG) ? 3'o1 :
                   (fMUL) ? 3'o4 :
                   (fBSF) ? 3'o5 :
                   3'o0;
         */
        rALU_OF <= #1
                   (fSKIP) ? 3'o2 : // NOP
                   (fBRA | fMOV) ? 3'o2 :
                   (fSFT) ? 3'o2 :
                   (fLOG) ? 3'o2 :
                   (fBSF) ? 3'o1 :
                   3'o0;
     end // if (ena_i)
 
   /* WB Selector */
 
   reg [2:0] rOPD_OF;
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rOPD_EX <= 3'h0;
        rOPD_MA <= 3'h0;
        rOPD_OF <= 3'h0;
        // End of automatics
     end else if (ena_i) begin
        rOPD_MA <= #1 rOPD_EX;
        rOPD_EX <= #1 rOPD_OF;
        rOPD_OF <= #1
                   (fSKIP) ? 3'o7: // NOP
                   (fSTR | fRTD | fBCC) ? 3'o7 : // STR/RTD/BCC            
                   (fLOD | fGET) ? 3'o2 : // RAM/FSL
                   (fBRU) ? 3'o1 : // PCLNK
                   (fMUL) ? 3'o3 : // MUL
                   (|rRD_IF) ? 3'o0 : // ALU
                   3'o7; // NOP
     end // if (ena_i)
 
 
 
   // The only non atomic instruction is IMMI. All other instructions
   // are atomic. No interception allowed for branching.
 
   /*
    INTERCEPTION
 
    Instructions are either pass-thru or intercepted here. */
 
   always @(posedge clk_i)
     if (rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rIMM_OF <= 16'h0;
        rOPC_OF <= 6'h0;
        rRA_OF <= 5'h0;
        rRD_EX <= 5'h0;
        rRD_MA <= 5'h0;
        rRD_OF <= 5'h0;
        // End of automatics
     end else if (ena_i) begin // if (rst_i)
        rRD_MA <= #1 rRD_EX;
        rRD_EX <= #1 rRD_OF;
 
        // TODO: Interrrupt
        case ({fINT, fSKIP})
          2'o0: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 {rOPC_IF, rRD_IF, rRA_IF, rIMM_IF};
          2'o1: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wNOPOP; // delay/stall
          2'o3,
          2'o2: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wINTOP; // interrupt
          default: {rOPC_OF, rRD_OF, rRA_OF} <= #1 16'hX;
        endcase // case (fSKIP)
 
     end // if (ena_i)
 
endmodule // aeMB2_idmx
 
/* $Log: not supported by cvs2svn $
/* Revision 1.4  2007/12/13 21:25:41  sybreon
/* Further optimisations (speed + size).
/*
/* Revision 1.3  2007/12/13 20:12:11  sybreon
/* Code cleanup + minor speed regression.
/*
/* Revision 1.2  2007/12/12 19:16:59  sybreon
/* Minor optimisations (~10% faster)
/*
/* Revision 1.1  2007/12/11 00:43:17  sybreon
/* initial import
/* */

Line No.	Rev	Author	Line
1	84	sybreon	`/* $Id: aeMB2_idmx.v,v 1.5 2007-12-16 03:25:02 sybreon Exp $`
2	78	sybreon	`**`
3			`** AEMB2 INSTRUCTION DECODE MUX`
4			`**`
5			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`**`
7			`** This file is part of AEMB.`
8			`**`
9			`** AEMB is free software: you can redistribute it and/or modify it`
10			`** under the terms of the GNU Lesser General Public License as`
11			`** published by the Free Software Foundation, either version 3 of the`
12			`** License, or (at your option) any later version.`
13			`**`
14			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21			`*/`
22
23			`module aeMB2_idmx (/AUTOARG/`
24			`// Outputs`
25			`rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,`
26			`rALU_OF,`
27			`// Inputs`
28			`rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,`
29	81	sybreon	`rRD_IF, pha_i, clk_i, rst_i, ena_i`
30	78	sybreon	`);`
31			`parameter TXE = 1;`
32
33			`parameter MUL = 1;`
34			`parameter BSF = 1;`
35			`parameter FSL = 1;`
36
37			`output [15:0] rIMM_OF;`
38			`output [5:0] rOPC_OF;`
39			`output [4:0] rRA_OF,`
40			`rRD_OF;`
41
42			`output [4:0] rRD_EX,`
43			`rRD_MA;`
44			`output [2:0] rOPD_EX,`
45			`rOPD_MA;`
46
47			`output [2:0] rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst`
48
49
50			`input [1:0] rBRA;`
51			`input rXCE,`
52	81	sybreon	`//rMSR_TXE,`
53	78	sybreon	`rINT;`
54
55			`input [15:0] rIMM_IF;`
56			`input [10:0] rALT_IF;`
57			`input [5:0] rOPC_IF;`
58			`input [4:0] rRA_IF,`
59			`rRB_IF,`
60			`rRD_IF;`
61
62			`input pha_i,`
63			`clk_i,`
64			`rst_i,`
65			`ena_i;`
66
67			`/AUTOREG/`
68			`// Beginning of automatic regs (for this module's undeclared outputs)`
69			`reg [2:0] rALU_OF;`
70			`reg [15:0] rIMM_OF;`
71			`reg [5:0] rOPC_OF;`
72			`reg [2:0] rOPD_EX;`
73			`reg [2:0] rOPD_MA;`
74			`reg [4:0] rRA_OF;`
75			`reg [4:0] rRD_EX;`
76			`reg [4:0] rRD_MA;`
77			`reg [4:0] rRD_OF;`
78			`// End of automatics`
79
80	80	sybreon	`//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20`
81			`wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10`
82	78	sybreon	`wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall`
83
84			`/* Partial decoding */`
85			`wire [5:0] rOPC = rOPC_IF;`
86			`wire [4:0] rRA = rRA_IF;`
87			`wire [4:0] rRB = rRB_IF;`
88			`wire fSFT = (rOPC == 6'o44);`
89			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
90			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
91			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
92			`wire fDIV = (rOPC == 6'o22);`
93			`wire fRTD = (rOPC == 6'o55);`
94			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
95			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
96			`wire fBRA = fBRU & rRA[3];`
97			`wire fIMM = (rOPC == 6'o54);`
98			`wire fMOV = (rOPC == 6'o45);`
99			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
100			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
101			`wire fLDST = (rOPC[5:4] == 2'o3);`
102			`wire fPUT = (rOPC == 6'o33) & rRB[4];`
103			`wire fGET = (rOPC == 6'o33) & !rRB[4];`
104
105			`/* Hazard detection */`
106
107			`wire fLOAD = (rOPD_EX == 3'o2);`
108			`wire fMULT = (rOPD_EX == 3'o3);`
109			`wire fWRE = \|rRD_EX;`
110			`wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD \| fMULT) & !fMOV & !rOPC_IF[3] & fWRE;`
111			`wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD \| fMULT) & !fBRU & fWRE;`
112			`wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD \| fMULT) & fSTR & fWRE;`
113			`wire fHAZARD = fOPBHZD \| fOPAHZD \| fOPDHZD;`
114
115			`wire fSKIP = (rBRA == 2'o2) \| // non-delay branch`
116	81	sybreon	`!(TXE \| pha_i) \|`
117	78	sybreon	`fOPBHZD \| fOPAHZD; // hazards`
118
119	84	sybreon	`/*`
120			`PARTIAL IMMI`
121
122			`Replicated from OPMX and used for checking atomicity for`
123			`interrupts. */`
124
125			`reg rFIM0, rFIM1, rFIML[0:1];`
126			`wire rFIM = (pha_i) ? rFIM0 : rFIM1;`
127			`wire fSKP = rBRA == 2'b10;`
128			`wire fINT = !rFIM & !rBRA[1] & rINT & pha_i;`
129
130			`always @(posedge clk_i)`
131			`if (rst_i) begin`
132			`/AUTORESET/`
133			`// Beginning of autoreset for uninitialized flops`
134			`rFIM0 <= 1'h0;`
135			`rFIM1 <= 1'h0;`
136			`// End of automatics`
137			`end else if (ena_i) begin`
138			`if (pha_i)`
139			`rFIM0 <= #1 fIMM & !fSKP;`
140			`else`
141			`rFIM1 <= #1 fIMM & !fSKP;`
142			`end`
143
144
145
146	78	sybreon	`/* ALU Selector */`
147
148			`always @(posedge clk_i)`
149			`if (rst_i) begin`
150			`/AUTORESET/`
151			`// Beginning of autoreset for uninitialized flops`
152			`rALU_OF <= 3'h0;`
153			`// End of automatics`
154			`end else if (ena_i) begin`
155	82	sybreon	`/*`
156	78	sybreon	`rALU_OF <= #1`
157	80	sybreon	`(fSKIP) ? 3'o1 : // NOP`
158	78	sybreon	`(fBRA \| fMOV) ? 3'o3 :`
159			`(fSFT) ? 3'o2 :`
160			`(fLOG) ? 3'o1 :`
161			`(fMUL) ? 3'o4 :`
162			`(fBSF) ? 3'o5 :`
163			`3'o0;`
164	82	sybreon	`*/`
165			`rALU_OF <= #1`
166	84	sybreon	`(fSKIP) ? 3'o2 : // NOP`
167			`(fBRA \| fMOV) ? 3'o2 :`
168			`(fSFT) ? 3'o2 :`
169			`(fLOG) ? 3'o2 :`
170			`(fBSF) ? 3'o1 :`
171	82	sybreon	`3'o0;`
172	84	sybreon	`end // if (ena_i)`
173	78	sybreon
174			`/* WB Selector */`
175
176			`reg [2:0] rOPD_OF;`
177
178			`always @(posedge clk_i)`
179			`if (rst_i) begin`
180			`/AUTORESET/`
181			`// Beginning of autoreset for uninitialized flops`
182			`rOPD_EX <= 3'h0;`
183			`rOPD_MA <= 3'h0;`
184			`rOPD_OF <= 3'h0;`
185			`// End of automatics`
186			`end else if (ena_i) begin`
187			`rOPD_MA <= #1 rOPD_EX;`
188			`rOPD_EX <= #1 rOPD_OF;`
189			`rOPD_OF <= #1`
190	80	sybreon	`(fSKIP) ? 3'o7: // NOP`
191			`(fSTR \| fRTD \| fBCC) ? 3'o7 : // STR/RTD/BCC`
192	78	sybreon	`(fLOD \| fGET) ? 3'o2 : // RAM/FSL`
193			`(fBRU) ? 3'o1 : // PCLNK`
194			`(fMUL) ? 3'o3 : // MUL`
195			`(\|rRD_IF) ? 3'o0 : // ALU`
196	82	sybreon	`3'o7; // NOP`
197	80	sybreon	`end // if (ena_i)`
198	78	sybreon
199	84	sybreon
200
201			`// The only non atomic instruction is IMMI. All other instructions`
202			`// are atomic. No interception allowed for branching.`
203
204			`/*`
205			`INTERCEPTION`
206
207			`Instructions are either pass-thru or intercepted here. */`
208
209	78	sybreon	`always @(posedge clk_i)`
210			`if (rst_i) begin`
211			`/AUTORESET/`
212			`// Beginning of autoreset for uninitialized flops`
213			`rIMM_OF <= 16'h0;`
214			`rOPC_OF <= 6'h0;`
215			`rRA_OF <= 5'h0;`
216			`rRD_EX <= 5'h0;`
217			`rRD_MA <= 5'h0;`
218			`rRD_OF <= 5'h0;`
219			`// End of automatics`
220	80	sybreon	`end else if (ena_i) begin // if (rst_i)`
221	78	sybreon	`rRD_MA <= #1 rRD_EX;`
222			`rRD_EX <= #1 rRD_OF;`
223
224	80	sybreon	`// TODO: Interrrupt`
225	84	sybreon	`case ({fINT, fSKIP})`
226	78	sybreon	`2'o0: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 {rOPC_IF, rRD_IF, rRA_IF, rIMM_IF};`
227			`2'o1: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wNOPOP; // delay/stall`
228	84	sybreon	`2'o3,`
229			`2'o2: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wINTOP; // interrupt`
230	78	sybreon	`default: {rOPC_OF, rRD_OF, rRA_OF} <= #1 16'hX;`
231			`endcase // case (fSKIP)`
232
233	80	sybreon	`end // if (ena_i)`
234	78	sybreon
235			`endmodule // aeMB2_idmx`
236
237	80	sybreon	`/* $Log: not supported by cvs2svn $`
238	84	sybreon	`/* Revision 1.4 2007/12/13 21:25:41 sybreon`
239			`/* Further optimisations (speed + size).`
240			`/*`
241	82	sybreon	`/* Revision 1.3 2007/12/13 20:12:11 sybreon`
242			`/* Code cleanup + minor speed regression.`
243			`/*`
244	81	sybreon	`/* Revision 1.2 2007/12/12 19:16:59 sybreon`
245			`/* Minor optimisations (~10% faster)`
246			`/*`
247	80	sybreon	`/* Revision 1.1 2007/12/11 00:43:17 sybreon`
248			`/* initial import`
249			`/* */`

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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB2_idmx.v] - Blame information for rev 193