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1 92 sybreon 
/* $Id: aeMB2_sim.v,v 1.1 2007-12-18 18:54:36 sybreon Exp $
2 
**
3 
** AEMB2 SIMULATION WRAPPER
4 
**
5 
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
6 
**
7 
** This file is part of AEMB.
8 
**
9 
** AEMB is free software: you can redistribute it and/or modify it
10 
** under the terms of the GNU Lesser General Public License as
11 
** published by the Free Software Foundation, either version 3 of the
12 
** License, or (at your option) any later version.
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**
14 
** AEMB is distributed in the hope that it will be useful, but WITHOUT
15 
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
17 
** Public License for more details.
18 
**
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** You should have received a copy of the GNU Lesser General Public
20 
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
21 
*/
22 
 
23 
module aeMB2_sim (/*AUTOARG*/
24 
   // Outputs
25 
   iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
26 
   dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
27 
   cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
28 
   // Inputs
29 
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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   dwb_ack_i, cwb_dat_i, cwb_ack_i
31 
   );
32 
 
33 
   parameter IWB=16;
34 
   parameter DWB=16;
35 
 
36 
   parameter TXE = 1; ///< thread execution enable
37 
 
38 
   parameter MUL = 1; ///< enable hardware multiplier
39 
   parameter BSF = 1; ///< enable barrel shifter
40 
   parameter FSL = 1; ///< enable FSL bus
41 
   parameter DIV = 0; ///< enable hardware divider
42 
 
43 
   /*AUTOOUTPUT*/
44 
   // Beginning of automatic outputs (from unused autoinst outputs)
45 
   output [6:2]         cwb_adr_o;              // From cpu of aeMB2_edk32.v
46 
   output [31:0] cwb_dat_o;              // From cpu of aeMB2_edk32.v
47 
   output [3:0]          cwb_sel_o;              // From cpu of aeMB2_edk32.v
48 
   output               cwb_stb_o;              // From cpu of aeMB2_edk32.v
49 
   output [1:0]          cwb_tga_o;              // From cpu of aeMB2_edk32.v
50 
   output               cwb_wre_o;              // From cpu of aeMB2_edk32.v
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   output [DWB-1:2]     dwb_adr_o;              // From cpu of aeMB2_edk32.v
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   output               dwb_cyc_o;              // From cpu of aeMB2_edk32.v
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   output [31:0] dwb_dat_o;              // From cpu of aeMB2_edk32.v
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   output [3:0]          dwb_sel_o;              // From cpu of aeMB2_edk32.v
55 
   output               dwb_stb_o;              // From cpu of aeMB2_edk32.v
56 
   output               dwb_tga_o;              // From cpu of aeMB2_edk32.v
57 
   output               dwb_wre_o;              // From cpu of aeMB2_edk32.v
58 
   output [IWB-1:2]     iwb_adr_o;              // From cpu of aeMB2_edk32.v
59 
   output               iwb_stb_o;              // From cpu of aeMB2_edk32.v
60 
   output               iwb_tga_o;              // From cpu of aeMB2_edk32.v
61 
   output               iwb_wre_o;              // From cpu of aeMB2_edk32.v
62 
   // End of automatics
63 
   /*AUTOINPUT*/
64 
   // Beginning of automatic inputs (from unused autoinst inputs)
65 
   input                cwb_ack_i;              // To cpu of aeMB2_edk32.v
66 
   input [31:0]          cwb_dat_i;              // To cpu of aeMB2_edk32.v
67 
   input                dwb_ack_i;              // To cpu of aeMB2_edk32.v
68 
   input [31:0]          dwb_dat_i;              // To cpu of aeMB2_edk32.v
69 
   input                iwb_ack_i;              // To cpu of aeMB2_edk32.v
70 
   input [31:0]          iwb_dat_i;              // To cpu of aeMB2_edk32.v
71 
   input                sys_clk_i;              // To cpu of aeMB2_edk32.v
72 
   input                sys_int_i;              // To cpu of aeMB2_edk32.v
73 
   input                sys_rst_i;              // To cpu of aeMB2_edk32.v
74 
   // End of automatics
75 
   /*AUTOWIRE*/
76 
 
77 
   aeMB2_edk32
78 
     #(/*AUTOINSTPARAM*/
79 
       // Parameters
80 
       .IWB                             (IWB),
81 
       .DWB                             (DWB),
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       .TXE                             (TXE),
83 
       .MUL                             (MUL),
84 
       .BSF                             (BSF),
85 
       .FSL                             (FSL))
86 
   sim
87 
     (/*AUTOINST*/
88 
      // Outputs
89 
      .cwb_adr_o                        (cwb_adr_o[6:2]),
90 
      .cwb_dat_o                        (cwb_dat_o[31:0]),
91 
      .cwb_sel_o                        (cwb_sel_o[3:0]),
92 
      .cwb_stb_o                        (cwb_stb_o),
93 
      .cwb_tga_o                        (cwb_tga_o[1:0]),
94 
      .cwb_wre_o                        (cwb_wre_o),
95 
      .dwb_adr_o                        (dwb_adr_o[DWB-1:2]),
96 
      .dwb_cyc_o                        (dwb_cyc_o),
97 
      .dwb_dat_o                        (dwb_dat_o[31:0]),
98 
      .dwb_sel_o                        (dwb_sel_o[3:0]),
99 
      .dwb_stb_o                        (dwb_stb_o),
100 
      .dwb_tga_o                        (dwb_tga_o),
101 
      .dwb_wre_o                        (dwb_wre_o),
102 
      .iwb_adr_o                        (iwb_adr_o[IWB-1:2]),
103 
      .iwb_stb_o                        (iwb_stb_o),
104 
      .iwb_tga_o                        (iwb_tga_o),
105 
      .iwb_wre_o                        (iwb_wre_o),
106 
      // Inputs
107 
      .cwb_ack_i                        (cwb_ack_i),
108 
      .cwb_dat_i                        (cwb_dat_i[31:0]),
109 
      .dwb_ack_i                        (dwb_ack_i),
110 
      .dwb_dat_i                        (dwb_dat_i[31:0]),
111 
      .iwb_ack_i                        (iwb_ack_i),
112 
      .iwb_dat_i                        (iwb_dat_i[31:0]),
113 
      .sys_clk_i                        (sys_clk_i),
114 
      .sys_int_i                        (sys_int_i),
115 
      .sys_rst_i                        (sys_rst_i));
116 
 
117 
   // synopsys translate_off
118 
 
119 
   wire [31:0]           iwb_adr = {iwb_adr_o, 2'd0};
120 
   wire [31:0]           dwb_adr = {dwb_adr_o, 2'd0};
121 
   wire [31:0]           wMSR = sim.aslu.wMSR[31:0];
122 
 
123 
   always @(posedge sim.clk_i) if (sim.ena_i) begin
124 
 
125 
      $write ("\n", ($stime/10));
126 
      $writeh (" T", sim.pha_i);
127 
      $writeh(" PC=", iwb_adr);
128 
 
129 
      $writeh ("\t| ");
130 
 
131 
      case (sim.rOPC_IF)
132 
        6'o00: if (sim.rRD_IF == 0) $write("   "); else $write("ADD");
133 
        6'o01: $write("SUB");
134 
        6'o02: $write("ADDC");
135 
        6'o03: $write("SUBC");
136 
        6'o04: $write("ADDK");
137 
        6'o05: case (sim.rIMM_IF[1:0])
138 
                 2'o0: $write("SUBK");
139 
                 2'o1: $write("CMP");
140 
                 2'o3: $write("CMPU");
141 
                 default: $write("XXX");
142 
               endcase // case (sim.rIMM_IF[1:0])
143 
        6'o06: $write("ADDKC");
144 
        6'o07: $write("SUBKC");
145 
 
146 
        6'o10: $write("ADDI");
147 
        6'o11: $write("SUBI");
148 
        6'o12: $write("ADDIC");
149 
        6'o13: $write("SUBIC");
150 
        6'o14: $write("ADDIK");
151 
        6'o15: $write("SUBIK");
152 
        6'o16: $write("ADDIKC");
153 
        6'o17: $write("SUBIKC");
154 
 
155 
        6'o20: $write("MUL");
156 
        6'o21: case (sim.rALT_IF[10:9])
157 
                 2'o0: $write("BSRL");
158 
                 2'o1: $write("BSRA");
159 
                 2'o2: $write("BSLL");
160 
                 default: $write("XXX");
161 
               endcase // case (sim.rALT_IF[10:9])
162 
        6'o22: $write("IDIV");
163 
 
164 
        6'o30: $write("MULI");
165 
        6'o31: case (sim.rALT_IF[10:9])
166 
                 2'o0: $write("BSRLI");
167 
                 2'o1: $write("BSRAI");
168 
                 2'o2: $write("BSLLI");
169 
                 default: $write("XXX");
170 
               endcase // case (sim.rALT_IF[10:9])
171 
        6'o33: case (sim.rRB_IF[4:2])
172 
                 3'o0: $write("GET");
173 
                 3'o4: $write("PUT");
174 
                 3'o2: $write("NGET");
175 
                 3'o6: $write("NPUT");
176 
                 3'o1: $write("CGET");
177 
                 3'o5: $write("CPUT");
178 
                 3'o3: $write("NCGET");
179 
                 3'o7: $write("NCPUT");
180 
               endcase // case (sim.rRB_IF[4:2])
181 
 
182 
        6'o40: $write("OR");
183 
        6'o41: $write("AND");
184 
        6'o42: if (sim.rRD_IF == 0) $write("   "); else $write("XOR");
185 
        6'o43: $write("ANDN");
186 
        6'o44: case (sim.rIMM_IF[6:5])
187 
                 2'o0: $write("SRA");
188 
                 2'o1: $write("SRC");
189 
                 2'o2: $write("SRL");
190 
                 2'o3: if (sim.rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
191 
               endcase // case (sim.rIMM_IF[6:5])
192 
 
193 
        6'o45: $write("MOV");
194 
        6'o46: case (sim.rRA_IF[3:2])
195 
                 3'o0: $write("BR");
196 
                 3'o1: $write("BRL");
197 
                 3'o2: $write("BRA");
198 
                 3'o3: $write("BRAL");
199 
               endcase // case (sim.rRA_IF[3:2])
200 
 
201 
        6'o47: case (sim.rRD_IF[2:0])
202 
                 3'o0: $write("BEQ");
203 
                 3'o1: $write("BNE");
204 
                 3'o2: $write("BLT");
205 
                 3'o3: $write("BLE");
206 
                 3'o4: $write("BGT");
207 
                 3'o5: $write("BGE");
208 
                 default: $write("XXX");
209 
               endcase // case (sim.rRD_IF[2:0])
210 
 
211 
        6'o50: $write("ORI");
212 
        6'o51: $write("ANDI");
213 
        6'o52: $write("XORI");
214 
        6'o53: $write("ANDNI");
215 
        6'o54: $write("IMMI");
216 
        6'o55: case (sim.rRD_IF[1:0])
217 
                 2'o0: $write("RTSD");
218 
                 2'o1: $write("RTID");
219 
                 2'o2: $write("RTBD");
220 
                 default: $write("XXX");
221 
               endcase // case (sim.rRD_IF[1:0])
222 
        6'o56: case (sim.rRA_IF[3:2])
223 
                 3'o0: $write("BRI");
224 
                 3'o1: $write("BRLI");
225 
                 3'o2: $write("BRAI");
226 
                 3'o3: $write("BRALI");
227 
               endcase // case (sim.rRA_IF[3:2])
228 
        6'o57: case (sim.rRD_IF[2:0])
229 
                 3'o0: $write("BEQI");
230 
                 3'o1: $write("BNEI");
231 
                 3'o2: $write("BLTI");
232 
                 3'o3: $write("BLEI");
233 
                 3'o4: $write("BGTI");
234 
                 3'o5: $write("BGEI");
235 
                 default: $write("XXX");
236 
               endcase // case (sim.rRD_IF[2:0])
237 
 
238 
        6'o60: $write("LBU");
239 
        6'o61: $write("LHU");
240 
        6'o62: $write("LW");
241 
        6'o64: $write("SB");
242 
        6'o65: $write("SH");
243 
        6'o66: $write("SW");
244 
 
245 
        6'o70: $write("LBUI");
246 
        6'o71: $write("LHUI");
247 
        6'o72: $write("LWI");
248 
        6'o74: $write("SBI");
249 
        6'o75: $write("SHI");
250 
        6'o76: $write("SWI");
251 
 
252 
        default: $write("XXX");
253 
      endcase // case (sim.rOPC_IF)
254 
 
255 
      case (sim.rOPC_IF[3])
256 
        1'b1: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
257 
        1'b0: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF,"  ");
258 
      endcase // case (sim.rOPC_IF[3])
259 
 
260 
      if (sim.bpcu.fHZD)
261 
        $write ("*");
262 
 
263 
      // ALU
264 
      $write("\t|");
265 
      $writeh(" A=",sim.rOPA_OF);
266 
      $writeh(" B=",sim.rOPB_OF);
267 
      $writeh(" C=",sim.rOPX_OF);
268 
      $writeh(" M=",sim.rOPM_OF);
269 
 
270 
      $writeh(" MSR=", wMSR," ");
271 
 
272 
      case (sim.rALU_OF)
273 
        3'o0: $write(" ADD");
274 
        3'o1: $write(" BSF");
275 
        3'o2: $write(" SLM");
276 
        3'o3: $write(" MOV");
277 
        default: $write(" XXX");
278 
      endcase // case (sim.rALU_OF)
279 
 
280 
      // MA
281 
      $write ("\t| ");
282 
      if (sim.dwb_stb_o)
283 
        $writeh("@",sim.rRES_EX);
284 
      else
285 
        $writeh("=",sim.rRES_EX);
286 
 
287 
 
288 
      case (sim.rBRA)
289 
        2'b00: $write(" ");
290 
        2'b01: $write(".");
291 
        2'b10: $write("-");
292 
        2'b11: $write("+");
293 
      endcase // case (sim.rBRA)
294 
 
295 
      // WRITEBACK
296 
      $write("\t|");
297 
 
298 
      if (|sim.rRD_MA) begin
299 
         case (sim.rOPD_MA)
300 
           2'o2: begin
301 
              if (sim.rSEL_MA != 4'h0) $writeh("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
302 
              if (sim.rSEL_MA == 4'h0) $writeh("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
303 
           end
304 
           2'o1: $writeh("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
305 
           2'o0: $writeh("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
306 
         endcase // case (sim.rOPD_MA)
307 
      end
308 
 
309 
      /*
310 
      // STORE
311 
      if (dwb_stb_o & dwb_wre_o) begin
312 
         $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
313 
         case (dwb_sel_o)
314 
           4'hF: $write(":L");
315 
           4'h3,4'hC: $write(":W");
316 
           4'h1,4'h2,4'h4,4'h8: $write(":B");
317 
         endcase // case (dwb_sel_o)
318 
 
319 
      end
320 
       */
321 
   end // if (sim.ena_i)
322 
 
323 
   // synopsys translate_on
324 
 
325 
 
326 
endmodule // aeMB2_sim
327 
 
328 
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