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/*
 * $Id: aeMB_core.v,v 1.7 2007-05-30 18:44:30 sybreon Exp $
 *
 * AEMB 32-bit Microblaze Compatible Core
 * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public License
 * as published by the Free Software Foundation; either version 2.1 of
 * the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
 *
 * DESCRIPTION
 * Microblaze compatible, WISHBONE compliant hardware core. This core is
 * capable of executing software compile for EDK 2.1 using GCC. It has the
 * capability of handling interrupts as well as exceptions.
 *
 * HISTORY
 * $Log: not supported by cvs2svn $
 * Revision 1.6  2007/05/17 09:08:21  sybreon
 * Removed asynchronous reset signal.
 *
 * Revision 1.5  2007/04/27 00:23:55  sybreon
 * Added code documentation.
 * Improved size & speed of rtl/verilog/aeMB_aslu.v
 *
 * Revision 1.4  2007/04/25 22:15:04  sybreon
 * Added support for 8-bit and 16-bit data types.
 *
 * Revision 1.3  2007/04/11 04:30:43  sybreon
 * Added pipeline stalling from incomplete bus cycles.
 * Separated sync and async portions of code.
 *
 * Revision 1.2  2007/04/04 06:13:23  sybreon
 * Removed unused signals
 *
 * Revision 1.1  2007/03/09 17:52:17  sybreon
 * initial import
 *
 */
 
module aeMB_core (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
   dwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
   dwb_dat_i, dwb_ack_i
   );
   // Instruction WB address space
   parameter ISIZ = 32;
   // Data WB address space
   parameter DSIZ = 32;
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DSIZ-1:0]     dwb_adr_o;              // From aslu of aeMB_aslu.v
   output [31:0] dwb_dat_o;              // From regfile of aeMB_regfile.v
   output [3:0]          dwb_sel_o;              // From aslu of aeMB_aslu.v
   output               dwb_stb_o;              // From decode of aeMB_decode.v
   output               dwb_we_o;               // From decode of aeMB_decode.v
   output [ISIZ-1:0]     iwb_adr_o;              // From fetch of aeMB_fetch.v
   output               iwb_stb_o;              // From fetch of aeMB_fetch.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To control of aeMB_control.v
   input [31:0]          dwb_dat_i;              // To regfile of aeMB_regfile.v
   input                iwb_ack_i;              // To control of aeMB_control.v
   input [31:0]          iwb_dat_i;              // To fetch of aeMB_fetch.v, ...
   input                sys_clk_i;              // To control of aeMB_control.v
   input                sys_exc_i;              // To control of aeMB_control.v
   input                sys_int_i;              // To control of aeMB_control.v
   input                sys_rst_i;              // To control of aeMB_control.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 drun;                   // From control of aeMB_control.v
   wire                 frun;                   // From control of aeMB_control.v
   wire                 nclk;                   // From control of aeMB_control.v
   wire                 prst;                   // From control of aeMB_control.v
   wire                 prun;                   // From control of aeMB_control.v
   wire                 rBRA;                   // From decode of aeMB_decode.v
   wire                 rDLY;                   // From decode of aeMB_decode.v
   wire [3:0]            rDWBSEL;                // From aslu of aeMB_aslu.v
   wire                 rDWBSTB;                // From decode of aeMB_decode.v
   wire                 rDWBWE;                 // From decode of aeMB_decode.v
   wire [1:0]            rFSM;                   // From control of aeMB_control.v
   wire [15:0]           rIMM;                   // From decode of aeMB_decode.v
   wire                 rIWBSTB;                // From fetch of aeMB_fetch.v
   wire                 rLNK;                   // From decode of aeMB_decode.v
   wire                 rMSR_IE;                // From aslu of aeMB_aslu.v
   wire [1:0]            rMXALU;                 // From decode of aeMB_decode.v
   wire [1:0]            rMXLDST;                // From decode of aeMB_decode.v
   wire [1:0]            rMXSRC;                 // From decode of aeMB_decode.v
   wire [1:0]            rMXTGT;                 // From decode of aeMB_decode.v
   wire [5:0]            rOPC;                   // From decode of aeMB_decode.v
   wire [31:0]           rPC;                    // From fetch of aeMB_fetch.v
   wire [4:0]            rRA;                    // From decode of aeMB_decode.v
   wire [4:0]            rRB;                    // From decode of aeMB_decode.v
   wire [4:0]            rRD;                    // From decode of aeMB_decode.v
   wire [31:0]           rREGA;                  // From regfile of aeMB_regfile.v
   wire [31:0]           rREGB;                  // From regfile of aeMB_regfile.v
   wire [31:0]           rRESULT;                // From aslu of aeMB_aslu.v
   wire                 rRWE;                   // From decode of aeMB_decode.v
   wire [31:0]           rSIMM;                  // From decode of aeMB_decode.v
   wire [31:0]           sDWBDAT;                // From regfile of aeMB_regfile.v
   // End of automatics
 
   // INSTANTIATIONS /////////////////////////////////////////////////////////////////
 
   aeMB_regfile #(DSIZ)
     regfile (/*AUTOINST*/
              // Outputs
              .dwb_dat_o                (dwb_dat_o[31:0]),
              .rREGA                    (rREGA[31:0]),
              .rREGB                    (rREGB[31:0]),
              .sDWBDAT                  (sDWBDAT[31:0]),
              // Inputs
              .dwb_dat_i                (dwb_dat_i[31:0]),
              .rDWBSTB                  (rDWBSTB),
              .rDWBWE                   (rDWBWE),
              .rRA                      (rRA[4:0]),
              .rRB                      (rRB[4:0]),
              .rRD                      (rRD[4:0]),
              .rRESULT                  (rRESULT[31:0]),
              .rFSM                     (rFSM[1:0]),
              .rPC                      (rPC[31:0]),
              .rOPC                     (rOPC[5:0]),
              .rDWBSEL                  (rDWBSEL[3:0]),
              .rLNK                     (rLNK),
              .rRWE                     (rRWE),
              .nclk                     (nclk),
              .prst                     (prst),
              .drun                     (drun),
              .prun                     (prun));
 
   aeMB_fetch #(ISIZ)
     fetch (/*AUTOINST*/
            // Outputs
            .iwb_adr_o                  (iwb_adr_o[ISIZ-1:0]),
            .iwb_stb_o                  (iwb_stb_o),
            .rPC                        (rPC[31:0]),
            .rIWBSTB                    (rIWBSTB),
            // Inputs
            .iwb_dat_i                  (iwb_dat_i[31:0]),
            .nclk                       (nclk),
            .prst                       (prst),
            .prun                       (prun),
            .rFSM                       (rFSM[1:0]),
            .rBRA                       (rBRA),
            .rRESULT                    (rRESULT[31:0]));
 
   aeMB_control
     control (/*AUTOINST*/
              // Outputs
              .rFSM                     (rFSM[1:0]),
              .nclk                     (nclk),
              .prst                     (prst),
              .prun                     (prun),
              .frun                     (frun),
              .drun                     (drun),
              // Inputs
              .sys_rst_i                (sys_rst_i),
              .sys_clk_i                (sys_clk_i),
              .sys_int_i                (sys_int_i),
              .sys_exc_i                (sys_exc_i),
              .rIWBSTB                  (rIWBSTB),
              .iwb_ack_i                (iwb_ack_i),
              .rDWBSTB                  (rDWBSTB),
              .dwb_ack_i                (dwb_ack_i),
              .rBRA                     (rBRA),
              .rDLY                     (rDLY),
              .iwb_dat_i                (iwb_dat_i[31:0]),
              .rMSR_IE                  (rMSR_IE));
 
   aeMB_aslu #(DSIZ)
     aslu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DSIZ-1:0]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           // Inputs
           .sDWBDAT                     (sDWBDAT[31:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALU                      (rMXALU[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rPC                         (rPC[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rMXLDST                     (rMXLDST[1:0]),
           .rFSM                        (rFSM[1:0]),
           .nclk                        (nclk),
           .prst                        (prst),
           .drun                        (drun),
           .prun                        (prun));
 
   aeMB_decode
     decode (/*AUTOINST*/
             // Outputs
             .rSIMM                     (rSIMM[31:0]),
             .rMXALU                    (rMXALU[1:0]),
             .rMXSRC                    (rMXSRC[1:0]),
             .rMXTGT                    (rMXTGT[1:0]),
             .rRA                       (rRA[4:0]),
             .rRB                       (rRB[4:0]),
             .rRD                       (rRD[4:0]),
             .rOPC                      (rOPC[5:0]),
             .rIMM                      (rIMM[15:0]),
             .rDWBSTB                   (rDWBSTB),
             .rDWBWE                    (rDWBWE),
             .rDLY                      (rDLY),
             .rLNK                      (rLNK),
             .rBRA                      (rBRA),
             .rRWE                      (rRWE),
             .rMXLDST                   (rMXLDST[1:0]),
             .dwb_stb_o                 (dwb_stb_o),
             .dwb_we_o                  (dwb_we_o),
             // Inputs
             .sDWBDAT                   (sDWBDAT[31:0]),
             .rDWBSEL                   (rDWBSEL[3:0]),
             .rREGA                     (rREGA[31:0]),
             .rRESULT                   (rRESULT[31:0]),
             .rFSM                      (rFSM[1:0]),
             .iwb_dat_i                 (iwb_dat_i[31:0]),
             .nclk                      (nclk),
             .prst                      (prst),
             .drun                      (drun),
             .frun                      (frun),
             .prun                      (prun));
 
endmodule // aeMB_core

Line No.	Rev	Author	Line
1	3	sybreon	`/*`
2	38	sybreon	`* $Id: aeMB_core.v,v 1.7 2007-05-30 18:44:30 sybreon Exp $`
3	3	sybreon	`*`
4	11	sybreon	`* AEMB 32-bit Microblaze Compatible Core`
5	25	sybreon	`* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6	3	sybreon	`*`
7	25	sybreon	`* This library is free software; you can redistribute it and/or`
8			`* modify it under the terms of the GNU Lesser General Public License`
9			`* as published by the Free Software Foundation; either version 2.1 of`
10			`* the License, or (at your option) any later version.`
11	3	sybreon	`*`
12	25	sybreon	`* This library is distributed in the hope that it will be useful, but`
13			`* WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`* Lesser General Public License for more details.`
16	3	sybreon	`*`
17	25	sybreon	`* You should have received a copy of the GNU Lesser General Public`
18			`* License along with this library; if not, write to the Free Software`
19			`* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
20			`* USA`
21	3	sybreon	`*`
22			`* DESCRIPTION`
23			`* Microblaze compatible, WISHBONE compliant hardware core. This core is`
24			`* capable of executing software compile for EDK 2.1 using GCC. It has the`
25			`* capability of handling interrupts as well as exceptions.`
26			`*`
27			`* HISTORY`
28			`* $Log: not supported by cvs2svn $`
29	38	sybreon	`* Revision 1.6 2007/05/17 09:08:21 sybreon`
30			`* Removed asynchronous reset signal.`
31			`*`
32	36	sybreon	`* Revision 1.5 2007/04/27 00:23:55 sybreon`
33			`* Added code documentation.`
34			`* Improved size & speed of rtl/verilog/aeMB_aslu.v`
35			`*`
36	25	sybreon	`* Revision 1.4 2007/04/25 22:15:04 sybreon`
37			`* Added support for 8-bit and 16-bit data types.`
38			`*`
39	22	sybreon	`* Revision 1.3 2007/04/11 04:30:43 sybreon`
40			`* Added pipeline stalling from incomplete bus cycles.`
41			`* Separated sync and async portions of code.`
42			`*`
43	16	sybreon	`* Revision 1.2 2007/04/04 06:13:23 sybreon`
44			`* Removed unused signals`
45			`*`
46	11	sybreon	`* Revision 1.1 2007/03/09 17:52:17 sybreon`
47			`* initial import`
48	3	sybreon	`*`
49			`*/`
50
51			`module aeMB_core (/AUTOARG/`
52			`// Outputs`
53	22	sybreon	`iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,`
54			`dwb_adr_o,`
55	3	sybreon	`// Inputs`
56	16	sybreon	`sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,`
57			`dwb_dat_i, dwb_ack_i`
58	3	sybreon	`);`
59			`// Instruction WB address space`
60			`parameter ISIZ = 32;`
61			`// Data WB address space`
62			`parameter DSIZ = 32;`
63
64			`/AUTOOUTPUT/`
65			`// Beginning of automatic outputs (from unused autoinst outputs)`
66			`output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v`
67			`output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v`
68	22	sybreon	`output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v`
69	3	sybreon	`output dwb_stb_o; // From decode of aeMB_decode.v`
70			`output dwb_we_o; // From decode of aeMB_decode.v`
71			`output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v`
72	25	sybreon	`output iwb_stb_o; // From fetch of aeMB_fetch.v`
73	3	sybreon	`// End of automatics`
74			`/AUTOINPUT/`
75			`// Beginning of automatic inputs (from unused autoinst inputs)`
76			`input dwb_ack_i; // To control of aeMB_control.v`
77	22	sybreon	`input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v`
78	3	sybreon	`input iwb_ack_i; // To control of aeMB_control.v`
79			`input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ...`
80			`input sys_clk_i; // To control of aeMB_control.v`
81			`input sys_exc_i; // To control of aeMB_control.v`
82			`input sys_int_i; // To control of aeMB_control.v`
83			`input sys_rst_i; // To control of aeMB_control.v`
84			`// End of automatics`
85			`/AUTOWIRE/`
86			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
87			`wire drun; // From control of aeMB_control.v`
88			`wire frun; // From control of aeMB_control.v`
89			`wire nclk; // From control of aeMB_control.v`
90	36	sybreon	`wire prst; // From control of aeMB_control.v`
91			`wire prun; // From control of aeMB_control.v`
92	3	sybreon	`wire rBRA; // From decode of aeMB_decode.v`
93			`wire rDLY; // From decode of aeMB_decode.v`
94	22	sybreon	`wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v`
95	3	sybreon	`wire rDWBSTB; // From decode of aeMB_decode.v`
96			`wire rDWBWE; // From decode of aeMB_decode.v`
97			`wire [1:0] rFSM; // From control of aeMB_control.v`
98			`wire [15:0] rIMM; // From decode of aeMB_decode.v`
99	25	sybreon	`wire rIWBSTB; // From fetch of aeMB_fetch.v`
100	3	sybreon	`wire rLNK; // From decode of aeMB_decode.v`
101	38	sybreon	`wire rMSR_IE; // From aslu of aeMB_aslu.v`
102	3	sybreon	`wire [1:0] rMXALU; // From decode of aeMB_decode.v`
103	11	sybreon	`wire [1:0] rMXLDST; // From decode of aeMB_decode.v`
104	3	sybreon	`wire [1:0] rMXSRC; // From decode of aeMB_decode.v`
105			`wire [1:0] rMXTGT; // From decode of aeMB_decode.v`
106			`wire [5:0] rOPC; // From decode of aeMB_decode.v`
107			`wire [31:0] rPC; // From fetch of aeMB_fetch.v`
108			`wire [4:0] rRA; // From decode of aeMB_decode.v`
109			`wire [4:0] rRB; // From decode of aeMB_decode.v`
110			`wire [4:0] rRD; // From decode of aeMB_decode.v`
111			`wire [31:0] rREGA; // From regfile of aeMB_regfile.v`
112			`wire [31:0] rREGB; // From regfile of aeMB_regfile.v`
113			`wire [31:0] rRESULT; // From aslu of aeMB_aslu.v`
114			`wire rRWE; // From decode of aeMB_decode.v`
115			`wire [31:0] rSIMM; // From decode of aeMB_decode.v`
116	22	sybreon	`wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v`
117	3	sybreon	`// End of automatics`
118
119	25	sybreon	`// INSTANTIATIONS /////////////////////////////////////////////////////////////////`
120
121	3	sybreon	`aeMB_regfile #(DSIZ)`
122			`regfile (/AUTOINST/`
123			`// Outputs`
124			`.dwb_dat_o (dwb_dat_o[31:0]),`
125			`.rREGA (rREGA[31:0]),`
126			`.rREGB (rREGB[31:0]),`
127	22	sybreon	`.sDWBDAT (sDWBDAT[31:0]),`
128	3	sybreon	`// Inputs`
129			`.dwb_dat_i (dwb_dat_i[31:0]),`
130			`.rDWBSTB (rDWBSTB),`
131			`.rDWBWE (rDWBWE),`
132			`.rRA (rRA[4:0]),`
133			`.rRB (rRB[4:0]),`
134			`.rRD (rRD[4:0]),`
135			`.rRESULT (rRESULT[31:0]),`
136			`.rFSM (rFSM[1:0]),`
137			`.rPC (rPC[31:0]),`
138	22	sybreon	`.rOPC (rOPC[5:0]),`
139			`.rDWBSEL (rDWBSEL[3:0]),`
140	3	sybreon	`.rLNK (rLNK),`
141			`.rRWE (rRWE),`
142			`.nclk (nclk),`
143	36	sybreon	`.prst (prst),`
144	3	sybreon	`.drun (drun),`
145	36	sybreon	`.prun (prun));`
146	3	sybreon
147			`aeMB_fetch #(ISIZ)`
148			`fetch (/AUTOINST/`
149			`// Outputs`
150			`.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),`
151	25	sybreon	`.iwb_stb_o (iwb_stb_o),`
152	3	sybreon	`.rPC (rPC[31:0]),`
153	25	sybreon	`.rIWBSTB (rIWBSTB),`
154	3	sybreon	`// Inputs`
155			`.iwb_dat_i (iwb_dat_i[31:0]),`
156			`.nclk (nclk),`
157	36	sybreon	`.prst (prst),`
158			`.prun (prun),`
159	3	sybreon	`.rFSM (rFSM[1:0]),`
160			`.rBRA (rBRA),`
161			`.rRESULT (rRESULT[31:0]));`
162
163			`aeMB_control`
164			`control (/AUTOINST/`
165			`// Outputs`
166			`.rFSM (rFSM[1:0]),`
167			`.nclk (nclk),`
168	36	sybreon	`.prst (prst),`
169			`.prun (prun),`
170	3	sybreon	`.frun (frun),`
171			`.drun (drun),`
172			`// Inputs`
173			`.sys_rst_i (sys_rst_i),`
174			`.sys_clk_i (sys_clk_i),`
175			`.sys_int_i (sys_int_i),`
176			`.sys_exc_i (sys_exc_i),`
177			`.rIWBSTB (rIWBSTB),`
178			`.iwb_ack_i (iwb_ack_i),`
179			`.rDWBSTB (rDWBSTB),`
180			`.dwb_ack_i (dwb_ack_i),`
181			`.rBRA (rBRA),`
182	38	sybreon	`.rDLY (rDLY),`
183			`.iwb_dat_i (iwb_dat_i[31:0]),`
184			`.rMSR_IE (rMSR_IE));`
185	3	sybreon
186			`aeMB_aslu #(DSIZ)`
187			`aslu (/AUTOINST/`
188			`// Outputs`
189			`.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),`
190	22	sybreon	`.dwb_sel_o (dwb_sel_o[3:0]),`
191	3	sybreon	`.rRESULT (rRESULT[31:0]),`
192	22	sybreon	`.rDWBSEL (rDWBSEL[3:0]),`
193	38	sybreon	`.rMSR_IE (rMSR_IE),`
194	3	sybreon	`// Inputs`
195	22	sybreon	`.sDWBDAT (sDWBDAT[31:0]),`
196	3	sybreon	`.rBRA (rBRA),`
197			`.rDLY (rDLY),`
198			`.rREGA (rREGA[31:0]),`
199			`.rREGB (rREGB[31:0]),`
200			`.rSIMM (rSIMM[31:0]),`
201			`.rMXSRC (rMXSRC[1:0]),`
202			`.rMXTGT (rMXTGT[1:0]),`
203			`.rMXALU (rMXALU[1:0]),`
204			`.rOPC (rOPC[5:0]),`
205			`.rPC (rPC[31:0]),`
206			`.rIMM (rIMM[15:0]),`
207			`.rRD (rRD[4:0]),`
208			`.rRA (rRA[4:0]),`
209	11	sybreon	`.rMXLDST (rMXLDST[1:0]),`
210	38	sybreon	`.rFSM (rFSM[1:0]),`
211	3	sybreon	`.nclk (nclk),`
212	36	sybreon	`.prst (prst),`
213	3	sybreon	`.drun (drun),`
214	36	sybreon	`.prun (prun));`
215	3	sybreon
216			`aeMB_decode`
217			`decode (/AUTOINST/`
218			`// Outputs`
219			`.rSIMM (rSIMM[31:0]),`
220			`.rMXALU (rMXALU[1:0]),`
221			`.rMXSRC (rMXSRC[1:0]),`
222			`.rMXTGT (rMXTGT[1:0]),`
223			`.rRA (rRA[4:0]),`
224			`.rRB (rRB[4:0]),`
225			`.rRD (rRD[4:0]),`
226			`.rOPC (rOPC[5:0]),`
227			`.rIMM (rIMM[15:0]),`
228			`.rDWBSTB (rDWBSTB),`
229			`.rDWBWE (rDWBWE),`
230			`.rDLY (rDLY),`
231			`.rLNK (rLNK),`
232			`.rBRA (rBRA),`
233			`.rRWE (rRWE),`
234	11	sybreon	`.rMXLDST (rMXLDST[1:0]),`
235	3	sybreon	`.dwb_stb_o (dwb_stb_o),`
236			`.dwb_we_o (dwb_we_o),`
237			`// Inputs`
238	22	sybreon	`.sDWBDAT (sDWBDAT[31:0]),`
239			`.rDWBSEL (rDWBSEL[3:0]),`
240	3	sybreon	`.rREGA (rREGA[31:0]),`
241			`.rRESULT (rRESULT[31:0]),`
242	38	sybreon	`.rFSM (rFSM[1:0]),`
243	3	sybreon	`.iwb_dat_i (iwb_dat_i[31:0]),`
244			`.nclk (nclk),`
245	36	sybreon	`.prst (prst),`
246	3	sybreon	`.drun (drun),`
247			`.frun (frun),`
248	36	sybreon	`.prun (prun));`
249	3	sybreon
250			`endmodule // aeMB_core`

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