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// $Id: aeMB_ctrl.v,v 1.9 2007-11-15 09:26:43 sybreon Exp $
//
// AEMB CONTROL UNIT
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2007/11/14 23:19:24  sybreon
// Fixed minor typo.
//
// Revision 1.7  2007/11/14 22:14:34  sybreon
// Changed interrupt handling system (reported by M. Ettus).
//
// Revision 1.6  2007/11/10 16:39:38  sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.5  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.4  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_ctrl (/*AUTOARG*/
   // Outputs
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
   fsl_stb_o, fsl_wre_o,
   // Inputs
   rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
   dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
   );
   // INTERNAL   
   //output [31:2] rPCLNK;
   output [1:0]  rMXDST;
   output [1:0]  rMXSRC, rMXTGT, rMXALT;
   output [2:0]  rMXALU;
   output [4:0]  rRW;
   //output      rDWBSTB;
   //output      rFSLSTB;
 
   //input [1:0]         rXCE;
   input         rDLY;
   input [15:0]  rIMM;
   input [10:0]  rALT;
   input [5:0]    rOPC;
   input [4:0]    rRD, rRA, rRB;
   input [31:2]  rPC;
   input         rBRA;
   input         rMSR_IE;
   input [31:0]  xIREG;
 
   // DATA WISHBONE
   output        dwb_stb_o;
   output        dwb_wre_o;
   input         dwb_ack_i;
 
   // INST WISHBONE
   input         iwb_ack_i;
 
   // FSL WISHBONE
   output        fsl_stb_o;
   output        fsl_wre_o;
   input         fsl_ack_i;
 
   // SYSTEM
   input         gclk, grst, gena;
 
   // --- DECODE INSTRUCTIONS
   // TODO: Simplify
 
   wire [5:0]     wOPC;
   wire [4:0]     wRD, wRA, wRB;
   wire [10:0]    wALT;
 
   assign        {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
 
   wire          fSFT = (rOPC == 6'o44);
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
 
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire          fDIV = (rOPC == 6'o22);
 
   wire          fRTD = (rOPC == 6'o55);
   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire          fBRA = fBRU & rRA[3];
 
   wire          fIMM = (rOPC == 6'o54);
   wire          fMOV = (rOPC == 6'o45);
 
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire          fLDST = (&rOPC[5:4]);
 
   wire          fPUT = (rOPC == 6'o33) & rRB[4];
   wire          fGET = (rOPC == 6'o33) & !rRB[4];
 
 
   wire          wSFT = (wOPC == 6'o44);
   wire          wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
 
   wire          wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire          wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   wire          wDIV = (wOPC == 6'o22);
 
   wire          wRTD = (wOPC == 6'o55);
   wire          wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire          wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   wire          wBRA = wBRU & wRA[3];
 
   wire          wIMM = (wOPC == 6'o54);
   wire          wMOV = (wOPC == 6'o45);
 
   wire          wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire          wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   wire          wLDST = (&wOPC[5:4]);
 
   wire          wPUT = (wOPC == 6'o33) & wRB[4];
   wire          wGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // --- BRANCH SLOT REGISTERS ---------------------------
 
   reg [31:2]    rPCLNK, xPCLNK;
   reg [1:0]      rMXDST, xMXDST;
   reg [4:0]      rRW, xRW;
 
   reg [1:0]      rMXSRC, xMXSRC;
   reg [1:0]      rMXTGT, xMXTGT;
   reg [1:0]      rMXALT, xMXALT;
 
 
   // --- OPERAND SELECTOR ---------------------------------
 
   /*
   wire          fRDWE = |rRW;
   wire          fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
   wire          fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
   wire          fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
   wire          fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
 
   assign        rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
                          (fAFWD_M) ? 2'o2: // RAM
                          (fAFWD_R) ? 2'o1: // FWD
                          2'o0; // REG
 
   assign        rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
                          (fBFWD_M) ? 2'o2 : // RAM
                          (fBFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
   assign        rMXALT = (fAFWD_M) ? 2'o2 : // RAM
                          (fAFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
   */
 
   wire          wRDWE = |xRW;
   wire          wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
   wire          wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
   wire          wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
   wire          wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
 
   always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
            or wBFWD_R or wBRU or wOPC)
     //if (rBRA | |rXCE) begin
     if (rBRA) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALT <= 2'h0;
        xMXSRC <= 2'h0;
        xMXTGT <= 2'h0;
        // End of automatics
     end else begin
        xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
                  (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
                  (wBFWD_M) ? 2'o2 : // RAM
                  (wBFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG  
     end
 
   // --- ALU CONTROL ---------------------------------------
 
   /*
   reg [2:0]     rMXALU;
   always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
     or fSFT) begin
      rMXALU <= (fBRA | fMOV) ? 3'o3 :
                (fSFT) ? 3'o2 :
                (fLOG) ? 3'o1 :
                (fMUL) ? 3'o4 :
                (fBSF) ? 3'o5 :
                (fDIV) ? 3'o6 :
                3'o0;
   end
    */
 
   reg [2:0]     rMXALU, xMXALU;
 
   always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
            or wMUL or wSFT)
     //if (rBRA | |rXCE) begin
     if (rBRA) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALU <= 3'h0;
        // End of automatics
     end else begin
        xMXALU <= (wBRA | wMOV) ? 3'o3 :
                  (wSFT) ? 3'o2 :
                  (wLOG) ? 3'o1 :
                  (wMUL) ? 3'o4 :
                  (wBSF) ? 3'o5 :
                  (wDIV) ? 3'o6 :
                  3'o0;
     end
 
   // --- DELAY SLOT REGISTERS ------------------------------
 
   wire          fSKIP = (rBRA & !rDLY);
 
   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
            or fSTR or rRD)
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXDST <= 2'h0;
        xRW <= 5'h0;
        // End of automatics
     end else begin
        /*
        case (rXCE)
          2'o2: xMXDST <= 2'o1;
          default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                             (fLOD | fGET) ? 2'o2 :
                             (fBRU) ? 2'o1 :
                             2'o0;
        endcase
 
        case (rXCE)
          2'o2: xRW <= 5'd14;
          default: xRW <= rRD;
        endcase
        */
        xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                  (fLOD | fGET) ? 2'o2 :
                  (fBRU) ? 2'o1 :
                  2'o0;
        xRW <= rRD;
     end // else: !if(fSKIP)
 
 
   // --- DATA WISHBONE ----------------------------------
 
   wire          fDACK = !(dwb_stb_o ^ dwb_ack_i);
 
   reg           rDWBSTB, xDWBSTB;
   reg           rDWBWRE, xDWBWRE;
 
   assign        dwb_stb_o = rDWBSTB;
   assign        dwb_wre_o = rDWBWRE;
 
 
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
     //if (fSKIP | |rXCE) begin
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xDWBSTB <= 1'h0;
        xDWBWRE <= 1'h0;
        // End of automatics
     end else begin
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
        xDWBWRE <= fSTR & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rDWBSTB <= 1'h0;
        rDWBWRE <= 1'h0;
        // End of automatics
     end else if (fDACK) begin
        rDWBSTB <= #1 xDWBSTB;
        rDWBWRE <= #1 xDWBWRE;
     end
 
 
   // --- FSL WISHBONE -----------------------------------
 
   wire          fFACK = !(fsl_stb_o ^ fsl_ack_i);
 
   reg           rFSLSTB, xFSLSTB;
   reg           rFSLWRE, xFSLWRE;
 
   assign        fsl_stb_o = rFSLSTB;
   assign        fsl_wre_o = rFSLWRE;
 
   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
     //if (fSKIP | |rXCE) begin
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xFSLSTB <= 1'h0;
        xFSLWRE <= 1'h0;
        // End of automatics
     end else begin
        xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
        xFSLWRE <= fPUT & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFSLSTB <= 1'h0;
        rFSLWRE <= 1'h0;
        // End of automatics
     end else if (fFACK) begin
        rFSLSTB <= #1 xFSLSTB;
        rFSLWRE <= #1 xFSLWRE;
     end
 
   // --- PIPELINE CONTROL DELAY ----------------------------
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMXALT <= 2'h0;
        rMXALU <= 3'h0;
        rMXDST <= 2'h0;
        rMXSRC <= 2'h0;
        rMXTGT <= 2'h0;
        rRW <= 5'h0;
        // End of automatics
     end else if (gena) begin
        //rPCLNK <= #1 xPCLNK;
        rMXDST <= #1 xMXDST;
        rRW <= #1 xRW;
        rMXSRC <= #1 xMXSRC;
        rMXTGT <= #1 xMXTGT;
        rMXALT <= #1 xMXALT;
        rMXALU <= #1 xMXALU;
     end
 
 
endmodule // aeMB_ctrl

Line No.	Rev	Author	Line
1	65	sybreon	`// $Id: aeMB_ctrl.v,v 1.9 2007-11-15 09:26:43 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB CONTROL UNIT`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	65	sybreon	`// Revision 1.8 2007/11/14 23:19:24 sybreon`
24			`// Fixed minor typo.`
25			`//`
26	62	sybreon	`// Revision 1.7 2007/11/14 22:14:34 sybreon`
27			`// Changed interrupt handling system (reported by M. Ettus).`
28			`//`
29	61	sybreon	`// Revision 1.6 2007/11/10 16:39:38 sybreon`
30			`// Upgraded license to LGPLv3.`
31			`// Significant performance optimisations.`
32			`//`
33	55	sybreon	`// Revision 1.5 2007/11/09 20:51:52 sybreon`
34			`// Added GET/PUT support through a FSL bus.`
35			`//`
36	53	sybreon	`// Revision 1.4 2007/11/08 17:48:14 sybreon`
37			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
38			`//`
39	51	sybreon	`// Revision 1.3 2007/11/08 14:17:47 sybreon`
40			`// Parameterised optional components.`
41			`//`
42	50	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
43			`// Added better (beta) interrupt support.`
44			`// Changed MSR_IE to disabled at reset as per MB docs.`
45			`//`
46	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
47			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
48			`// Fixed various minor data hazard bugs.`
49			`// Code compatible with -O0/1/2/3/s generated code.`
50			`//`
51	41	sybreon
52			`module aeMB_ctrl (/AUTOARG/`
53			`// Outputs`
54	62	sybreon	`rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,`
55			`fsl_stb_o, fsl_wre_o,`
56	41	sybreon	`// Inputs`
57	61	sybreon	`rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,`
58			`dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena`
59	41	sybreon	`);`
60			`// INTERNAL`
61			`//output [31:2] rPCLNK;`
62			`output [1:0] rMXDST;`
63			`output [1:0] rMXSRC, rMXTGT, rMXALT;`
64			`output [2:0] rMXALU;`
65			`output [4:0] rRW;`
66	62	sybreon	`//output rDWBSTB;`
67			`//output rFSLSTB;`
68	53	sybreon
69	61	sybreon	`//input [1:0] rXCE;`
70	41	sybreon	`input rDLY;`
71			`input [15:0] rIMM;`
72			`input [10:0] rALT;`
73			`input [5:0] rOPC;`
74			`input [4:0] rRD, rRA, rRB;`
75			`input [31:2] rPC;`
76			`input rBRA;`
77			`input rMSR_IE;`
78	61	sybreon	`input [31:0] xIREG;`
79	41	sybreon
80			`// DATA WISHBONE`
81			`output dwb_stb_o;`
82			`output dwb_wre_o;`
83	51	sybreon	`input dwb_ack_i;`
84
85			`// INST WISHBONE`
86	55	sybreon	`input iwb_ack_i;`
87	41	sybreon
88	53	sybreon	`// FSL WISHBONE`
89			`output fsl_stb_o;`
90			`output fsl_wre_o;`
91			`input fsl_ack_i;`
92
93	41	sybreon	`// SYSTEM`
94			`input gclk, grst, gena;`
95
96			`// --- DECODE INSTRUCTIONS`
97			`// TODO: Simplify`
98
99	55	sybreon	`wire [5:0] wOPC;`
100			`wire [4:0] wRD, wRA, wRB;`
101			`wire [10:0] wALT;`
102
103	61	sybreon	`assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian`
104	55	sybreon
105	41	sybreon	`wire fSFT = (rOPC == 6'o44);`
106			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
107
108			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
109			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
110			`wire fDIV = (rOPC == 6'o22);`
111
112			`wire fRTD = (rOPC == 6'o55);`
113			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
114			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
115			`wire fBRA = fBRU & rRA[3];`
116
117			`wire fIMM = (rOPC == 6'o54);`
118			`wire fMOV = (rOPC == 6'o45);`
119
120			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
121			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
122			`wire fLDST = (&rOPC[5:4]);`
123
124	53	sybreon	`wire fPUT = (rOPC == 6'o33) & rRB[4];`
125			`wire fGET = (rOPC == 6'o33) & !rRB[4];`
126	55	sybreon
127
128			`wire wSFT = (wOPC == 6'o44);`
129			`wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
130
131			`wire wMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
132			`wire wBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
133			`wire wDIV = (wOPC == 6'o22);`
134	41	sybreon
135	55	sybreon	`wire wRTD = (wOPC == 6'o55);`
136			`wire wBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
137			`wire wBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
138			`wire wBRA = wBRU & wRA[3];`
139
140			`wire wIMM = (wOPC == 6'o54);`
141			`wire wMOV = (wOPC == 6'o45);`
142
143			`wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
144			`wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
145			`wire wLDST = (&wOPC[5:4]);`
146
147			`wire wPUT = (wOPC == 6'o33) & wRB[4];`
148			`wire wGET = (wOPC == 6'o33) & !wRB[4];`
149
150
151			`// --- BRANCH SLOT REGISTERS ---------------------------`
152
153			`reg [31:2] rPCLNK, xPCLNK;`
154			`reg [1:0] rMXDST, xMXDST;`
155			`reg [4:0] rRW, xRW;`
156
157			`reg [1:0] rMXSRC, xMXSRC;`
158			`reg [1:0] rMXTGT, xMXTGT;`
159			`reg [1:0] rMXALT, xMXALT;`
160
161
162	41	sybreon	`// --- OPERAND SELECTOR ---------------------------------`
163
164	55	sybreon	`/*`
165	41	sybreon	`wire fRDWE = \|rRW;`
166			`wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;`
167			`wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;`
168			`wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;`
169			`wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;`
170
171			`assign rMXSRC = (fBRU \| fBCC) ? 2'o3 : // PC`
172			`(fAFWD_M) ? 2'o2: // RAM`
173			`(fAFWD_R) ? 2'o1: // FWD`
174			`2'o0; // REG`
175
176			`assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM`
177			`(fBFWD_M) ? 2'o2 : // RAM`
178			`(fBFWD_R) ? 2'o1 : // FWD`
179			`2'o0; // REG`
180
181			`assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM`
182			`(fAFWD_R) ? 2'o1 : // FWD`
183			`2'o0; // REG`
184	55	sybreon	`*/`
185
186			`wire wRDWE = \|xRW;`
187			`wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;`
188			`wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;`
189			`wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;`
190			`wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;`
191
192	61	sybreon	`always @(/AUTOSENSE/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M`
193			`or wBFWD_R or wBRU or wOPC)`
194			`//if (rBRA \| \|rXCE) begin`
195			`if (rBRA) begin`
196	55	sybreon	`/AUTORESET/`
197			`// Beginning of autoreset for uninitialized flops`
198			`xMXALT <= 2'h0;`
199			`xMXSRC <= 2'h0;`
200			`xMXTGT <= 2'h0;`
201			`// End of automatics`
202			`end else begin`
203			`xMXSRC <= (wBRU \| wBCC) ? 2'o3 : // PC`
204			`(wAFWD_M) ? 2'o2 : // RAM`
205			`(wAFWD_R) ? 2'o1 : // FWD`
206			`2'o0; // REG`
207			`xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM`
208			`(wBFWD_M) ? 2'o2 : // RAM`
209			`(wBFWD_R) ? 2'o1 : // FWD`
210			`2'o0; // REG`
211			`xMXALT <= (wAFWD_M) ? 2'o2 : // RAM`
212			`(wAFWD_R) ? 2'o1 : // FWD`
213			`2'o0; // REG`
214			`end`
215	41	sybreon
216			`// --- ALU CONTROL ---------------------------------------`
217
218	55	sybreon	`/*`
219	41	sybreon	`reg [2:0] rMXALU;`
220	55	sybreon	`always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL`
221			`or fSFT) begin`
222	41	sybreon	`rMXALU <= (fBRA \| fMOV) ? 3'o3 :`
223			`(fSFT) ? 3'o2 :`
224			`(fLOG) ? 3'o1 :`
225			`(fMUL) ? 3'o4 :`
226			`(fBSF) ? 3'o5 :`
227			`(fDIV) ? 3'o6 :`
228			`3'o0;`
229			`end`
230	55	sybreon	`*/`
231
232			`reg [2:0] rMXALU, xMXALU;`
233
234	61	sybreon	`always @(/AUTOSENSE/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV`
235			`or wMUL or wSFT)`
236			`//if (rBRA \| \|rXCE) begin`
237			`if (rBRA) begin`
238	55	sybreon	`/AUTORESET/`
239			`// Beginning of autoreset for uninitialized flops`
240			`xMXALU <= 3'h0;`
241			`// End of automatics`
242			`end else begin`
243			`xMXALU <= (wBRA \| wMOV) ? 3'o3 :`
244			`(wSFT) ? 3'o2 :`
245			`(wLOG) ? 3'o1 :`
246			`(wMUL) ? 3'o4 :`
247			`(wBSF) ? 3'o5 :`
248			`(wDIV) ? 3'o6 :`
249			`3'o0;`
250			`end`
251	41	sybreon
252			`// --- DELAY SLOT REGISTERS ------------------------------`
253
254	50	sybreon	`wire fSKIP = (rBRA & !rDLY);`
255	51	sybreon
256	53	sybreon	`always @(/AUTOSENSE/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP`
257	61	sybreon	`or fSTR or rRD)`
258	41	sybreon	`if (fSKIP) begin`
259			`/AUTORESET/`
260			`// Beginning of autoreset for uninitialized flops`
261			`xMXDST <= 2'h0;`
262			`xRW <= 5'h0;`
263			`// End of automatics`
264			`end else begin`
265	61	sybreon	`/*`
266	41	sybreon	`case (rXCE)`
267	44	sybreon	`2'o2: xMXDST <= 2'o1;`
268	41	sybreon	`default: xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
269	53	sybreon	`(fLOD \| fGET) ? 2'o2 :`
270	41	sybreon	`(fBRU) ? 2'o1 :`
271			`2'o0;`
272	44	sybreon	`endcase`
273
274	41	sybreon	`case (rXCE)`
275	44	sybreon	`2'o2: xRW <= 5'd14;`
276	41	sybreon	`default: xRW <= rRD;`
277	44	sybreon	`endcase`
278	61	sybreon	`*/`
279			`xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
280			`(fLOD \| fGET) ? 2'o2 :`
281			`(fBRU) ? 2'o1 :`
282			`2'o0;`
283			`xRW <= rRD;`
284	44	sybreon	`end // else: !if(fSKIP)`
285	53	sybreon
286
287			`// --- DATA WISHBONE ----------------------------------`
288
289	65	sybreon	`wire fDACK = !(dwb_stb_o ^ dwb_ack_i);`
290	41	sybreon
291	53	sybreon	`reg rDWBSTB, xDWBSTB;`
292			`reg rDWBWRE, xDWBWRE;`
293
294			`assign dwb_stb_o = rDWBSTB;`
295			`assign dwb_wre_o = rDWBWRE;`
296	41	sybreon
297	53	sybreon
298	61	sybreon	`always @(/AUTOSENSE/fLOD or fSKIP or fSTR or iwb_ack_i)`
299			`//if (fSKIP \| \|rXCE) begin`
300			`if (fSKIP) begin`
301	41	sybreon	`/AUTORESET/`
302			`// Beginning of autoreset for uninitialized flops`
303	53	sybreon	`xDWBSTB <= 1'h0;`
304			`xDWBWRE <= 1'h0;`
305	41	sybreon	`// End of automatics`
306	53	sybreon	`end else begin`
307			`xDWBSTB <= (fLOD \| fSTR) & iwb_ack_i;`
308			`xDWBWRE <= fSTR & iwb_ack_i;`
309	51	sybreon	`end`
310	53	sybreon
311	51	sybreon	`always @(posedge gclk)`
312			`if (grst) begin`
313			`/AUTORESET/`
314			`// Beginning of autoreset for uninitialized flops`
315			`rDWBSTB <= 1'h0;`
316			`rDWBWRE <= 1'h0;`
317			`// End of automatics`
318			`end else if (fDACK) begin`
319	41	sybreon	`rDWBSTB <= #1 xDWBSTB;`
320			`rDWBWRE <= #1 xDWBWRE;`
321	51	sybreon	`end`
322	41	sybreon
323	53	sybreon
324			`// --- FSL WISHBONE -----------------------------------`
325
326	65	sybreon	`wire fFACK = !(fsl_stb_o ^ fsl_ack_i);`
327	53	sybreon
328			`reg rFSLSTB, xFSLSTB;`
329			`reg rFSLWRE, xFSLWRE;`
330
331			`assign fsl_stb_o = rFSLSTB;`
332			`assign fsl_wre_o = rFSLWRE;`
333
334	61	sybreon	`always @(/AUTOSENSE/fGET or fPUT or fSKIP or iwb_ack_i)`
335			`//if (fSKIP \| \|rXCE) begin`
336			`if (fSKIP) begin`
337	53	sybreon	`/AUTORESET/`
338			`// Beginning of autoreset for uninitialized flops`
339			`xFSLSTB <= 1'h0;`
340			`xFSLWRE <= 1'h0;`
341			`// End of automatics`
342			`end else begin`
343			`xFSLSTB <= (fPUT \| fGET) & iwb_ack_i;`
344			`xFSLWRE <= fPUT & iwb_ack_i;`
345			`end`
346
347			`always @(posedge gclk)`
348			`if (grst) begin`
349			`/AUTORESET/`
350			`// Beginning of autoreset for uninitialized flops`
351			`rFSLSTB <= 1'h0;`
352			`rFSLWRE <= 1'h0;`
353			`// End of automatics`
354			`end else if (fFACK) begin`
355			`rFSLSTB <= #1 xFSLSTB;`
356			`rFSLWRE <= #1 xFSLWRE;`
357			`end`
358	41	sybreon
359	53	sybreon	`// --- PIPELINE CONTROL DELAY ----------------------------`
360
361			`always @(posedge gclk)`
362			`if (grst) begin`
363			`/AUTORESET/`
364			`// Beginning of autoreset for uninitialized flops`
365	55	sybreon	`rMXALT <= 2'h0;`
366			`rMXALU <= 3'h0;`
367	53	sybreon	`rMXDST <= 2'h0;`
368	55	sybreon	`rMXSRC <= 2'h0;`
369			`rMXTGT <= 2'h0;`
370	53	sybreon	`rRW <= 5'h0;`
371			`// End of automatics`
372			`end else if (gena) begin`
373			`//rPCLNK <= #1 xPCLNK;`
374			`rMXDST <= #1 xMXDST;`
375			`rRW <= #1 xRW;`
376	55	sybreon	`rMXSRC <= #1 xMXSRC;`
377			`rMXTGT <= #1 xMXTGT;`
378			`rMXALT <= #1 xMXALT;`
379			`rMXALU <= #1 xMXALU;`
380	53	sybreon	`end`
381
382
383	41	sybreon	`endmodule // aeMB_ctrl`

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