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1 102 sybreon
/* $Id: aeMB_xecu.v,v 1.11 2008-01-19 15:57:36 sybreon Exp $
2 96 sybreon
**
3
** AEMB MAIN EXECUTION ALU
4
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
5
**
6
** This file is part of AEMB.
7
**
8
** AEMB is free software: you can redistribute it and/or modify it
9
** under the terms of the GNU Lesser General Public License as
10
** published by the Free Software Foundation, either version 3 of the
11
** License, or (at your option) any later version.
12
**
13
** AEMB is distributed in the hope that it will be useful, but WITHOUT
14
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
16
** Public License for more details.
17
**
18
** You should have received a copy of the GNU Lesser General Public
19
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
20
*/
21 41 sybreon
 
22
module aeMB_xecu (/*AUTOARG*/
23
   // Outputs
24 66 sybreon
   dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL,
25
   rMSR_IE, rMSR_BIP,
26 41 sybreon
   // Inputs
27 61 sybreon
   rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
28 96 sybreon
   rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
29 41 sybreon
   );
30
   parameter DW=32;
31 50 sybreon
 
32
   parameter MUL=0;
33
   parameter BSF=0;
34 41 sybreon
 
35
   // DATA WISHBONE
36
   output [DW-1:2] dwb_adr_o;
37
   output [3:0]    dwb_sel_o;
38 53 sybreon
 
39
   // FSL WISHBONE
40 66 sybreon
   output [6:2]   fsl_adr_o;
41
   output [1:0]   fsl_tag_o;
42 41 sybreon
 
43
   // INTERNAL
44
   output [31:0]   rRESULT;
45
   output [3:0]    rDWBSEL;
46 44 sybreon
   output          rMSR_IE;
47
   output          rMSR_BIP;
48 41 sybreon
   input [31:0]    rREGA, rREGB;
49
   input [1:0]      rMXSRC, rMXTGT;
50 53 sybreon
   input [4:0]      rRA, rRB;
51 41 sybreon
   input [2:0]      rMXALU;
52
   input           rBRA, rDLY;
53 50 sybreon
   input [10:0]    rALT;
54 96 sybreon
 
55
   input           rSTALL;
56 41 sybreon
   input [31:0]    rSIMM;
57
   input [15:0]    rIMM;
58
   input [5:0]      rOPC;
59
   input [4:0]      rRD;
60
   input [31:0]    rDWBDI;
61
   input [31:2]    rPC;
62
 
63
   // SYSTEM
64
   input           gclk, grst, gena;
65
 
66
   reg             rMSR_C, xMSR_C;
67
   reg             rMSR_IE, xMSR_IE;
68 44 sybreon
   reg             rMSR_BE, xMSR_BE;
69
   reg             rMSR_BIP, xMSR_BIP;
70 41 sybreon
 
71 44 sybreon
   wire            fSKIP = rBRA & !rDLY;
72
 
73 41 sybreon
   // --- OPERAND SELECT
74
 
75
   reg [31:0]       rOPA, rOPB;
76
   always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
77
     case (rMXSRC)
78
       2'o0: rOPA <= rREGA;
79
       2'o1: rOPA <= rRESULT;
80
       2'o2: rOPA <= rDWBDI;
81
       2'o3: rOPA <= {rPC, 2'o0};
82
     endcase // case (rMXSRC)
83
 
84
   always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM)
85
     case (rMXTGT)
86
       2'o0: rOPB <= rREGB;
87
       2'o1: rOPB <= rRESULT;
88
       2'o2: rOPB <= rDWBDI;
89
       2'o3: rOPB <= rSIMM;
90
     endcase // case (rMXTGT)
91
 
92 44 sybreon
   // --- ADD/SUB SELECTOR ----
93 50 sybreon
   // FIXME: Redesign
94 44 sybreon
   // TODO: Refactor
95
   // TODO: Verify signed compare
96
 
97
   wire             wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
98
   wire [31:0]       wADD, wSUB, wRES_A, wCMP, wOPX;
99
 
100
   wire             wCMPU = (rOPA > rOPB);
101
   wire             wCMPF = (rIMM[1]) ? wCMPU :
102
                            ((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
103
 
104
   assign           {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
105
   assign           wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
106
   assign           wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
107
 
108
   assign           {wSUBC,wSUB} = {wADDC,wADD};
109
   assign           {wADDC,wADD} = (rOPB + wOPX) + wOPC;
110
 
111
   reg              rRES_ADDC;
112
   reg [31:0]        rRES_ADD;
113
   always @(rIMM or rOPC or wADD or wADDC or wCMP
114
            or wCMPC or wSUB or wSUBC)
115
     case ({rOPC[3],rOPC[0],rIMM[0]})
116
       4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
117
       4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
118
       default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
119
     endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
120
 
121 50 sybreon
   // --- LOGIC SELECTOR --------------------------------------
122 41 sybreon
 
123
   reg [31:0]        rRES_LOG;
124
   always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
125
     case (rOPC[1:0])
126
       2'o0: rRES_LOG <= #1 rOPA | rOPB;
127
       2'o1: rRES_LOG <= #1 rOPA & rOPB;
128
       2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
129
       2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
130
     endcase // case (rOPC[1:0])
131
 
132 50 sybreon
   // --- SHIFTER SELECTOR ------------------------------------
133 41 sybreon
 
134
   reg [31:0]        rRES_SFT;
135
   reg              rRES_SFTC;
136
 
137
   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
138
     case (rIMM[6:5])
139
       2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]};
140
       2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]};
141
       2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
142
       2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
143
                                      { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
144
     endcase // case (rIMM[6:5])
145
 
146 50 sybreon
   // --- MOVE SELECTOR ---------------------------------------
147 41 sybreon
 
148 44 sybreon
   wire [31:0]       wMSR = {rMSR_C, 3'o0,
149
                            20'h0ED32,
150
                            4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
151 41 sybreon
   wire             fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
152
   wire             fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
153
   reg [31:0]        rRES_MOV;
154
   always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
155
            or wMSR)
156
     rRES_MOV <= (fMFSR) ? wMSR :
157
                 (fMFPC) ? rPC :
158
                 (rRA[3]) ? rOPB :
159
                 rOPA;
160
 
161 50 sybreon
   // --- MULTIPLIER ------------------------------------------
162 72 sybreon
   // TODO: 2 stage multiplier
163
 
164 96 sybreon
   reg [31:0]        rRES_MUL, rRES_MUL0, xRES_MUL;
165 50 sybreon
   always @(/*AUTOSENSE*/rOPA or rOPB) begin
166 96 sybreon
      xRES_MUL <= (rOPA * rOPB);
167 50 sybreon
   end
168
 
169 96 sybreon
   always @(posedge gclk)
170
     if (grst) begin
171
        /*AUTORESET*/
172
        // Beginning of autoreset for uninitialized flops
173
        rRES_MUL <= 32'h0;
174
        // End of automatics
175
     end else if (rSTALL) begin
176
        rRES_MUL <= #1 xRES_MUL;
177
     end
178
 
179
 
180 50 sybreon
   // --- BARREL SHIFTER --------------------------------------
181
 
182
   reg [31:0]     rRES_BSF;
183
   reg [31:0]     xBSRL, xBSRA, xBSLL;
184 41 sybreon
 
185 50 sybreon
   // Infer a logical left barrel shifter.   
186
   always @(/*AUTOSENSE*/rOPA or rOPB)
187
     xBSLL <= rOPA << rOPB[4:0];
188
 
189
   // Infer a logical right barrel shifter.
190
   always @(/*AUTOSENSE*/rOPA or rOPB)
191
     xBSRL <= rOPA >> rOPB[4:0];
192
 
193
   // Infer a arithmetic right barrel shifter.
194
   always @(/*AUTOSENSE*/rOPA or rOPB)
195
     case (rOPB[4:0])
196
       5'd00: xBSRA <= rOPA;
197
       5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
198
       5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
199
       5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
200
       5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
201
       5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
202
       5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
203
       5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
204
       5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
205
       5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
206
       5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
207
       5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
208
       5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
209
       5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
210
       5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
211
       5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
212
       5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
213
       5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
214
       5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
215
       5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
216
       5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
217
       5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
218
       5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
219
       5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
220
       5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
221
       5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
222
       5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
223
       5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
224
       5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
225
       5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
226
       5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
227
       5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
228
     endcase // case (rOPB[4:0])
229
 
230 96 sybreon
   reg [31:0]     rBSRL, rBSRA, rBSLL;
231
 
232
   always @(posedge gclk)
233
     if (grst) begin
234
        /*AUTORESET*/
235
        // Beginning of autoreset for uninitialized flops
236
        rBSLL <= 32'h0;
237
        rBSRA <= 32'h0;
238
        rBSRL <= 32'h0;
239
        // End of automatics
240
     end else if (rSTALL) begin
241
        rBSRL <= #1 xBSRL;
242
        rBSRA <= #1 xBSRA;
243
        rBSLL <= #1 xBSLL;
244
     end
245
 
246
   always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL)
247 50 sybreon
     case (rALT[10:9])
248 96 sybreon
       2'd0: rRES_BSF <= rBSRL;
249
       2'd1: rRES_BSF <= rBSRA;
250
       2'd2: rRES_BSF <= rBSLL;
251 50 sybreon
       default: rRES_BSF <= 32'hX;
252
     endcase // case (rALT[10:9])
253
 
254
 
255 44 sybreon
   // --- MSR REGISTER -----------------
256 41 sybreon
 
257 44 sybreon
   // C
258 102 sybreon
   wire            fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
259 44 sybreon
   wire            fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
260 41 sybreon
 
261 44 sybreon
   always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
262 61 sybreon
            or rOPA or rRES_ADDC or rRES_SFTC)
263
     //if (fSKIP | |rXCE) begin
264
     if (fSKIP) begin
265 44 sybreon
        xMSR_C <= rMSR_C;
266
     end else
267
       case (rMXALU)
268
         3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
269
         3'o1: xMSR_C <= rMSR_C; // LOGIC       
270
         3'o2: xMSR_C <= rRES_SFTC; // SHIFT
271
         3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
272
         3'o4: xMSR_C <= rMSR_C;
273
         3'o5: xMSR_C <= rMSR_C;
274
         default: xMSR_C <= 1'hX;
275 102 sybreon
       endcase // case (rMXALU)
276 44 sybreon
 
277
   // IE/BIP/BE
278 102 sybreon
   wire             fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;
279
   wire             fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
280 61 sybreon
   wire             fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
281 72 sybreon
   wire             fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
282 41 sybreon
 
283 72 sybreon
   always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
284
     xMSR_IE <= (fINT) ? 1'b0 :
285 44 sybreon
                (fRTID) ? 1'b1 :
286
                (fMTS) ? rOPA[1] :
287
                rMSR_IE;
288 41 sybreon
 
289 44 sybreon
   always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
290
     xMSR_BIP <= (fBRK) ? 1'b1 :
291
                 (fRTBD) ? 1'b0 :
292
                 (fMTS) ? rOPA[3] :
293
                 rMSR_BIP;
294
 
295
   always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
296
     xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
297
 
298 50 sybreon
   // --- RESULT SELECTOR -------------------------------------------
299
   // Selects results from functional units. 
300 41 sybreon
   reg [31:0]       rRESULT, xRESULT;
301
 
302
   // RESULT
303
   always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
304
            or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
305
     if (fSKIP)
306
       /*AUTORESET*/
307
       // Beginning of autoreset for uninitialized flops
308
       xRESULT <= 32'h0;
309
       // End of automatics
310
     else
311
       case (rMXALU)
312
         3'o0: xRESULT <= rRES_ADD;
313
         3'o1: xRESULT <= rRES_LOG;
314
         3'o2: xRESULT <= rRES_SFT;
315
         3'o3: xRESULT <= rRES_MOV;
316 50 sybreon
         3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX;
317
         3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX;
318 41 sybreon
         default: xRESULT <= 32'hX;
319
       endcase // case (rMXALU)
320
 
321
   // --- DATA WISHBONE -----
322
 
323
   reg [3:0]         rDWBSEL, xDWBSEL;
324
   assign           dwb_adr_o = rRESULT[DW-1:2];
325
   assign           dwb_sel_o = rDWBSEL;
326
 
327
   always @(/*AUTOSENSE*/rOPC or wADD)
328
     case (rOPC[1:0])
329 53 sybreon
       2'o0: case (wADD[1:0]) // 8'bit
330 41 sybreon
               2'o0: xDWBSEL <= 4'h8;
331
               2'o1: xDWBSEL <= 4'h4;
332
               2'o2: xDWBSEL <= 4'h2;
333
               2'o3: xDWBSEL <= 4'h1;
334
             endcase // case (wADD[1:0])
335 53 sybreon
       2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
336
       2'o2: xDWBSEL <= 4'hF; // 32'bit
337
       2'o3: xDWBSEL <= 4'h0; // FSL
338 41 sybreon
     endcase // case (rOPC[1:0])
339 53 sybreon
 
340
   // --- FSL WISHBONE --------------------
341
 
342
   reg [14:2]       rFSLADR, xFSLADR;
343 41 sybreon
 
344 66 sybreon
   assign           {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2];
345 53 sybreon
 
346
   always @(/*AUTOSENSE*/rALT or rRB) begin
347
      xFSLADR <= {rALT, rRB[3:2]};
348
   end
349
 
350 41 sybreon
   // --- SYNC ---
351
 
352
   always @(posedge gclk)
353
     if (grst) begin
354
        /*AUTORESET*/
355
        // Beginning of autoreset for uninitialized flops
356
        rDWBSEL <= 4'h0;
357 53 sybreon
        rFSLADR <= 13'h0;
358 44 sybreon
        rMSR_BE <= 1'h0;
359
        rMSR_BIP <= 1'h0;
360 41 sybreon
        rMSR_C <= 1'h0;
361 44 sybreon
        rMSR_IE <= 1'h0;
362 41 sybreon
        rRESULT <= 32'h0;
363
        // End of automatics
364 102 sybreon
     end else if (gena) begin // if (grst)
365 41 sybreon
        rRESULT <= #1 xRESULT;
366
        rDWBSEL <= #1 xDWBSEL;
367
        rMSR_C <= #1 xMSR_C;
368
        rMSR_IE <= #1 xMSR_IE;
369 44 sybreon
        rMSR_BE <= #1 xMSR_BE;
370 53 sybreon
        rMSR_BIP <= #1 xMSR_BIP;
371 96 sybreon
        rFSLADR <= #1 xFSLADR;
372 41 sybreon
     end
373 72 sybreon
 
374 41 sybreon
endmodule // aeMB_xecu
375 96 sybreon
 
376
/*
377
 $Log: not supported by cvs2svn $
378 102 sybreon
 Revision 1.10  2007/12/25 22:15:09  sybreon
379
 Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
380
 
381 96 sybreon
 Revision 1.9  2007/11/30 16:42:51  sybreon
382
 Minor code cleanup.
383
 
384
 Revision 1.8  2007/11/16 21:52:03  sybreon
385
 Added fsl_tag_o to FSL bus (tag either address or data).
386
 
387
 Revision 1.7  2007/11/14 22:14:34  sybreon
388
 Changed interrupt handling system (reported by M. Ettus).
389
 
390
 Revision 1.6  2007/11/10 16:39:38  sybreon
391
 Upgraded license to LGPLv3.
392
 Significant performance optimisations.
393
 
394
 Revision 1.5  2007/11/09 20:51:52  sybreon
395
 Added GET/PUT support through a FSL bus.
396
 
397
 Revision 1.4  2007/11/08 14:17:47  sybreon
398
 Parameterised optional components.
399
 
400
 Revision 1.3  2007/11/03 08:34:55  sybreon
401
 Minor code cleanup.
402
 
403
 Revision 1.2  2007/11/02 19:20:58  sybreon
404
 Added better (beta) interrupt support.
405
 Changed MSR_IE to disabled at reset as per MB docs.
406
 
407
 Revision 1.1  2007/11/02 03:25:41  sybreon
408
 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
409
 Fixed various minor data hazard bugs.
410
 Code compatible with -O0/1/2/3/s generated code.
411
 
412
*/

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