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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] [aeMB_fetch.v] - Blame information for rev 14

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//                              -*- Mode: Verilog -*-
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// Filename        : aeMB_fetch.v
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// Description     : AEMB Programme Counter
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// Author          : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On      : Sat Dec 30 04:34:44 2006
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// Last Modified By: $Author: sybreon $
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// Last Modified On: $Date: 2007-04-04 14:08:34 $
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// Update Count    : $Revision: 1.2 $
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// Status          : $State: Exp $
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/*
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 * $Id: aeMB_fetch.v,v 1.2 2007-04-04 14:08:34 sybreon Exp $
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 *
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 * AEMB Instruction Fetch
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 * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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 *
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 * This library is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU Lesser General Public License as published by
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 * the Free Software Foundation; either version 2.1 of the License,
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 * or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful, but
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 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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 * License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public License
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 * along with this library; if not, write to the Free Software Foundation, Inc.,
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 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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 *
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 * DESCRIPTION
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 * Controls the instruction side of AEMB.
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 *
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 * HISTORY
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 * $Log: not supported by cvs2svn $
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 * Revision 1.1  2007/03/09 17:52:17  sybreon
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 * initial import
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 *
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 */
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module aeMB_fetch (/*AUTOARG*/
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   // Outputs
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   iwb_adr_o, rPC, rPCNXT,
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   // Inputs
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   iwb_dat_i, nclk, nrst, frun, rFSM, rBRA, rRESULT
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   );
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   parameter ISIZ = 32;
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   // Instruction WB I/F
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   output [ISIZ-1:0] iwb_adr_o;
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   input [31:0]      iwb_dat_i;
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   // System
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   input             nclk, nrst, frun;
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   // Internal
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   output [31:0]     rPC;
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   output [31:0]     rPCNXT;
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   input [1:0]        rFSM;
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   input             rBRA;
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   input [31:0]      rRESULT;
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   // WB ADR signal
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   reg [31:0]         rIWBADR, rPC;
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   assign            rPCNXT = rIWBADR + 4;
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   assign            iwb_adr_o = {rIWBADR[ISIZ-1:2],2'b00}; // Word Aligned
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   always @(negedge nclk or negedge nrst)
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     if (!nrst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        rIWBADR <= 32'h0;
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        rPC <= 32'h0;
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        // End of automatics
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     end else begin
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        // PC Sources - ALU, Direct, Next
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        case (rFSM)
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          2'b01: rIWBADR <= #1 32'h00000010; // HWINT
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          2'b10: rIWBADR <= #1 32'h00000020; // HWEXC
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          //2'b11: rIWBADR <= #1 32'h00000008; // SWEXC
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          default: rIWBADR <= #1 (rBRA) ? rRESULT : rPCNXT;
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        endcase // case(rFSM)
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        rPC <= #1 {rIWBADR[31:2],2'd0};
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     end // if (frun)
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endmodule // aeMB_fetch
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