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// -*- Mode: Verilog -*-
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// Filename : aeMB_regfile.v
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// Description : AEMB Register File
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Fri Dec 29 16:17:31 2006
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// Last Modified By: $Author: sybreon $
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// Last Modified On: $Date: 2007-04-04 14:08:34 $
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// Update Count : $Revision: 1.5 $
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sybreon |
// Status : $State: Exp $
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sybreon |
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/*
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sybreon |
* $Id: aeMB_regfile.v,v 1.5 2007-04-04 14:08:34 sybreon Exp $
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sybreon |
*
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sybreon |
* AEMB Register File
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sybreon |
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* DESCRIPTION
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* Implements the 32 registers as registers. Some registers require
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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*
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* HISTORY
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* $Log: not supported by cvs2svn $
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sybreon |
* Revision 1.4 2007/04/04 06:11:47 sybreon
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* Fixed memory read-write data hazard
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*
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* Revision 1.3 2007/04/03 14:46:26 sybreon
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* Fixed endian correction issues on data bus.
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*
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* Revision 1.2 2007/03/26 12:21:31 sybreon
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* Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.
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*
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sybreon |
* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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*
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*/
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module aeMB_regfile(/*AUTOARG*/
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// Outputs
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dwb_dat_o, rREGA, rREGB,
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// Inputs
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dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRD_, rRESULT, rFSM,
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rPC, rPCNXT, rLNK, rRWE, nclk, nrst, drun, drst
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);
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// Data WB bus width
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parameter DSIZ = 32;
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// Data WB I/F
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output [31:0] dwb_dat_o;
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input [31:0] dwb_dat_i;
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// Internal I/F
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output [31:0] rREGA, rREGB;
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input rDWBSTB, rDWBWE;
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input [4:0] rRA, rRB, rRD, rRD_;
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input [31:0] rRESULT;
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input [1:0] rFSM;
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input [31:0] rPC, rPCNXT;
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input rLNK, rRWE;
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input nclk, nrst, drun, drst;
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// Register File
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reg [31:0] r00,r01,r02,r03,r04,r05,r06,r07;
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reg [31:0] r08,r09,r0A,r0B,r0C,r0D,r0E,r0F;
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reg [31:0] r10,r11,r12,r13,r14,r15,r16,r17;
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reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;
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// FLAGS
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4 |
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wire fWE = rRWE & ~rDWBWE;
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wire fLNK = rLNK;
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wire fLD = rDWBSTB ^ rDWBWE;
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4 |
sybreon |
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// PC Latch
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reg [31:0] rPC_;
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always @(negedge nclk or negedge nrst)
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if (!nrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rPC_ <= 32'h0;
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// End of automatics
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end else begin
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rPC_ <= #1 rPC;
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end
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// DWB data - Endian Correction
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reg [31:0] rDWBDAT;
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//assign dwb_dat_o = rDWBDAT;
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//wire [31:0] wDWBDAT = dwb_dat_i;
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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wire [31:0] wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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// Forwarding Control
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wire fDFWD = (rRD == rRD_) & fWE;
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wire fMFWD = rDWBSTB & ~rDWBWE;
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wire [31:0] wRESULT = (fMFWD) ? wDWBDAT : rRESULT;
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// Register Load
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always @(negedge nclk or negedge nrst)
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if (!nrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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// End of automatics
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end else if (drun) begin
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case (rRD)
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5'h00: rDWBDAT <= #1 (fDFWD) ? wRESULT : r00;
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5'h01: rDWBDAT <= #1 (fDFWD) ? wRESULT : r01;
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5'h02: rDWBDAT <= #1 (fDFWD) ? wRESULT : r02;
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5'h03: rDWBDAT <= #1 (fDFWD) ? wRESULT : r03;
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5'h04: rDWBDAT <= #1 (fDFWD) ? wRESULT : r04;
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5'h05: rDWBDAT <= #1 (fDFWD) ? wRESULT : r05;
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5'h06: rDWBDAT <= #1 (fDFWD) ? wRESULT : r06;
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5'h07: rDWBDAT <= #1 (fDFWD) ? wRESULT : r07;
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5'h08: rDWBDAT <= #1 (fDFWD) ? wRESULT : r08;
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5'h09: rDWBDAT <= #1 (fDFWD) ? wRESULT : r09;
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5'h0A: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0A;
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5'h0B: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0B;
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5'h0C: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0C;
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5'h0D: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0D;
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5'h0E: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0E;
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5'h0F: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0F;
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5'h10: rDWBDAT <= #1 (fDFWD) ? wRESULT : r10;
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5'h11: rDWBDAT <= #1 (fDFWD) ? wRESULT : r11;
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5'h12: rDWBDAT <= #1 (fDFWD) ? wRESULT : r12;
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5'h13: rDWBDAT <= #1 (fDFWD) ? wRESULT : r13;
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5'h14: rDWBDAT <= #1 (fDFWD) ? wRESULT : r14;
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5'h15: rDWBDAT <= #1 (fDFWD) ? wRESULT : r15;
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5'h16: rDWBDAT <= #1 (fDFWD) ? wRESULT : r16;
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5'h17: rDWBDAT <= #1 (fDFWD) ? wRESULT : r17;
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5'h18: rDWBDAT <= #1 (fDFWD) ? wRESULT : r18;
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5'h19: rDWBDAT <= #1 (fDFWD) ? wRESULT : r19;
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5'h1A: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1A;
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5'h1B: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1B;
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5'h1C: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1C;
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5'h1D: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1D;
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5'h1E: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1E;
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5'h1F: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1F;
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4 |
sybreon |
endcase // case (rRD)
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3 |
sybreon |
end else begin // if (drun)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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// End of automatics
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4 |
sybreon |
end // else: !if(drun)
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sybreon |
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3 |
sybreon |
// Load Registers
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reg [31:0] rREGA, rREGB;
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always @(posedge nclk or negedge nrst)
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if (!nrst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rREGA <= 32'h0;
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rREGB <= 32'h0;
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// End of automatics
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end else if (drun) begin
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case (rRA)
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5'h1F: rREGA <= #1 r1F;
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5'h1E: rREGA <= #1 r1E;
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5'h1D: rREGA <= #1 r1D;
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5'h1C: rREGA <= #1 r1C;
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5'h1B: rREGA <= #1 r1B;
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5'h1A: rREGA <= #1 r1A;
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5'h19: rREGA <= #1 r19;
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5'h18: rREGA <= #1 r18;
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5'h17: rREGA <= #1 r17;
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5'h16: rREGA <= #1 r16;
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5'h15: rREGA <= #1 r15;
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5'h14: rREGA <= #1 r14;
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5'h13: rREGA <= #1 r13;
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5'h12: rREGA <= #1 r12;
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5'h11: rREGA <= #1 r11;
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5'h10: rREGA <= #1 r10;
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5'h0F: rREGA <= #1 r0F;
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5'h0E: rREGA <= #1 r0E;
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5'h0D: rREGA <= #1 r0D;
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5'h0C: rREGA <= #1 r0C;
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5'h0B: rREGA <= #1 r0B;
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5'h0A: rREGA <= #1 r0A;
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5'h09: rREGA <= #1 r09;
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5'h08: rREGA <= #1 r08;
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5'h07: rREGA <= #1 r07;
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5'h06: rREGA <= #1 r06;
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5'h05: rREGA <= #1 r05;
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5'h04: rREGA <= #1 r04;
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5'h03: rREGA <= #1 r03;
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5'h02: rREGA <= #1 r02;
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5'h01: rREGA <= #1 r01;
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5'h00: rREGA <= #1 r00;
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4 |
sybreon |
endcase // case (rRA)
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3 |
sybreon |
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case (rRB)
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5'h1F: rREGB <= #1 r1F;
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5'h1E: rREGB <= #1 r1E;
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5'h1D: rREGB <= #1 r1D;
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5'h1C: rREGB <= #1 r1C;
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5'h1B: rREGB <= #1 r1B;
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5'h1A: rREGB <= #1 r1A;
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5'h19: rREGB <= #1 r19;
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5'h18: rREGB <= #1 r18;
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5'h17: rREGB <= #1 r17;
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5'h16: rREGB <= #1 r16;
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5'h15: rREGB <= #1 r15;
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5'h14: rREGB <= #1 r14;
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5'h13: rREGB <= #1 r13;
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5'h12: rREGB <= #1 r12;
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5'h11: rREGB <= #1 r11;
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5'h10: rREGB <= #1 r10;
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5'h0F: rREGB <= #1 r0F;
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5'h0E: rREGB <= #1 r0E;
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5'h0D: rREGB <= #1 r0D;
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5'h0C: rREGB <= #1 r0C;
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5'h0B: rREGB <= #1 r0B;
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5'h0A: rREGB <= #1 r0A;
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5'h09: rREGB <= #1 r09;
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5'h08: rREGB <= #1 r08;
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5'h07: rREGB <= #1 r07;
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5'h06: rREGB <= #1 r06;
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5'h05: rREGB <= #1 r05;
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5'h04: rREGB <= #1 r04;
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5'h03: rREGB <= #1 r03;
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5'h02: rREGB <= #1 r02;
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5'h01: rREGB <= #1 r01;
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5'h00: rREGB <= #1 r00;
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4 |
sybreon |
endcase // case (rRB)
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| 239 |
3 |
sybreon |
end else begin // if (drun)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rREGA <= 32'h0;
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rREGB <= 32'h0;
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// End of automatics
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4 |
sybreon |
end // else: !if(drun)
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| 246 |
3 |
sybreon |
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| 247 |
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// Normal Registers
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wire fR00 = (rRD_ == 5'h00);
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| 250 |
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wire fR01 = (rRD_ == 5'h01);
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| 251 |
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wire fR02 = (rRD_ == 5'h02);
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| 252 |
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wire fR03 = (rRD_ == 5'h03);
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| 253 |
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wire fR04 = (rRD_ == 5'h04);
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| 254 |
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wire fR05 = (rRD_ == 5'h05);
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| 255 |
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wire fR06 = (rRD_ == 5'h06);
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| 256 |
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wire fR07 = (rRD_ == 5'h07);
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| 257 |
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wire fR08 = (rRD_ == 5'h08);
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| 258 |
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wire fR09 = (rRD_ == 5'h09);
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| 259 |
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wire fR0A = (rRD_ == 5'h0A);
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| 260 |
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wire fR0B = (rRD_ == 5'h0B);
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| 261 |
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wire fR0C = (rRD_ == 5'h0C);
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| 262 |
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wire fR0D = (rRD_ == 5'h0D);
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| 263 |
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wire fR0E = (rRD_ == 5'h0E);
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| 264 |
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wire fR0F = (rRD_ == 5'h0F);
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| 265 |
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wire fR10 = (rRD_ == 5'h10);
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| 266 |
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wire fR11 = (rRD_ == 5'h11);
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| 267 |
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wire fR12 = (rRD_ == 5'h12);
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| 268 |
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wire fR13 = (rRD_ == 5'h13);
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| 269 |
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wire fR14 = (rRD_ == 5'h14);
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| 270 |
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wire fR15 = (rRD_ == 5'h15);
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| 271 |
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wire fR16 = (rRD_ == 5'h16);
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| 272 |
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wire fR17 = (rRD_ == 5'h17);
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| 273 |
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wire fR18 = (rRD_ == 5'h18);
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| 274 |
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wire fR19 = (rRD_ == 5'h19);
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| 275 |
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wire fR1A = (rRD_ == 5'h1A);
|
| 276 |
|
|
wire fR1B = (rRD_ == 5'h1B);
|
| 277 |
|
|
wire fR1C = (rRD_ == 5'h1C);
|
| 278 |
|
|
wire fR1D = (rRD_ == 5'h1D);
|
| 279 |
|
|
wire fR1E = (rRD_ == 5'h1E);
|
| 280 |
|
|
wire fR1F = (rRD_ == 5'h1F);
|
| 281 |
|
|
|
| 282 |
|
|
always @(negedge nclk or negedge nrst)
|
| 283 |
|
|
if (!nrst) begin
|
| 284 |
|
|
/*AUTORESET*/
|
| 285 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 286 |
|
|
r01 <= 32'h0;
|
| 287 |
|
|
r02 <= 32'h0;
|
| 288 |
|
|
r03 <= 32'h0;
|
| 289 |
|
|
r04 <= 32'h0;
|
| 290 |
|
|
r05 <= 32'h0;
|
| 291 |
|
|
r06 <= 32'h0;
|
| 292 |
|
|
r07 <= 32'h0;
|
| 293 |
|
|
r08 <= 32'h0;
|
| 294 |
|
|
r09 <= 32'h0;
|
| 295 |
|
|
r0A <= 32'h0;
|
| 296 |
|
|
r0B <= 32'h0;
|
| 297 |
|
|
r0C <= 32'h0;
|
| 298 |
|
|
r0D <= 32'h0;
|
| 299 |
|
|
r0F <= 32'h0;
|
| 300 |
|
|
r10 <= 32'h0;
|
| 301 |
|
|
r12 <= 32'h0;
|
| 302 |
|
|
r13 <= 32'h0;
|
| 303 |
|
|
r14 <= 32'h0;
|
| 304 |
|
|
r15 <= 32'h0;
|
| 305 |
|
|
r16 <= 32'h0;
|
| 306 |
|
|
r17 <= 32'h0;
|
| 307 |
|
|
r18 <= 32'h0;
|
| 308 |
|
|
r19 <= 32'h0;
|
| 309 |
|
|
r1A <= 32'h0;
|
| 310 |
|
|
r1B <= 32'h0;
|
| 311 |
|
|
r1C <= 32'h0;
|
| 312 |
|
|
r1D <= 32'h0;
|
| 313 |
|
|
r1E <= 32'h0;
|
| 314 |
|
|
r1F <= 32'h0;
|
| 315 |
|
|
// End of automatics
|
| 316 |
|
|
end else begin // if (!nrst)
|
| 317 |
|
|
r01 <= #1 (!fR01) ? r01 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r01;
|
| 318 |
|
|
r02 <= #1 (!fR02) ? r02 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r02;
|
| 319 |
|
|
r03 <= #1 (!fR03) ? r03 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r03;
|
| 320 |
|
|
r04 <= #1 (!fR04) ? r04 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r04;
|
| 321 |
|
|
r05 <= #1 (!fR05) ? r05 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r05;
|
| 322 |
|
|
r06 <= #1 (!fR06) ? r06 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r06;
|
| 323 |
|
|
r07 <= #1 (!fR07) ? r07 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r07;
|
| 324 |
|
|
r08 <= #1 (!fR08) ? r08 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r08;
|
| 325 |
|
|
r09 <= #1 (!fR09) ? r09 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r09;
|
| 326 |
|
|
r0A <= #1 (!fR0A) ? r0A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0A;
|
| 327 |
|
|
r0B <= #1 (!fR0B) ? r0B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0B;
|
| 328 |
|
|
r0C <= #1 (!fR0C) ? r0C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0C;
|
| 329 |
|
|
r0D <= #1 (!fR0D) ? r0D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0D;
|
| 330 |
|
|
r0F <= #1 (!fR0F) ? r0F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0F;
|
| 331 |
|
|
r10 <= #1 (!fR10) ? r10 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r10;
|
| 332 |
|
|
r12 <= #1 (!fR12) ? r12 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r12;
|
| 333 |
14 |
sybreon |
r13 <= #1 (!fR13) ? r13 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r13;
|
| 334 |
|
|
r14 <= #1 (!fR14) ? r14 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r14;
|
| 335 |
3 |
sybreon |
r15 <= #1 (!fR15) ? r15 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r15;
|
| 336 |
14 |
sybreon |
r16 <= #1 (!fR16) ? r16 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r16;
|
| 337 |
|
|
r17 <= #1 (!fR17) ? r17 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r17;
|
| 338 |
3 |
sybreon |
r18 <= #1 (!fR18) ? r18 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r18;
|
| 339 |
|
|
r19 <= #1 (!fR19) ? r19 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r19;
|
| 340 |
|
|
r1A <= #1 (!fR1A) ? r1A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1A;
|
| 341 |
|
|
r1B <= #1 (!fR1B) ? r1B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1B;
|
| 342 |
|
|
r1C <= #1 (!fR1C) ? r1C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1C;
|
| 343 |
|
|
r1D <= #1 (!fR1D) ? r1D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1D;
|
| 344 |
|
|
r1E <= #1 (!fR1E) ? r1E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1E;
|
| 345 |
|
|
r1F <= #1 (!fR1F) ? r1F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r1F;
|
| 346 |
|
|
|
| 347 |
4 |
sybreon |
end // else: !if(!nrst)
|
| 348 |
3 |
sybreon |
|
| 349 |
|
|
// Special Registers
|
| 350 |
|
|
always @(negedge nclk or negedge nrst)
|
| 351 |
|
|
if (!nrst) begin
|
| 352 |
|
|
/*AUTORESET*/
|
| 353 |
|
|
// Beginning of autoreset for uninitialized flops
|
| 354 |
|
|
r00 <= 32'h0;
|
| 355 |
|
|
r0E <= 32'h0;
|
| 356 |
|
|
r11 <= 32'h0;
|
| 357 |
|
|
// End of automatics
|
| 358 |
|
|
end else begin
|
| 359 |
|
|
// R00 - Zero
|
| 360 |
|
|
r00 <= #1 r00;
|
| 361 |
|
|
// R0E - Interrupt
|
| 362 |
14 |
sybreon |
r0E <= #1 (rFSM == 2'b01) ? rPCNXT :
|
| 363 |
3 |
sybreon |
(!fR0E) ? r0E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0E;
|
| 364 |
|
|
// R11 - Exception
|
| 365 |
14 |
sybreon |
r11 <= #1 (rFSM == 2'b10) ? rPCNXT :
|
| 366 |
3 |
sybreon |
(!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11;
|
| 367 |
4 |
sybreon |
end // else: !if(!nrst)
|
| 368 |
5 |
sybreon |
|
| 369 |
|
|
// Simulation ONLY
|
| 370 |
|
|
always @(negedge nclk) begin
|
| 371 |
14 |
sybreon |
if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_== 5'd0))) $displayh("!!! Warning: Write to R0 !!!");
|
| 372 |
|
|
end
|
| 373 |
|
|
|
| 374 |
3 |
sybreon |
endmodule // aeMB_regfile
|
| 375 |
|
|
|
| 376 |
|
|
// Local Variables:
|
| 377 |
|
|
// verilog-library-directories:(".")
|
| 378 |
|
|
// verilog-library-files:("")
|
| 379 |
|
|
// End:
|
