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sybreon |
/*
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* $Id: aeMB_ucore.v,v 1.1 2007-04-13 13:02:34 sybreon Exp $
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*
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* AEMB Unified 32-bit Microprocessor Core
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* Copyright (C) 2006-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* DESCRIPTION
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* This is the top level core with integrated cache and unified memory.
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*
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* HISTORY
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* $Log: not supported by cvs2svn $
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*/
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// 691@60
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module aeMB_ucore (/*AUTOARG*/
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// Outputs
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wb_wre_o, wb_stb_o, wb_sel_o, wb_dat_o, wb_adr_o,
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// Inputs
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wb_dat_i, wb_ack_i, sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i
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);
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/* Bus Address Width */
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parameter ASIZ = 32;
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parameter CSIZ = 7;
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/* DO NOT TOUCH */
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parameter DSIZ = ASIZ;
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parameter ISIZ = ASIZ;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [ASIZ-1:0] wb_adr_o; // From wbbus of aeMB_wbbus.v
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output [31:0] wb_dat_o; // From wbbus of aeMB_wbbus.v
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output [3:0] wb_sel_o; // From wbbus of aeMB_wbbus.v
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output wb_stb_o; // From wbbus of aeMB_wbbus.v
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output wb_wre_o; // From wbbus of aeMB_wbbus.v
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// End of automatics
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input sys_clk_i; // To wbbus of aeMB_wbbus.v, ...
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input sys_exc_i; // To cpu of aeMB_core.v
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input sys_int_i; // To cpu of aeMB_core.v
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input sys_rst_i; // To wbbus of aeMB_wbbus.v, ...
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input wb_ack_i; // To wbbus of aeMB_wbbus.v
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input [31:0] wb_dat_i; // To wbbus of aeMB_wbbus.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire dwb_ack_i; // From wbbus of aeMB_wbbus.v
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wire [DSIZ-1:0] dwb_adr_o; // From cpu of aeMB_core.v
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wire [31:0] dwb_dat_i; // From wbbus of aeMB_wbbus.v
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wire [31:0] dwb_dat_o; // From cpu of aeMB_core.v
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wire dwb_stb_o; // From cpu of aeMB_core.v
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wire dwb_we_o; // From cpu of aeMB_core.v
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wire iwb_ack_i; // From wbbus of aeMB_wbbus.v
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wire [ISIZ-1:0] iwb_adr_o; // From cpu of aeMB_core.v
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wire [31:0] iwb_dat_i; // From wbbus of aeMB_wbbus.v
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wire iwb_stb_o; // From cpu of aeMB_core.v
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// End of automatics
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aeMB_wbbus #(ASIZ, CSIZ, ISIZ, DSIZ)
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wbbus (/*AUTOINST*/
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// Outputs
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.wb_adr_o (wb_adr_o[ASIZ-1:0]),
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.wb_dat_o (wb_dat_o[31:0]),
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.wb_sel_o (wb_sel_o[3:0]),
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.wb_stb_o (wb_stb_o),
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.wb_wre_o (wb_wre_o),
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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// Inputs
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.wb_dat_i (wb_dat_i[31:0]),
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.wb_ack_i (wb_ack_i),
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.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
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.iwb_stb_o (iwb_stb_o),
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.sys_clk_i (sys_clk_i),
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.sys_rst_i (sys_rst_i));
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aeMB_core #(ISIZ, DSIZ)
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cpu (/*AUTOINST*/
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// Outputs
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.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
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.iwb_stb_o (iwb_stb_o),
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// Inputs
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.sys_clk_i (sys_clk_i),
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.sys_exc_i (sys_exc_i),
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.sys_int_i (sys_int_i),
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.sys_rst_i (sys_rst_i));
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endmodule // aeMB_ucore
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