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/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $
**
** FASM MEMORY LIBRARY
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net>
** All rights reserved.
**
** FASM is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** FASM is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>.
*/
/*
 * DUAL PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE
 * Synthesis proven on:
 * - Xilinx ISE
 * - Altera Quartus (>=8.0)
 */
 
module fasm_dpsram_rbw (/*AUTOARG*/
   // Outputs
   dat_o, xdat_o,
   // Inputs
   dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i,
   xstb_i, xrst_i, xclk_i
   );
 
   parameter AW = 8;  ///< address space (2^AW) words
   parameter DW = 32; ///< data word width bits
 
   // wishbone port a
   output [DW-1:0] dat_o; // DO
   input [DW-1:0]  dat_i; // DI
   input [AW-1:0]  adr_i; // A
   input           wre_i; // WE
   input           stb_i; // CS
 
   input           rst_i,
                   clk_i;
 
   // wishbone port x
   output [DW-1:0] xdat_o; // DO
   input [DW-1:0]  xdat_i; // DI
   input [AW-1:0]  xadr_i; // A
   input           xwre_i; // WE
   input           xstb_i; // CS
 
   input           xrst_i,
                   xclk_i;
 
   // address latch
   reg [AW-1:0]    rA, rX;
 
   // memory block
   reg [DW-1:0]    bram [(1<<AW)-1:0];
 
   always @(posedge xclk_i)
     if (xstb_i)
       begin
          rX <= #1 bram[xadr_i];
          if (xwre_i) // strobe and write-enable
            bram[xadr_i] <= #1 xdat_i;
       end
   always @(posedge clk_i)
     if (stb_i)
       begin
          rA <= #1 bram[adr_i];
          if (wre_i) // strobe and write-enable
            bram[adr_i] <= #1 dat_i;
       end
 
   assign          xdat_o = rX; // write-thru
   assign          dat_o = rA; // write-thru
 
   // ### SIMULATION ONLY ###
   // synopsys translate_off
   integer i;
   initial begin
      for (i=0; i<(1<<AW); i=i+1) begin
         bram[i] <= $random;
      end
   end
   // synopsys translate_on
 
endmodule // fasm_dpsram_rbw

Line No.	Rev	Author	Line
1	195	sybreon	`/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $`
2			`**`
3			`** FASM MEMORY LIBRARY`
4			`** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net>`
5			`** All rights reserved.`
6			`**`
7			`** FASM is free software: you can redistribute it and/or modify it`
8			`** under the terms of the GNU Lesser General Public License as`
9			`** published by the Free Software Foundation, either version 3 of the`
10			`** License, or (at your option) any later version.`
11			`**`
12			`** FASM is distributed in the hope that it will be useful, but WITHOUT`
13			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
14			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
15			`** Public License for more details.`
16			`**`
17			`** You should have received a copy of the GNU Lesser General Public`
18			` License along with FASM. If not, see <http:www.gnu.org/licenses/>.`
19			`*/`
20			`/*`
21			`* DUAL PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE`
22			`* Synthesis proven on:`
23			`* - Xilinx ISE`
24			`* - Altera Quartus (>=8.0)`
25			`*/`
26
27			`module fasm_dpsram_rbw (/AUTOARG/`
28			`// Outputs`
29			`dat_o, xdat_o,`
30			`// Inputs`
31			`dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i,`
32			`xstb_i, xrst_i, xclk_i`
33			`);`
34
35			`parameter AW = 8; ///< address space (2^AW) words`
36			`parameter DW = 32; ///< data word width bits`
37
38			`// wishbone port a`
39			`output [DW-1:0] dat_o; // DO`
40			`input [DW-1:0] dat_i; // DI`
41			`input [AW-1:0] adr_i; // A`
42			`input wre_i; // WE`
43			`input stb_i; // CS`
44
45			`input rst_i,`
46			`clk_i;`
47
48			`// wishbone port x`
49			`output [DW-1:0] xdat_o; // DO`
50			`input [DW-1:0] xdat_i; // DI`
51			`input [AW-1:0] xadr_i; // A`
52			`input xwre_i; // WE`
53			`input xstb_i; // CS`
54
55			`input xrst_i,`
56			`xclk_i;`
57
58			`// address latch`
59			`reg [AW-1:0] rA, rX;`
60
61			`// memory block`
62			`reg [DW-1:0] bram [(1<<AW)-1:0];`
63
64			`always @(posedge xclk_i)`
65			`if (xstb_i)`
66			`begin`
67			`rX <= #1 bram[xadr_i];`
68			`if (xwre_i) // strobe and write-enable`
69			`bram[xadr_i] <= #1 xdat_i;`
70			`end`
71			`always @(posedge clk_i)`
72			`if (stb_i)`
73			`begin`
74			`rA <= #1 bram[adr_i];`
75			`if (wre_i) // strobe and write-enable`
76			`bram[adr_i] <= #1 dat_i;`
77			`end`
78
79			`assign xdat_o = rX; // write-thru`
80			`assign dat_o = rA; // write-thru`
81
82			`// ### SIMULATION ONLY ###`
83			`// synopsys translate_off`
84			`integer i;`
85			`initial begin`
86			`for (i=0; i<(1<<AW); i=i+1) begin`
87			`bram[i] <= $random;`
88			`end`
89			`end`
90			`// synopsys translate_on`
91
92			`endmodule // fasm_dpsram_rbw`

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[/] [aemb/] [trunk/] [lib/] [fasm/] [fasm_dpsram_rbw.v] - Blame information for rev 195