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[/] [aemb/] [trunk/] [lib/] [fasm/] [fasm_dpsram_rbw.v] - Blame information for rev 195

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1 195 sybreon
/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $
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**
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** FASM MEMORY LIBRARY
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** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net>
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** All rights reserved.
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**
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** FASM is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** FASM is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with FASM. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/*
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 * DUAL PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE
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 * Synthesis proven on:
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 * - Xilinx ISE
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 * - Altera Quartus (>=8.0)
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 */
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module fasm_dpsram_rbw (/*AUTOARG*/
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   // Outputs
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   dat_o, xdat_o,
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   // Inputs
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   dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i,
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   xstb_i, xrst_i, xclk_i
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   );
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   parameter AW = 8;  ///< address space (2^AW) words
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   parameter DW = 32; ///< data word width bits
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   // wishbone port a
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   output [DW-1:0] dat_o; // DO
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   input [DW-1:0]  dat_i; // DI
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   input [AW-1:0]  adr_i; // A
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   input           wre_i; // WE
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   input           stb_i; // CS
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   input           rst_i,
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                   clk_i;
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   // wishbone port x
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   output [DW-1:0] xdat_o; // DO
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   input [DW-1:0]  xdat_i; // DI
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   input [AW-1:0]  xadr_i; // A
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   input           xwre_i; // WE
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   input           xstb_i; // CS
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   input           xrst_i,
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                   xclk_i;
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   // address latch
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   reg [AW-1:0]    rA, rX;
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   // memory block
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   reg [DW-1:0]    bram [(1<<AW)-1:0];
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   always @(posedge xclk_i)
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     if (xstb_i)
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       begin
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          rX <= #1 bram[xadr_i];
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          if (xwre_i) // strobe and write-enable
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            bram[xadr_i] <= #1 xdat_i;
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       end
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   always @(posedge clk_i)
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     if (stb_i)
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       begin
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          rA <= #1 bram[adr_i];
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          if (wre_i) // strobe and write-enable
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            bram[adr_i] <= #1 dat_i;
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       end
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   assign          xdat_o = rX; // write-thru
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   assign          dat_o = rA; // write-thru
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   // ### SIMULATION ONLY ###
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   // synopsys translate_off
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   integer i;
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   initial begin
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      for (i=0; i<(1<<AW); i=i+1) begin
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         bram[i] <= $random;
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      end
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   end
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   // synopsys translate_on
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endmodule // fasm_dpsram_rbw

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