URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Blame information for rev 118

Go to most recent revision | Details | Compare with Previous | View Log


/* $Id: aeMB2_ctrl.v,v 1.1 2008-04-18 00:21:52 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
 
/**
 * Instruction Decode & Control
 * @file aeMB2_ctrl.v
 
 * This is the data decoder that will control the command signals and
   operand fetch.
 
 */
 
module aeMB2_ctrl (/*AUTOARG*/
   // Outputs
   opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
   mux_of, mux_ex, hzd_bpc, hzd_fwd,
   // Inputs
   opa_if, opb_if, opd_if, bra_ex, rpc_if, alu_ex, ich_dat, gclk,
   grst, dena, iena, gpha
   );
   parameter AEMB_HTX = 1;
 
   // EX CONTROL
   output [31:0] opa_of;
   output [31:0] opb_of;
   output [31:0] opd_of;
   output [5:0]  opc_of;
   output [4:0]  ra_of,
                 //rb_of,
                 rd_of;
   output [15:0] imm_of;
   output [4:0]   rd_ex;
 
   // REGS
   input [31:0]  opa_if,
                 opb_if,
                 opd_if;
 
   // WB CONTROL
   output [2:0]  mux_of,
                 mux_ex;
 
   // INTERNAL
   input [1:0]    bra_ex;
   input [31:2]  rpc_if;
   input [31:0]  alu_ex;
   input [31:0]  ich_dat;
 
   output        hzd_bpc;
   output        hzd_fwd;
 
   // SYSTEM
   input         gclk,
                 grst,
                 dena,
                 iena,
                 gpha;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [15:0]            imm_of;
   reg [2:0]             mux_ex;
   reg [2:0]             mux_of;
   reg [31:0]            opa_of;
   reg [31:0]            opb_of;
   reg [5:0]             opc_of;
   reg [31:0]            opd_of;
   reg [4:0]             ra_of;
   reg [4:0]             rd_ex;
   reg [4:0]             rd_of;
   // End of automatics
 
   wire [1:0]            mux_opa, mux_opb, mux_opd;
 
   // translate signals
   wire [4:0]            wRD, wRA, wRB;
   wire [5:0]            wOPC;
   wire [15:0]           wIMM;
   wire [31:0]           imm_if;
 
   assign               {wOPC, wRD, wRA, wIMM} = ich_dat;
   assign               wRB = wIMM[15:11];
 
   // decode main opgroups
 
   wire                 fSFT = (wOPC == 6'o44);
   wire                 fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
   wire                 fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire                 fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   wire                 fDIV = (wOPC == 6'o22);
   wire                 fRTD = (wOPC == 6'o55);
   wire                 fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire                 fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   wire                 fBRA = fBRU & wRA[3];
   wire                 fIMM = (wOPC == 6'o54);
   wire                 fMOV = (wOPC == 6'o45);
   wire                 fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire                 fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   wire                 fLDST = (wOPC[5:4] == 2'o3);
   wire                 fPUT = (wOPC == 6'o33) & wRB[4];
   wire                 fGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // control signals
   wire [31:0]           wXCEOP = 32'hBA2D0020; // Vector 0x20
   wire [31:0]           wINTOP = 32'hB9CE0010; // Vector 0x10   
   wire [31:0]           wNOPOP = 32'h88000000; // branch-no-delay/stall
 
   localparam [2:0]      MUX_ALU = 3'o7,
                        MUX_SFR = 3'o5,
                        MUX_BSF = 3'o4,
                        MUX_MUL = 3'o3,
                        MUX_MEM = 3'o2,
                        MUX_RPC = 3'o1,
                        MUX_NOP = 3'o0;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        imm_of <= 16'h0;
        mux_of <= 3'h0;
        opc_of <= 6'h0;
        ra_of <= 5'h0;
        rd_of <= 5'h0;
        // End of automatics
     end else if (dena) begin
 
        mux_of <= #1
                  (hzd_bpc | hzd_fwd) ? MUX_NOP :
                  (fMOV) ? MUX_SFR :
                  (fMUL) ? MUX_MUL :
                  (fBSF) ? MUX_BSF :
                  (fLOD | fGET) ? MUX_MEM :
                  (fBRU) ? MUX_RPC :
                  (fSTR | fRTD | fBCC) ? MUX_NOP :
                  (|wRD) ? MUX_ALU :
                  MUX_NOP;
 
        opc_of <= #1
                  (hzd_bpc | hzd_fwd) ? 6'o42 :
                  wOPC;
 
        rd_of <= #1 wRD;
        ra_of <= #1 wRA;
        //rb_of <= #1 wRB;
        imm_of <= #1 wIMM;
 
     end
 
 
   // immediate implementation
   reg [15:0]            rIMM0, rIMM1;
   reg                  rFIM0, rFIM1;
   wire                 wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
   wire [15:0]           wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
 
   assign               imm_if[15:0] = wIMM;
   assign               imm_if[31:16] = (wFIMH) ? wIMMH :
                                        {(16){wIMM[15]}};
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFIM0 <= 1'h0;
        rFIM1 <= 1'h0;
        rIMM0 <= 16'h0;
        rIMM1 <= 16'h0;
        // End of automatics
     end else if (dena) begin
        if (gpha) begin
           rFIM1 <= #1 fIMM & !hzd_bpc;
           rIMM1 <= #1 wIMM;
        end else begin
           rFIM0 <= #1 fIMM & !hzd_bpc;
           rIMM0 <= #1 wIMM;
        end
     end
 
 
   // operand latch   
   reg                  wrb_ex;
   reg                  fwd_ex;
 
   wire                 opb_fwd, opa_fwd, opd_fwd;
 
   assign               mux_opb = {wOPC[3], opb_fwd};
   assign               opb_fwd = (wRB == rd_ex) &
                                  fwd_ex & wrb_ex;
 
   assign               mux_opa = {(fBRU|fBCC), opa_fwd};
   assign               opa_fwd = (wRA == rd_ex) &
                                  fwd_ex & wrb_ex;
 
   assign               mux_opd = {fBCC, opd_fwd};
   assign               opd_fwd = (((wRA == rd_ex) & fBCC) |
                                   ((wRD == rd_ex) & fSTR)) &
                                  fwd_ex & wrb_ex;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        fwd_ex <= 1'h0;
        mux_ex <= 3'h0;
        rd_ex <= 5'h0;
        wrb_ex <= 1'h0;
        // End of automatics
     end else if (dena) begin
        wrb_ex <= #1 |rd_of & |mux_of; // FIXME: check mux      
        fwd_ex <= #1 |mux_of; // FIXME: check mux
 
        mux_ex <= #1 mux_of;
        rd_ex <= #1 rd_of;
     end
 
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        opa_of <= 32'h0;
        opb_of <= 32'h0;
        opd_of <= 32'h0;
        // End of automatics
 
     end else if (dena) begin
 
        case (mux_opd)
          2'o2: opd_of <= #1 opa_if; // BCC
          2'o1: opd_of <= #1 alu_ex; // FWD
          2'o0: opd_of <= #1 opd_if; // SXX
          2'o3: opd_of <= #1 alu_ex; // FWD               
        endcase // case (mux_opd)       
 
        case (mux_opb)
          2'o0: opb_of <= #1 opb_if;
          2'o1: opb_of <= #1 alu_ex;
          2'o2: opb_of <= #1 imm_if;
          2'o3: opb_of <= #1 imm_if;
          //default: 32'hX;
        endcase // case (mux_opb)       
 
        case (mux_opa)
          2'o0: opa_of <= #1 opa_if;
          2'o1: opa_of <= #1 alu_ex;
          2'o2: opa_of <= #1 {rpc_if, 2'o0};
          2'o3: opa_of <= #1 {rpc_if, 2'o0};
        endcase // case (mux_opa)       
 
     end
 
   // Hazard Detection
   wire                 wFMUL = (mux_ex == MUX_MUL);
   wire                 wFBSF = (mux_ex == MUX_BSF);
   wire                 wFMEM = (mux_ex == MUX_MEM);
   wire                 wFMOV = (mux_ex == MUX_SFR);
 
   assign               hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) &
                                  (wFMUL | wFBSF | wFMEM | wFMOV);
   assign               hzd_bpc = (bra_ex[1] & !bra_ex[0]);
 
endmodule // aeMB2_ctrl
 
// $Log: not supported by cvs2svn $

Browse

Tools

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Blame information for rev 118

Line No.	Rev	Author	Line
1	118	sybreon	`/* $Id: aeMB2_ctrl.v,v 1.1 2008-04-18 00:21:52 sybreon Exp $`
2			`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21
22			`/**`
23			`* Instruction Decode & Control`
24			`* @file aeMB2_ctrl.v`
25
26			`* This is the data decoder that will control the command signals and`
27			`operand fetch.`
28
29			`*/`
30
31			`module aeMB2_ctrl (/AUTOARG/`
32			`// Outputs`
33			`opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,`
34			`mux_of, mux_ex, hzd_bpc, hzd_fwd,`
35			`// Inputs`
36			`opa_if, opb_if, opd_if, bra_ex, rpc_if, alu_ex, ich_dat, gclk,`
37			`grst, dena, iena, gpha`
38			`);`
39			`parameter AEMB_HTX = 1;`
40
41			`// EX CONTROL`
42			`output [31:0] opa_of;`
43			`output [31:0] opb_of;`
44			`output [31:0] opd_of;`
45			`output [5:0] opc_of;`
46			`output [4:0] ra_of,`
47			`//rb_of,`
48			`rd_of;`
49			`output [15:0] imm_of;`
50			`output [4:0] rd_ex;`
51
52			`// REGS`
53			`input [31:0] opa_if,`
54			`opb_if,`
55			`opd_if;`
56
57			`// WB CONTROL`
58			`output [2:0] mux_of,`
59			`mux_ex;`
60
61			`// INTERNAL`
62			`input [1:0] bra_ex;`
63			`input [31:2] rpc_if;`
64			`input [31:0] alu_ex;`
65			`input [31:0] ich_dat;`
66
67			`output hzd_bpc;`
68			`output hzd_fwd;`
69
70			`// SYSTEM`
71			`input gclk,`
72			`grst,`
73			`dena,`
74			`iena,`
75			`gpha;`
76
77			`/AUTOREG/`
78			`// Beginning of automatic regs (for this module's undeclared outputs)`
79			`reg [15:0] imm_of;`
80			`reg [2:0] mux_ex;`
81			`reg [2:0] mux_of;`
82			`reg [31:0] opa_of;`
83			`reg [31:0] opb_of;`
84			`reg [5:0] opc_of;`
85			`reg [31:0] opd_of;`
86			`reg [4:0] ra_of;`
87			`reg [4:0] rd_ex;`
88			`reg [4:0] rd_of;`
89			`// End of automatics`
90
91			`wire [1:0] mux_opa, mux_opb, mux_opd;`
92
93			`// translate signals`
94			`wire [4:0] wRD, wRA, wRB;`
95			`wire [5:0] wOPC;`
96			`wire [15:0] wIMM;`
97			`wire [31:0] imm_if;`
98
99			`assign {wOPC, wRD, wRA, wIMM} = ich_dat;`
100			`assign wRB = wIMM[15:11];`
101
102			`// decode main opgroups`
103
104			`wire fSFT = (wOPC == 6'o44);`
105			`wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
106			`wire fMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
107			`wire fBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
108			`wire fDIV = (wOPC == 6'o22);`
109			`wire fRTD = (wOPC == 6'o55);`
110			`wire fBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
111			`wire fBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
112			`wire fBRA = fBRU & wRA[3];`
113			`wire fIMM = (wOPC == 6'o54);`
114			`wire fMOV = (wOPC == 6'o45);`
115			`wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
116			`wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
117			`wire fLDST = (wOPC[5:4] == 2'o3);`
118			`wire fPUT = (wOPC == 6'o33) & wRB[4];`
119			`wire fGET = (wOPC == 6'o33) & !wRB[4];`
120
121
122			`// control signals`
123			`wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20`
124			`wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10`
125			`wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall`
126
127			`localparam [2:0] MUX_ALU = 3'o7,`
128			`MUX_SFR = 3'o5,`
129			`MUX_BSF = 3'o4,`
130			`MUX_MUL = 3'o3,`
131			`MUX_MEM = 3'o2,`
132			`MUX_RPC = 3'o1,`
133			`MUX_NOP = 3'o0;`
134
135			`always @(posedge gclk)`
136			`if (grst) begin`
137			`/AUTORESET/`
138			`// Beginning of autoreset for uninitialized flops`
139			`imm_of <= 16'h0;`
140			`mux_of <= 3'h0;`
141			`opc_of <= 6'h0;`
142			`ra_of <= 5'h0;`
143			`rd_of <= 5'h0;`
144			`// End of automatics`
145			`end else if (dena) begin`
146
147			`mux_of <= #1`
148			`(hzd_bpc \| hzd_fwd) ? MUX_NOP :`
149			`(fMOV) ? MUX_SFR :`
150			`(fMUL) ? MUX_MUL :`
151			`(fBSF) ? MUX_BSF :`
152			`(fLOD \| fGET) ? MUX_MEM :`
153			`(fBRU) ? MUX_RPC :`
154			`(fSTR \| fRTD \| fBCC) ? MUX_NOP :`
155			`(\|wRD) ? MUX_ALU :`
156			`MUX_NOP;`
157
158			`opc_of <= #1`
159			`(hzd_bpc \| hzd_fwd) ? 6'o42 :`
160			`wOPC;`
161
162			`rd_of <= #1 wRD;`
163			`ra_of <= #1 wRA;`
164			`//rb_of <= #1 wRB;`
165			`imm_of <= #1 wIMM;`
166
167			`end`
168
169
170			`// immediate implementation`
171			`reg [15:0] rIMM0, rIMM1;`
172			`reg rFIM0, rFIM1;`
173			`wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;`
174			`wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;`
175
176			`assign imm_if[15:0] = wIMM;`
177			`assign imm_if[31:16] = (wFIMH) ? wIMMH :`
178			`{(16){wIMM[15]}};`
179
180			`always @(posedge gclk)`
181			`if (grst) begin`
182			`/AUTORESET/`
183			`// Beginning of autoreset for uninitialized flops`
184			`rFIM0 <= 1'h0;`
185			`rFIM1 <= 1'h0;`
186			`rIMM0 <= 16'h0;`
187			`rIMM1 <= 16'h0;`
188			`// End of automatics`
189			`end else if (dena) begin`
190			`if (gpha) begin`
191			`rFIM1 <= #1 fIMM & !hzd_bpc;`
192			`rIMM1 <= #1 wIMM;`
193			`end else begin`
194			`rFIM0 <= #1 fIMM & !hzd_bpc;`
195			`rIMM0 <= #1 wIMM;`
196			`end`
197			`end`
198
199
200			`// operand latch`
201			`reg wrb_ex;`
202			`reg fwd_ex;`
203
204			`wire opb_fwd, opa_fwd, opd_fwd;`
205
206			`assign mux_opb = {wOPC[3], opb_fwd};`
207			`assign opb_fwd = (wRB == rd_ex) &`
208			`fwd_ex & wrb_ex;`
209
210			`assign mux_opa = {(fBRU\|fBCC), opa_fwd};`
211			`assign opa_fwd = (wRA == rd_ex) &`
212			`fwd_ex & wrb_ex;`
213
214			`assign mux_opd = {fBCC, opd_fwd};`
215			`assign opd_fwd = (((wRA == rd_ex) & fBCC) \|`
216			`((wRD == rd_ex) & fSTR)) &`
217			`fwd_ex & wrb_ex;`
218
219			`always @(posedge gclk)`
220			`if (grst) begin`
221			`/AUTORESET/`
222			`// Beginning of autoreset for uninitialized flops`
223			`fwd_ex <= 1'h0;`
224			`mux_ex <= 3'h0;`
225			`rd_ex <= 5'h0;`
226			`wrb_ex <= 1'h0;`
227			`// End of automatics`
228			`end else if (dena) begin`
229			`wrb_ex <= #1 \|rd_of & \|mux_of; // FIXME: check mux`
230			`fwd_ex <= #1 \|mux_of; // FIXME: check mux`
231
232			`mux_ex <= #1 mux_of;`
233			`rd_ex <= #1 rd_of;`
234			`end`
235
236
237			`always @(posedge gclk)`
238			`if (grst) begin`
239			`/AUTORESET/`
240			`// Beginning of autoreset for uninitialized flops`
241			`opa_of <= 32'h0;`
242			`opb_of <= 32'h0;`
243			`opd_of <= 32'h0;`
244			`// End of automatics`
245
246			`end else if (dena) begin`
247
248			`case (mux_opd)`
249			`2'o2: opd_of <= #1 opa_if; // BCC`
250			`2'o1: opd_of <= #1 alu_ex; // FWD`
251			`2'o0: opd_of <= #1 opd_if; // SXX`
252			`2'o3: opd_of <= #1 alu_ex; // FWD`
253			`endcase // case (mux_opd)`
254
255			`case (mux_opb)`
256			`2'o0: opb_of <= #1 opb_if;`
257			`2'o1: opb_of <= #1 alu_ex;`
258			`2'o2: opb_of <= #1 imm_if;`
259			`2'o3: opb_of <= #1 imm_if;`
260			`//default: 32'hX;`
261			`endcase // case (mux_opb)`
262
263			`case (mux_opa)`
264			`2'o0: opa_of <= #1 opa_if;`
265			`2'o1: opa_of <= #1 alu_ex;`
266			`2'o2: opa_of <= #1 {rpc_if, 2'o0};`
267			`2'o3: opa_of <= #1 {rpc_if, 2'o0};`
268			`endcase // case (mux_opa)`
269
270			`end`
271
272			`// Hazard Detection`
273			`wire wFMUL = (mux_ex == MUX_MUL);`
274			`wire wFBSF = (mux_ex == MUX_BSF);`
275			`wire wFMEM = (mux_ex == MUX_MEM);`
276			`wire wFMOV = (mux_ex == MUX_SFR);`
277
278			`assign hzd_fwd = (opd_fwd \| opa_fwd \| opb_fwd) &`
279			`(wFMUL \| wFBSF \| wFMEM \| wFMOV);`
280			`assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);`
281
282			`endmodule // aeMB2_ctrl`
283
284			`// $Log: not supported by cvs2svn $`