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/* $Id: aeMB2_ctrl.v,v 1.3 2008-04-26 01:09:05 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
/**
 * Instruction Decode & Control
 * @file aeMB2_ctrl.v
 
 * This is the data decoder that will control the command signals and
   operand fetch.
 
 */
 
module aeMB2_ctrl (/*AUTOARG*/
   // Outputs
   opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
   mux_of, mux_ex, hzd_bpc, hzd_fwd,
   // Inputs
   opa_if, opb_if, opd_if, bra_ex, rpc_if, alu_ex, ich_dat, gclk,
   grst, dena, iena, gpha
   );
   parameter AEMB_HTX = 1;
 
   // EX CONTROL
   output [31:0] opa_of;
   output [31:0] opb_of;
   output [31:0] opd_of;
   output [5:0]  opc_of;
   output [4:0]  ra_of,
                 //rb_of,
                 rd_of;
   output [15:0] imm_of;
   output [4:0]   rd_ex;
 
   // REGS
   input [31:0]  opa_if,
                 opb_if,
                 opd_if;
 
   // WB CONTROL
   output [2:0]  mux_of,
                 mux_ex;
 
   // INTERNAL
   input [1:0]    bra_ex;
   input [31:2]  rpc_if;
   input [31:0]  alu_ex;
   input [31:0]  ich_dat;
 
   output        hzd_bpc;
   output        hzd_fwd;
 
   // SYSTEM
   input         gclk,
                 grst,
                 dena,
                 iena,
                 gpha;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [15:0]            imm_of;
   reg [2:0]             mux_ex;
   reg [2:0]             mux_of;
   reg [31:0]            opa_of;
   reg [31:0]            opb_of;
   reg [5:0]             opc_of;
   reg [31:0]            opd_of;
   reg [4:0]             ra_of;
   reg [4:0]             rd_ex;
   reg [4:0]             rd_of;
   // End of automatics
 
   wire [1:0]            mux_opa, mux_opb, mux_opd;
 
   // translate signals
   wire [4:0]            wRD, wRA, wRB;
   wire [5:0]            wOPC;
   wire [15:0]           wIMM;
   wire [31:0]           imm_if;
 
   assign               {wOPC, wRD, wRA, wIMM} = ich_dat;
   assign               wRB = wIMM[15:11];
 
   // decode main opgroups
 
   wire                 fSFT = (wOPC == 6'o44);
   wire                 fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
   wire                 fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire                 fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   wire                 fDIV = (wOPC == 6'o22);
   wire                 fRTD = (wOPC == 6'o55);
   wire                 fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire                 fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   wire                 fBRA = fBRU & wRA[3];
   wire                 fIMM = (wOPC == 6'o54);
   wire                 fMOV = (wOPC == 6'o45);
   wire                 fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire                 fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   wire                 fLDST = (wOPC[5:4] == 2'o3);
   wire                 fPUT = (wOPC == 6'o33) & wRB[4];
   wire                 fGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // control signals
   wire [31:0]           wXCEOP = 32'hBA2D0020; // Vector 0x20
   wire [31:0]           wINTOP = 32'hB9CE0010; // Vector 0x10   
   wire [31:0]           wNOPOP = 32'h88000000; // branch-no-delay/stall
 
   localparam [2:0]      MUX_ALU = 3'o7,
                        MUX_SFR = 3'o5,
                        MUX_BSF = 3'o4,
                        MUX_MUL = 3'o3,
                        MUX_MEM = 3'o2,
                        MUX_RPC = 3'o1,
                        MUX_NOP = 3'o0;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        imm_of <= 16'h0;
        mux_of <= 3'h0;
        opc_of <= 6'h0;
        ra_of <= 5'h0;
        rd_of <= 5'h0;
        // End of automatics
     end else if (dena) begin
 
        mux_of <= #1
                  (hzd_bpc | hzd_fwd) ? MUX_NOP :
                  (fMOV) ? MUX_SFR :
                  (fMUL) ? MUX_MUL :
                  (fBSF) ? MUX_BSF :
                  (fLOD | fGET) ? MUX_MEM :
                  (fBRU) ? MUX_RPC :
                  (fSTR | fRTD | fBCC) ? MUX_NOP :
                  (|wRD) ? MUX_ALU :
                  MUX_NOP;
 
        opc_of <= #1
                  (hzd_bpc | hzd_fwd) ? 6'o42 :
                  wOPC;
 
        rd_of <= #1 wRD;
        ra_of <= #1 wRA;
        //rb_of <= #1 wRB;
        imm_of <= #1 wIMM;
 
     end // if (dena)
 
 
   // immediate implementation
   reg [15:0]            rIMM0, rIMM1;
   reg                  rFIM0, rFIM1;
   wire                 wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
   wire [15:0]           wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
 
   assign               imm_if[15:0] = wIMM;
   assign               imm_if[31:16] = (wFIMH) ? wIMMH :
                                        {(16){wIMM[15]}};
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFIM0 <= 1'h0;
        rFIM1 <= 1'h0;
        rIMM0 <= 16'h0;
        rIMM1 <= 16'h0;
        // End of automatics
     end else if (dena) begin
        if (gpha) begin
           rFIM1 <= #1 fIMM & !hzd_bpc;
           rIMM1 <= #1 wIMM;
        end else begin
           rFIM0 <= #1 fIMM & !hzd_bpc;
           rIMM0 <= #1 wIMM;
        end
     end
 
 
   // operand latch   
   reg                  wrb_ex;
   reg                  fwd_ex;
 
   wire                 opb_fwd, opa_fwd, opd_fwd;
 
   assign               mux_opb = {wOPC[3], opb_fwd};
   assign               opb_fwd = (wRB == rd_ex) &
                                  fwd_ex & wrb_ex;
 
   assign               mux_opa = {(fBRU|fBCC), opa_fwd};
   assign               opa_fwd = (wRA == rd_ex) &
                                  fwd_ex & wrb_ex;
 
   assign               mux_opd = {fBCC, opd_fwd};
   assign               opd_fwd = (((wRA == rd_ex) & fBCC) |
                                   ((wRD == rd_ex) & fSTR)) &
                                  fwd_ex & wrb_ex;
 
   reg [2:0]             mux_mx;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        fwd_ex <= 1'h0;
        mux_ex <= 3'h0;
        mux_mx <= 3'h0;
        rd_ex <= 5'h0;
        wrb_ex <= 1'h0;
        // End of automatics
     end else if (dena) begin
        wrb_ex <= #1 |rd_of & |mux_of; // FIXME: check mux      
        fwd_ex <= #1 |mux_of; // FIXME: check mux
 
        mux_mx <= #1 mux_ex;
        mux_ex <= #1 mux_of;
        rd_ex <= #1 rd_of;
     end
 
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        opa_of <= 32'h0;
        opb_of <= 32'h0;
        opd_of <= 32'h0;
        // End of automatics
 
     end else if (dena) begin
 
        case (mux_opd)
          2'o2: opd_of <= #1 opa_if; // BCC
          2'o1: opd_of <= #1 alu_ex; // FWD
          2'o0: opd_of <= #1 opd_if; // SXX
          2'o3: opd_of <= #1 alu_ex; // FWD               
        endcase // case (mux_opd)
 
        case (mux_opb)
          2'o0: opb_of <= #1 opb_if;
          2'o1: opb_of <= #1 alu_ex;
          2'o2: opb_of <= #1 imm_if;
          2'o3: opb_of <= #1 imm_if;
          //default: 32'hX;
        endcase // case (mux_opb)
 
        case (mux_opa)
          2'o0: opa_of <= #1 opa_if;
          2'o1: opa_of <= #1 alu_ex;
          2'o2: opa_of <= #1 {rpc_if, 2'o0};
          2'o3: opa_of <= #1 {rpc_if, 2'o0};
        endcase // case (mux_opa)
 
     end // if (dena)
 
   // Hazard Detection
   wire                 wFMUL = (mux_ex == MUX_MUL);
   wire                 wFBSF = (mux_ex == MUX_BSF);
   wire                 wFMEM = (mux_ex == MUX_MEM);
   wire                 wFMOV = (mux_ex == MUX_SFR);
 
   assign               hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) &
                                  (wFMUL | wFBSF | wFMEM | wFMOV);
   assign               hzd_bpc = (bra_ex[1] & !bra_ex[0]);
 
endmodule // aeMB2_ctrl
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.2  2008/04/20 16:34:32  sybreon
 Basic version with some features left out.
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 Initial import.
*/

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	sybreon	`/* $Id: aeMB2_ctrl.v,v 1.3 2008-04-26 01:09:05 sybreon Exp $`
2	118	sybreon	`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21			`/**`
22			`* Instruction Decode & Control`
23			`* @file aeMB2_ctrl.v`
24
25			`* This is the data decoder that will control the command signals and`
26			`operand fetch.`
27
28			`*/`
29
30			`module aeMB2_ctrl (/AUTOARG/`
31			`// Outputs`
32			`opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,`
33			`mux_of, mux_ex, hzd_bpc, hzd_fwd,`
34			`// Inputs`
35			`opa_if, opb_if, opd_if, bra_ex, rpc_if, alu_ex, ich_dat, gclk,`
36			`grst, dena, iena, gpha`
37			`);`
38			`parameter AEMB_HTX = 1;`
39
40			`// EX CONTROL`
41			`output [31:0] opa_of;`
42			`output [31:0] opb_of;`
43			`output [31:0] opd_of;`
44			`output [5:0] opc_of;`
45			`output [4:0] ra_of,`
46			`//rb_of,`
47			`rd_of;`
48			`output [15:0] imm_of;`
49			`output [4:0] rd_ex;`
50
51			`// REGS`
52			`input [31:0] opa_if,`
53			`opb_if,`
54			`opd_if;`
55
56			`// WB CONTROL`
57			`output [2:0] mux_of,`
58			`mux_ex;`
59
60			`// INTERNAL`
61			`input [1:0] bra_ex;`
62			`input [31:2] rpc_if;`
63			`input [31:0] alu_ex;`
64			`input [31:0] ich_dat;`
65
66			`output hzd_bpc;`
67			`output hzd_fwd;`
68
69			`// SYSTEM`
70			`input gclk,`
71			`grst,`
72			`dena,`
73			`iena,`
74			`gpha;`
75
76			`/AUTOREG/`
77			`// Beginning of automatic regs (for this module's undeclared outputs)`
78			`reg [15:0] imm_of;`
79			`reg [2:0] mux_ex;`
80			`reg [2:0] mux_of;`
81			`reg [31:0] opa_of;`
82			`reg [31:0] opb_of;`
83			`reg [5:0] opc_of;`
84			`reg [31:0] opd_of;`
85			`reg [4:0] ra_of;`
86			`reg [4:0] rd_ex;`
87			`reg [4:0] rd_of;`
88			`// End of automatics`
89
90			`wire [1:0] mux_opa, mux_opb, mux_opd;`
91
92			`// translate signals`
93			`wire [4:0] wRD, wRA, wRB;`
94			`wire [5:0] wOPC;`
95			`wire [15:0] wIMM;`
96			`wire [31:0] imm_if;`
97
98			`assign {wOPC, wRD, wRA, wIMM} = ich_dat;`
99			`assign wRB = wIMM[15:11];`
100
101			`// decode main opgroups`
102
103			`wire fSFT = (wOPC == 6'o44);`
104			`wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
105			`wire fMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
106			`wire fBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
107			`wire fDIV = (wOPC == 6'o22);`
108			`wire fRTD = (wOPC == 6'o55);`
109			`wire fBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
110			`wire fBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
111			`wire fBRA = fBRU & wRA[3];`
112			`wire fIMM = (wOPC == 6'o54);`
113			`wire fMOV = (wOPC == 6'o45);`
114			`wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
115			`wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
116			`wire fLDST = (wOPC[5:4] == 2'o3);`
117			`wire fPUT = (wOPC == 6'o33) & wRB[4];`
118			`wire fGET = (wOPC == 6'o33) & !wRB[4];`
119
120
121			`// control signals`
122			`wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20`
123			`wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10`
124			`wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall`
125
126			`localparam [2:0] MUX_ALU = 3'o7,`
127			`MUX_SFR = 3'o5,`
128			`MUX_BSF = 3'o4,`
129			`MUX_MUL = 3'o3,`
130			`MUX_MEM = 3'o2,`
131			`MUX_RPC = 3'o1,`
132			`MUX_NOP = 3'o0;`
133
134			`always @(posedge gclk)`
135			`if (grst) begin`
136			`/AUTORESET/`
137			`// Beginning of autoreset for uninitialized flops`
138			`imm_of <= 16'h0;`
139			`mux_of <= 3'h0;`
140			`opc_of <= 6'h0;`
141			`ra_of <= 5'h0;`
142			`rd_of <= 5'h0;`
143			`// End of automatics`
144			`end else if (dena) begin`
145
146			`mux_of <= #1`
147			`(hzd_bpc \| hzd_fwd) ? MUX_NOP :`
148			`(fMOV) ? MUX_SFR :`
149			`(fMUL) ? MUX_MUL :`
150			`(fBSF) ? MUX_BSF :`
151			`(fLOD \| fGET) ? MUX_MEM :`
152			`(fBRU) ? MUX_RPC :`
153			`(fSTR \| fRTD \| fBCC) ? MUX_NOP :`
154			`(\|wRD) ? MUX_ALU :`
155			`MUX_NOP;`
156
157			`opc_of <= #1`
158			`(hzd_bpc \| hzd_fwd) ? 6'o42 :`
159			`wOPC;`
160
161			`rd_of <= #1 wRD;`
162			`ra_of <= #1 wRA;`
163			`//rb_of <= #1 wRB;`
164			`imm_of <= #1 wIMM;`
165
166	131	sybreon	`end // if (dena)`
167	118	sybreon
168
169			`// immediate implementation`
170			`reg [15:0] rIMM0, rIMM1;`
171			`reg rFIM0, rFIM1;`
172			`wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;`
173			`wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;`
174
175			`assign imm_if[15:0] = wIMM;`
176			`assign imm_if[31:16] = (wFIMH) ? wIMMH :`
177			`{(16){wIMM[15]}};`
178
179			`always @(posedge gclk)`
180			`if (grst) begin`
181			`/AUTORESET/`
182			`// Beginning of autoreset for uninitialized flops`
183			`rFIM0 <= 1'h0;`
184			`rFIM1 <= 1'h0;`
185			`rIMM0 <= 16'h0;`
186			`rIMM1 <= 16'h0;`
187			`// End of automatics`
188			`end else if (dena) begin`
189			`if (gpha) begin`
190			`rFIM1 <= #1 fIMM & !hzd_bpc;`
191			`rIMM1 <= #1 wIMM;`
192			`end else begin`
193			`rFIM0 <= #1 fIMM & !hzd_bpc;`
194			`rIMM0 <= #1 wIMM;`
195	131	sybreon	`end`
196			`end`
197	118	sybreon
198
199			`// operand latch`
200			`reg wrb_ex;`
201			`reg fwd_ex;`
202
203			`wire opb_fwd, opa_fwd, opd_fwd;`
204
205			`assign mux_opb = {wOPC[3], opb_fwd};`
206			`assign opb_fwd = (wRB == rd_ex) &`
207			`fwd_ex & wrb_ex;`
208
209			`assign mux_opa = {(fBRU\|fBCC), opa_fwd};`
210			`assign opa_fwd = (wRA == rd_ex) &`
211			`fwd_ex & wrb_ex;`
212
213			`assign mux_opd = {fBCC, opd_fwd};`
214			`assign opd_fwd = (((wRA == rd_ex) & fBCC) \|`
215			`((wRD == rd_ex) & fSTR)) &`
216			`fwd_ex & wrb_ex;`
217
218	120	sybreon	`reg [2:0] mux_mx;`
219
220	118	sybreon	`always @(posedge gclk)`
221			`if (grst) begin`
222			`/AUTORESET/`
223			`// Beginning of autoreset for uninitialized flops`
224			`fwd_ex <= 1'h0;`
225			`mux_ex <= 3'h0;`
226	120	sybreon	`mux_mx <= 3'h0;`
227	118	sybreon	`rd_ex <= 5'h0;`
228			`wrb_ex <= 1'h0;`
229			`// End of automatics`
230			`end else if (dena) begin`
231			`wrb_ex <= #1 \|rd_of & \|mux_of; // FIXME: check mux`
232			`fwd_ex <= #1 \|mux_of; // FIXME: check mux`
233
234	120	sybreon	`mux_mx <= #1 mux_ex;`
235	118	sybreon	`mux_ex <= #1 mux_of;`
236			`rd_ex <= #1 rd_of;`
237			`end`
238
239
240			`always @(posedge gclk)`
241			`if (grst) begin`
242			`/AUTORESET/`
243			`// Beginning of autoreset for uninitialized flops`
244			`opa_of <= 32'h0;`
245			`opb_of <= 32'h0;`
246			`opd_of <= 32'h0;`
247			`// End of automatics`
248
249			`end else if (dena) begin`
250
251			`case (mux_opd)`
252			`2'o2: opd_of <= #1 opa_if; // BCC`
253			`2'o1: opd_of <= #1 alu_ex; // FWD`
254			`2'o0: opd_of <= #1 opd_if; // SXX`
255			`2'o3: opd_of <= #1 alu_ex; // FWD`
256	131	sybreon	`endcase // case (mux_opd)`
257	118	sybreon
258			`case (mux_opb)`
259			`2'o0: opb_of <= #1 opb_if;`
260			`2'o1: opb_of <= #1 alu_ex;`
261			`2'o2: opb_of <= #1 imm_if;`
262			`2'o3: opb_of <= #1 imm_if;`
263			`//default: 32'hX;`
264	131	sybreon	`endcase // case (mux_opb)`
265	118	sybreon
266			`case (mux_opa)`
267			`2'o0: opa_of <= #1 opa_if;`
268			`2'o1: opa_of <= #1 alu_ex;`
269			`2'o2: opa_of <= #1 {rpc_if, 2'o0};`
270			`2'o3: opa_of <= #1 {rpc_if, 2'o0};`
271	131	sybreon	`endcase // case (mux_opa)`
272	118	sybreon
273	131	sybreon	`end // if (dena)`
274	118	sybreon
275			`// Hazard Detection`
276			`wire wFMUL = (mux_ex == MUX_MUL);`
277			`wire wFBSF = (mux_ex == MUX_BSF);`
278			`wire wFMEM = (mux_ex == MUX_MEM);`
279			`wire wFMOV = (mux_ex == MUX_SFR);`
280
281			`assign hzd_fwd = (opd_fwd \| opa_fwd \| opb_fwd) &`
282			`(wFMUL \| wFBSF \| wFMEM \| wFMOV);`
283			`assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);`
284
285			`endmodule // aeMB2_ctrl`
286
287	131	sybreon	`/*`
288			$Log: not supported by cvs2svn $
289			`Revision 1.2 2008/04/20 16:34:32 sybreon`
290			`Basic version with some features left out.`
291
292			`Revision 1.1 2008/04/18 00:21:52 sybreon`
293			`Initial import.`
294			`*/`