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/* $Id: aeMB2_dwbif.v,v 1.7 2008-04-27 16:41:55 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
/**
 * Data Wishbone Interface
 * @file aeMB2_dwbif.v
 
 * This sets up the Wishbone control signals for the DATA bus
   interfaces. Bus transactions are independent of the pipeline.
 
 */
 
module aeMB2_dwbif (/*AUTOARG*/
   // Outputs
   dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
   dwb_dat_o, dwb_fb, sel_mx, dwb_mx,
   // Inputs
   dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of,
   msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
   );
   parameter AEMB_DWB = 32; ///< data bus address width   
 
   // DWB control signals
   output [AEMB_DWB-1:2] dwb_adr_o;
   output [3:0]   dwb_sel_o;
   output                dwb_stb_o,
                         dwb_cyc_o,
                         dwb_tag_o, // cache enable
                         dwb_wre_o;
   output [31:0]          dwb_dat_o;
   input [31:0]   dwb_dat_i;
   input                 dwb_ack_i;
 
   // INTERNAL
   output                dwb_fb;
   output [3:0]   sel_mx;
   output [31:0]          dwb_mx;
   input [15:0]   imm_of;
   input [31:0]   opd_of;
   input [5:0]            opc_of;
   input [1:0]            opa_of;
   input [1:0]            opb_of;
   input [7:0]            msr_ex;
   input [AEMB_DWB-1:2]  mem_ex;
   input [7:5]           sfr_mx;
 
   // SYS signals
   input                 gclk,
                         grst,
                         dena,
                         gpha;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg                  dwb_cyc_o;
   reg [31:0]            dwb_dat_o;
   reg [31:0]            dwb_mx;
   reg [3:0]             dwb_sel_o;
   reg                  dwb_stb_o;
   reg                  dwb_wre_o;
   reg [3:0]             sel_mx;
   // End of automatics
 
   wire [1:0]            wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder   
   wire [3:0]            wSEL = {opc_of[1:0], wOFF};
 
   // ENABLE FEEDBACK
   assign               dwb_fb = (dwb_stb_o ~^ dwb_ack_i);
 
   // DATA bus
   assign               dwb_adr_o = mem_ex; // passthru
 
   // STORE SIZER
   // TODO: Move the right words to the right place
   // TODO: Make this work with dwb_mx to for partial word loads.
 
   reg [31:0]            dwb_lat;
   reg [31:0]            opd_ex;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_dat_o <= 32'h0;
        // End of automatics
     end else if (dena) begin
        //opd_ex <= #1 opd_of;  
        case (opc_of[1:0])
          2'o0: dwb_dat_o <= #1 {(4){opd_of[7:0]}};
          2'o1: dwb_dat_o <= #1 {(2){opd_of[15:0]}};
          2'o2: dwb_dat_o <= #1 opd_of;
          default: dwb_dat_o <= #1 32'hX;
        endcase // case (opc_of[1:0])
     end
 
   // WISHBONE PIPELINE
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_mx <= 32'h0;
        dwb_sel_o <= 4'h0;
        dwb_wre_o <= 1'h0;
        sel_mx <= 4'h0;
        // End of automatics
     end else if (dena) begin
        sel_mx <= #1 dwb_sel_o; // FIXME: do away with this! Combine
                                // dwb_dat_o & dwb_mx. dwb_dat_o can
                                // hold the existing RD value and have
                                // dwb_mx latch the correct bytes
                                // depending on dwb_sel_o.
 
        dwb_wre_o <= #1 opc_of[2]; // SXX
 
        dwb_mx <= #1
                  (dwb_ack_i) ?
                  dwb_dat_i : // stalled from RAM
                  dwb_lat; // latch earlier data
 
        case (wSEL) // Latch output
          // 32'bit
          4'h8: dwb_sel_o <= #1 4'hF;
          // 16'bit
          4'h4: dwb_sel_o <= #1 4'hC;
          4'h6: dwb_sel_o <= #1 4'h3;
          // 8'bit
          4'h0: dwb_sel_o <= #1 4'h8;
          4'h1: dwb_sel_o <= #1 4'h4;
          4'h2: dwb_sel_o <= #1 4'h2;
          4'h3: dwb_sel_o <= #1 4'h1;
          // XSL bus
          4'hC, 4'hD, 4'hE, 4'hF:
            dwb_sel_o <= #1 4'h0;
          // TODO: ILLEGAL
          default: dwb_sel_o <= #1 4'hX;
        endcase // case (wSEL)
     end // if (dena)
 
   // Independent on pipeline
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_lat <= 32'h0;
        // End of automatics
     end else if (dwb_ack_i) begin
        // LATCH READS
        dwb_lat <= #1 dwb_dat_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_cyc_o <= 1'h0;
        dwb_stb_o <= 1'h0;
        // End of automatics
     //end else if (dwb_fb) begin
     end else if (dwb_fb) begin
        dwb_stb_o <= #1
                     (dena) ? &opc_of[5:4] : // LXX/SSS
                     (dwb_stb_o & !dwb_ack_i); // LXX/SSS
        dwb_cyc_o <= #1
                     (dena) ? &opc_of[5:4] | msr_ex[0] :
                     (dwb_stb_o & !dwb_ack_i) | msr_ex[0];
     end
 
   assign dwb_tag_o = msr_ex[7]; // MSR_DCE     
 
endmodule // aeMB2_dwbif
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.6  2008/04/26 17:57:43  sybreon
 Minor performance improvements.
 
 Revision 1.5  2008/04/26 01:09:05  sybreon
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 Revision 1.4  2008/04/23 14:18:52  sybreon
 Fixed pipelined latching of data bug.
 
 Revision 1.3  2008/04/21 12:11:38  sybreon
 Passes arithmetic tests with single thread.
 
 Revision 1.2  2008/04/20 16:34:32  sybreon
 Basic version with some features left out.
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 Initial import.
*/

Line No.	Rev	Author	Line
1	147	sybreon	`/* $Id: aeMB2_dwbif.v,v 1.7 2008-04-27 16:41:55 sybreon Exp $`
2	118	sybreon	`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21			`/**`
22			`* Data Wishbone Interface`
23			`* @file aeMB2_dwbif.v`
24
25			`* This sets up the Wishbone control signals for the DATA bus`
26			`interfaces. Bus transactions are independent of the pipeline.`
27
28			`*/`
29
30			`module aeMB2_dwbif (/AUTOARG/`
31			`// Outputs`
32			`dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,`
33			`dwb_dat_o, dwb_fb, sel_mx, dwb_mx,`
34			`// Inputs`
35			`dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of,`
36	125	sybreon	`msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha`
37	118	sybreon	`);`
38			`parameter AEMB_DWB = 32; ///< data bus address width`
39
40			`// DWB control signals`
41			`output [AEMB_DWB-1:2] dwb_adr_o;`
42			`output [3:0] dwb_sel_o;`
43			`output dwb_stb_o,`
44			`dwb_cyc_o,`
45			`dwb_tag_o, // cache enable`
46			`dwb_wre_o;`
47			`output [31:0] dwb_dat_o;`
48			`input [31:0] dwb_dat_i;`
49			`input dwb_ack_i;`
50
51			`// INTERNAL`
52			`output dwb_fb;`
53			`output [3:0] sel_mx;`
54			`output [31:0] dwb_mx;`
55			`input [15:0] imm_of;`
56			`input [31:0] opd_of;`
57			`input [5:0] opc_of;`
58			`input [1:0] opa_of;`
59			`input [1:0] opb_of;`
60			`input [7:0] msr_ex;`
61			`input [AEMB_DWB-1:2] mem_ex;`
62	131	sybreon	`input [7:5] sfr_mx;`
63	118	sybreon
64			`// SYS signals`
65			`input gclk,`
66			`grst,`
67			`dena,`
68			`gpha;`
69
70			`/AUTOREG/`
71			`// Beginning of automatic regs (for this module's undeclared outputs)`
72			`reg dwb_cyc_o;`
73			`reg [31:0] dwb_dat_o;`
74			`reg [31:0] dwb_mx;`
75			`reg [3:0] dwb_sel_o;`
76			`reg dwb_stb_o;`
77			`reg dwb_wre_o;`
78			`reg [3:0] sel_mx;`
79			`// End of automatics`
80
81	131	sybreon	`wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder`
82	118	sybreon	`wire [3:0] wSEL = {opc_of[1:0], wOFF};`
83
84			`// ENABLE FEEDBACK`
85	120	sybreon	`assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i);`
86	118	sybreon
87			`// DATA bus`
88			`assign dwb_adr_o = mem_ex; // passthru`
89
90	125	sybreon	`// STORE SIZER`
91			`// TODO: Move the right words to the right place`
92			`// TODO: Make this work with dwb_mx to for partial word loads.`
93
94	131	sybreon	`reg [31:0] dwb_lat;`
95			`reg [31:0] opd_ex;`
96
97	118	sybreon	`always @(posedge gclk)`
98			`if (grst) begin`
99			`/AUTORESET/`
100			`// Beginning of autoreset for uninitialized flops`
101			`dwb_dat_o <= 32'h0;`
102			`// End of automatics`
103	125	sybreon	`end else if (dena) begin`
104	131	sybreon	`//opd_ex <= #1 opd_of;`
105	118	sybreon	`case (opc_of[1:0])`
106			`2'o0: dwb_dat_o <= #1 {(4){opd_of[7:0]}};`
107			`2'o1: dwb_dat_o <= #1 {(2){opd_of[15:0]}};`
108			`2'o2: dwb_dat_o <= #1 opd_of;`
109			`default: dwb_dat_o <= #1 32'hX;`
110			`endcase // case (opc_of[1:0])`
111	131	sybreon	`end`
112	118	sybreon
113			`// WISHBONE PIPELINE`
114			`always @(posedge gclk)`
115			`if (grst) begin`
116			`/AUTORESET/`
117			`// Beginning of autoreset for uninitialized flops`
118	131	sybreon	`dwb_mx <= 32'h0;`
119	118	sybreon	`dwb_sel_o <= 4'h0;`
120			`dwb_wre_o <= 1'h0;`
121			`sel_mx <= 4'h0;`
122			`// End of automatics`
123			`end else if (dena) begin`
124	125	sybreon	`sel_mx <= #1 dwb_sel_o; // FIXME: do away with this! Combine`
125			`// dwb_dat_o & dwb_mx. dwb_dat_o can`
126			`// hold the existing RD value and have`
127			`// dwb_mx latch the correct bytes`
128			`// depending on dwb_sel_o.`
129
130	118	sybreon	`dwb_wre_o <= #1 opc_of[2]; // SXX`
131	127	sybreon
132	147	sybreon	`dwb_mx <= #1`
133			`(dwb_ack_i) ?`
134			`dwb_dat_i : // stalled from RAM`
135			`dwb_lat; // latch earlier data`
136	118	sybreon
137	134	sybreon	`case (wSEL) // Latch output`
138	118	sybreon	`// 32'bit`
139			`4'h8: dwb_sel_o <= #1 4'hF;`
140			`// 16'bit`
141			`4'h4: dwb_sel_o <= #1 4'hC;`
142			`4'h6: dwb_sel_o <= #1 4'h3;`
143			`// 8'bit`
144			`4'h0: dwb_sel_o <= #1 4'h8;`
145			`4'h1: dwb_sel_o <= #1 4'h4;`
146			`4'h2: dwb_sel_o <= #1 4'h2;`
147			`4'h3: dwb_sel_o <= #1 4'h1;`
148	134	sybreon	`// XSL bus`
149			`4'hC, 4'hD, 4'hE, 4'hF:`
150			`dwb_sel_o <= #1 4'h0;`
151	118	sybreon	`// TODO: ILLEGAL`
152	131	sybreon	`default: dwb_sel_o <= #1 4'hX;`
153	118	sybreon	`endcase // case (wSEL)`
154			`end // if (dena)`
155
156	127	sybreon	`// Independent on pipeline`
157	131	sybreon
158	118	sybreon	`always @(posedge gclk)`
159			`if (grst) begin`
160			`/AUTORESET/`
161			`// Beginning of autoreset for uninitialized flops`
162	127	sybreon	`dwb_lat <= 32'h0;`
163			`// End of automatics`
164	131	sybreon	`end else if (dwb_ack_i) begin`
165	127	sybreon	`// LATCH READS`
166			`dwb_lat <= #1 dwb_dat_i;`
167			`end`
168
169			`always @(posedge gclk)`
170			`if (grst) begin`
171			`/AUTORESET/`
172			`// Beginning of autoreset for uninitialized flops`
173	118	sybreon	`dwb_cyc_o <= 1'h0;`
174			`dwb_stb_o <= 1'h0;`
175			`// End of automatics`
176	131	sybreon	`//end else if (dwb_fb) begin`
177	147	sybreon	`end else if (dwb_fb) begin`
178	118	sybreon	`dwb_stb_o <= #1`
179			`(dena) ? &opc_of[5:4] : // LXX/SSS`
180			`(dwb_stb_o & !dwb_ack_i); // LXX/SSS`
181			`dwb_cyc_o <= #1`
182			`(dena) ? &opc_of[5:4] \| msr_ex[0] :`
183			`(dwb_stb_o & !dwb_ack_i) \| msr_ex[0];`
184			`end`
185	125	sybreon
186			`assign dwb_tag_o = msr_ex[7]; // MSR_DCE`
187	118	sybreon
188	131	sybreon	`endmodule // aeMB2_dwbif`
189	118	sybreon
190	131	sybreon	`/*`
191			$Log: not supported by cvs2svn $
192	147	sybreon	`Revision 1.6 2008/04/26 17:57:43 sybreon`
193			`Minor performance improvements.`
194
195	134	sybreon	`Revision 1.5 2008/04/26 01:09:05 sybreon`
196			`Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.`
197
198	131	sybreon	`Revision 1.4 2008/04/23 14:18:52 sybreon`
199			`Fixed pipelined latching of data bug.`
200
201			`Revision 1.3 2008/04/21 12:11:38 sybreon`
202			`Passes arithmetic tests with single thread.`
203
204			`Revision 1.2 2008/04/20 16:34:32 sybreon`
205			`Basic version with some features left out.`
206
207			`Revision 1.1 2008/04/18 00:21:52 sybreon`
208			`Initial import.`
209			`*/`

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_dwbif.v] - Blame information for rev 191