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/* $Id: aeMB2_iche.v,v 1.5 2008-04-28 00:54:31 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
/**
 * Instruction Cache Block
 * @file aeMB2_iche.v
 
 * This is a non-optional instruction cache for single cycle
   operations. The maximum line width is 16 words (512 bits)
 
 * Single port synchronous RAM is used as the main cache DATA
   block. A single port asynchronous RAM is used as the TAG block.
 
 * The sizes need to be selected carefully to minimise resource
   wastage. Details are provided in the documentation.
 
 */
 
// 63@158 - X3S
 
module aeMB2_iche (/*AUTOARG*/
   // Outputs
   ich_dat, ich_hit, ich_fb,
   // Inputs
   ich_adr, iwb_dat_i, iwb_ack_i, gclk, grst, iena, gpha
   );
   parameter AEMB_IWB = 32;
   parameter AEMB_ICH = 11;
   parameter AEMB_IDX = 6;
   parameter AEMB_HTX = 1;
 
   // Cache
   input [AEMB_IWB-1:2] ich_adr;
   output [31:0]         ich_dat;
   output               ich_hit; ///< cache hit
   output               ich_fb; ///< cache hit
 
   // Wishbone
   input [31:0]  iwb_dat_i;
   input                iwb_ack_i;
 
   // SYS signals
   input                gclk,
                        grst,
                        iena,
                        gpha;
 
   // SOME MATH
   localparam           SIZ = AEMB_ICH-2; // 2^SIZ entries
   localparam           BLK = AEMB_ICH-AEMB_IDX; // 2^BLK blocks 
   localparam           LNE = AEMB_IDX-2; // 2^LNE lines per block
 
   localparam           TAG = AEMB_IWB-AEMB_ICH; // TAG length
   localparam           VAL = (1<<LNE); // VAL values (max 16)
 
   /*AUTOWIRE*/
   /*AUTOREG*/
 
   assign               ich_fb = ich_hit;
 
   // 1-of-X decoder
   // FIXME: Make decoder dynamic.
   // TODO: Factorise into primitive
   reg [VAL:1]          rDEC;
   always @(/*AUTOSENSE*/ich_adr)
     case (ich_adr[AEMB_IDX-1:2])
       4'h0: rDEC <= #1 16'h0001;
       4'h1: rDEC <= #1 16'h0002;
       4'h2: rDEC <= #1 16'h0004;
       4'h3: rDEC <= #1 16'h0008;
       4'h4: rDEC <= #1 16'h0010;
       4'h5: rDEC <= #1 16'h0020;
       4'h6: rDEC <= #1 16'h0040;
       4'h7: rDEC <= #1 16'h0080;
       4'h8: rDEC <= #1 16'h0100;
       4'h9: rDEC <= #1 16'h0200;
       4'hA: rDEC <= #1 16'h0400;
       4'hB: rDEC <= #1 16'h0800;
       4'hC: rDEC <= #1 16'h1000;
       4'hD: rDEC <= #1 16'h2000;
       4'hE: rDEC <= #1 16'h4000;
       4'hF: rDEC <= #1 16'h8000;
     endcase // case (ich_adr[AEMB_IDX-1:2])
 
   wire [VAL:1]         wDEC = rDEC[VAL:1]; // resize decoder   
 
   // explode the address bits
   wire [VAL:1]         oVAL, iVAL;
   wire [SIZ:1]         aLNE = ich_adr[AEMB_ICH-1:2]; // line address
   wire [BLK:1]         aTAG = ich_adr[AEMB_ICH-1:AEMB_IDX]; // block address   
   wire [TAG:1]         iTAG = ich_adr[AEMB_IWB-1:AEMB_ICH]; // current TAG value
   wire [TAG:1]         oTAG;
 
   // HIT CHECKS
   wire                 hTAG = ((iTAG ^ oTAG) == {(TAG){1'b0}}); // 100.0
                        //~|(iTAG ^ oTAG); // 98
                        //(iTAG == oTAG); // 85
   wire                 hVAL = //|(oVAL & wDEC);   
                        ((oVAL & wDEC) != {(VAL){1'b0}});
 
   assign               ich_hit = hTAG & hVAL;
   assign               iVAL = (hTAG) ? // BLOCK/LINE fill check
                               oVAL | wDEC : // LINE fill
                               wDEC; // BLOCK replace
 
   /*
    aeMB2_tpsram AUTO_TEMPLATE (
    .AW(SIZ),
    .DW(6'd32),
 
    .dat_o(),
    .dat_i(iwb_dat_i[31:0]),
    .adr_i(aLNE[SIZ:1]),
    .rst_i(),
    .ena_i(iwb_ack_i),
    .clk_i(gclk),
    .wre_i(iwb_ack_i),
 
    .xdat_o(ich_dat[31:0]),
    .xdat_i(),
    .xadr_i(aLNE[SIZ:1]),
    .xrst_i(grst),
    .xena_i(iena),
    .xclk_i(gclk),
    .xwre_i(),
    )
 
    aeMB2_sparam AUTO_TEMPLATE (
    .AW(BLK),
    .DW(VAL+TAG),
 
    .dat_o({oVAL, oTAG}),
    .dat_i({iVAL, iTAG}),
    .adr_i(aTAG[BLK:1]),
    .ena_i(iwb_ack_i),
    .clk_i(gclk),
    .wre_i(iwb_ack_i),
    )
    */
 
   // CACHE TAG BLOCK
   aeMB2_sparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (BLK),                   // Templated
       .DW                              (VAL+TAG))               // Templated
   tag0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            ({oVAL, oTAG}),          // Templated
      // Inputs
      .adr_i                            (aTAG[BLK:1]),           // Templated
      .dat_i                            ({iVAL, iTAG}),          // Templated
      .wre_i                            (iwb_ack_i),             // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (iwb_ack_i));            // Templated
 
   // CACHE DATA BLOCK   
   // Writes on successful IWB bus transfers.
   // Reads on pipeline enable.
   aeMB2_tpsram
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (SIZ),                   // Templated
       .DW                              (6'd32))                 // Templated
   data0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (ich_dat[31:0]),  // Templated
      // Inputs
      .adr_i                            (aLNE[SIZ:1]),           // Templated
      .dat_i                            (iwb_dat_i[31:0]),        // Templated
      .wre_i                            (iwb_ack_i),             // Templated
      .ena_i                            (iwb_ack_i),             // Templated
      .rst_i                            (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .xadr_i                           (aLNE[SIZ:1]),           // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .xena_i                           (iena),                  // Templated
      .xrst_i                           (grst),                  // Templated
      .xclk_i                           (gclk));                         // Templated
 
endmodule // aeMB2_iche
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.4  2008/04/26 17:57:43  sybreon
 Minor performance improvements.
 
 Revision 1.3  2008/04/26 01:09:06  sybreon
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 Revision 1.2  2008/04/20 16:34:32  sybreon
 Basic version with some features left out.
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 Initial import.
*/

Line No.	Rev	Author	Line
1	149	sybreon	`/* $Id: aeMB2_iche.v,v 1.5 2008-04-28 00:54:31 sybreon Exp $`
2	118	sybreon	`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21			`/**`
22			`* Instruction Cache Block`
23			`* @file aeMB2_iche.v`
24
25	120	sybreon	`* This is a non-optional instruction cache for single cycle`
26			`operations. The maximum line width is 16 words (512 bits)`
27	118	sybreon
28	120	sybreon	`* Single port synchronous RAM is used as the main cache DATA`
29			`block. A single port asynchronous RAM is used as the TAG block.`
30
31			`* The sizes need to be selected carefully to minimise resource`
32			`wastage. Details are provided in the documentation.`
33
34	118	sybreon	`*/`
35
36	120	sybreon	`// 63@158 - X3S`
37
38	118	sybreon	`module aeMB2_iche (/AUTOARG/`
39			`// Outputs`
40			`ich_dat, ich_hit, ich_fb,`
41			`// Inputs`
42	120	sybreon	`ich_adr, iwb_dat_i, iwb_ack_i, gclk, grst, iena, gpha`
43	118	sybreon	`);`
44			`parameter AEMB_IWB = 32;`
45			`parameter AEMB_ICH = 11;`
46	120	sybreon	`parameter AEMB_IDX = 6;`
47	118	sybreon	`parameter AEMB_HTX = 1;`
48
49			`// Cache`
50			`input [AEMB_IWB-1:2] ich_adr;`
51			`output [31:0] ich_dat;`
52	120	sybreon	`output ich_hit; ///< cache hit`
53			`output ich_fb; ///< cache hit`
54	118	sybreon
55			`// Wishbone`
56			`input [31:0] iwb_dat_i;`
57	120	sybreon	`input iwb_ack_i;`
58	118	sybreon
59			`// SYS signals`
60			`input gclk,`
61			`grst,`
62			`iena,`
63			`gpha;`
64	120	sybreon
65			`// SOME MATH`
66			`localparam SIZ = AEMB_ICH-2; // 2^SIZ entries`
67			`localparam BLK = AEMB_ICH-AEMB_IDX; // 2^BLK blocks`
68			`localparam LNE = AEMB_IDX-2; // 2^LNE lines per block`
69
70			`localparam TAG = AEMB_IWB-AEMB_ICH; // TAG length`
71			`localparam VAL = (1<<LNE); // VAL values (max 16)`
72	118	sybreon
73			`/AUTOWIRE/`
74			`/AUTOREG/`
75
76	120	sybreon	`assign ich_fb = ich_hit;`
77	118	sybreon
78	120	sybreon	`// 1-of-X decoder`
79			`// FIXME: Make decoder dynamic.`
80			`// TODO: Factorise into primitive`
81			`reg [VAL:1] rDEC;`
82			`always @(/AUTOSENSE/ich_adr)`
83			`case (ich_adr[AEMB_IDX-1:2])`
84			`4'h0: rDEC <= #1 16'h0001;`
85			`4'h1: rDEC <= #1 16'h0002;`
86			`4'h2: rDEC <= #1 16'h0004;`
87			`4'h3: rDEC <= #1 16'h0008;`
88			`4'h4: rDEC <= #1 16'h0010;`
89			`4'h5: rDEC <= #1 16'h0020;`
90			`4'h6: rDEC <= #1 16'h0040;`
91			`4'h7: rDEC <= #1 16'h0080;`
92			`4'h8: rDEC <= #1 16'h0100;`
93			`4'h9: rDEC <= #1 16'h0200;`
94			`4'hA: rDEC <= #1 16'h0400;`
95			`4'hB: rDEC <= #1 16'h0800;`
96			`4'hC: rDEC <= #1 16'h1000;`
97			`4'hD: rDEC <= #1 16'h2000;`
98			`4'hE: rDEC <= #1 16'h4000;`
99			`4'hF: rDEC <= #1 16'h8000;`
100	131	sybreon	`endcase // case (ich_adr[AEMB_IDX-1:2])`
101	118	sybreon
102	120	sybreon	`wire [VAL:1] wDEC = rDEC[VAL:1]; // resize decoder`
103
104			`// explode the address bits`
105	149	sybreon	`wire [VAL:1] oVAL, iVAL;`
106	120	sybreon	`wire [SIZ:1] aLNE = ich_adr[AEMB_ICH-1:2]; // line address`
107			`wire [BLK:1] aTAG = ich_adr[AEMB_ICH-1:AEMB_IDX]; // block address`
108			`wire [TAG:1] iTAG = ich_adr[AEMB_IWB-1:AEMB_ICH]; // current TAG value`
109			`wire [TAG:1] oTAG;`
110	134	sybreon
111	120	sybreon	`// HIT CHECKS`
112	149	sybreon	`wire hTAG = ((iTAG ^ oTAG) == {(TAG){1'b0}}); // 100.0`
113			`//~\|(iTAG ^ oTAG); // 98`
114			`//(iTAG == oTAG); // 85`
115			`wire hVAL = //\|(oVAL & wDEC);`
116			`((oVAL & wDEC) != {(VAL){1'b0}});`
117	118	sybreon
118	120	sybreon	`assign ich_hit = hTAG & hVAL;`
119			`assign iVAL = (hTAG) ? // BLOCK/LINE fill check`
120			`oVAL \| wDEC : // LINE fill`
121			`wDEC; // BLOCK replace`
122	134	sybreon
123	120	sybreon	`/*`
124			`aeMB2_tpsram AUTO_TEMPLATE (`
125	149	sybreon	`.AW(SIZ),`
126			`.DW(6'd32),`
127
128	120	sybreon	`.dat_o(),`
129			`.dat_i(iwb_dat_i[31:0]),`
130			`.adr_i(aLNE[SIZ:1]),`
131			`.rst_i(),`
132			`.ena_i(iwb_ack_i),`
133			`.clk_i(gclk),`
134			`.wre_i(iwb_ack_i),`
135
136	149	sybreon	`.xdat_o(ich_dat[31:0]),`
137	120	sybreon	`.xdat_i(),`
138			`.xadr_i(aLNE[SIZ:1]),`
139			`.xrst_i(grst),`
140			`.xena_i(iena),`
141	118	sybreon	`.xclk_i(gclk),`
142	120	sybreon	`.xwre_i(),`
143			`)`
144	118	sybreon
145	120	sybreon	`aeMB2_sparam AUTO_TEMPLATE (`
146	149	sybreon	`.AW(BLK),`
147			`.DW(VAL+TAG),`
148
149	120	sybreon	`.dat_o({oVAL, oTAG}),`
150			`.dat_i({iVAL, iTAG}),`
151			`.adr_i(aTAG[BLK:1]),`
152			`.ena_i(iwb_ack_i),`
153	118	sybreon	`.clk_i(gclk),`
154	120	sybreon	`.wre_i(iwb_ack_i),`
155			`)`
156			`*/`
157
158			`// CACHE TAG BLOCK`
159			`aeMB2_sparam`
160	149	sybreon	`#(/AUTOINSTPARAM/`
161			`// Parameters`
162			`.AW (BLK), // Templated`
163			`.DW (VAL+TAG)) // Templated`
164	120	sybreon	`tag0`
165	118	sybreon	`(/AUTOINST/`
166			`// Outputs`
167	120	sybreon	`.dat_o ({oVAL, oTAG}), // Templated`
168	118	sybreon	`// Inputs`
169	120	sybreon	`.adr_i (aTAG[BLK:1]), // Templated`
170			`.dat_i ({iVAL, iTAG}), // Templated`
171			`.wre_i (iwb_ack_i), // Templated`
172			`.clk_i (gclk), // Templated`
173			`.ena_i (iwb_ack_i)); // Templated`
174
175			`// CACHE DATA BLOCK`
176			`// Writes on successful IWB bus transfers.`
177			`// Reads on pipeline enable.`
178			`aeMB2_tpsram`
179	149	sybreon	`#(/AUTOINSTPARAM/`
180			`// Parameters`
181			`.AW (SIZ), // Templated`
182			`.DW (6'd32)) // Templated`
183	120	sybreon	`data0`
184			`(/AUTOINST/`
185			`// Outputs`
186			`.dat_o (), // Templated`
187	149	sybreon	`.xdat_o (ich_dat[31:0]), // Templated`
188	120	sybreon	`// Inputs`
189			`.adr_i (aLNE[SIZ:1]), // Templated`
190	118	sybreon	`.dat_i (iwb_dat_i[31:0]), // Templated`
191	120	sybreon	`.wre_i (iwb_ack_i), // Templated`
192			`.ena_i (iwb_ack_i), // Templated`
193			`.rst_i (), // Templated`
194	118	sybreon	`.clk_i (gclk), // Templated`
195	120	sybreon	`.xadr_i (aLNE[SIZ:1]), // Templated`
196			`.xdat_i (), // Templated`
197			`.xwre_i (), // Templated`
198			`.xena_i (iena), // Templated`
199			`.xrst_i (grst), // Templated`
200			`.xclk_i (gclk)); // Templated`
201	118	sybreon
202			`endmodule // aeMB2_iche`
203
204	131	sybreon	`/*`
205			$Log: not supported by cvs2svn $
206	149	sybreon	`Revision 1.4 2008/04/26 17:57:43 sybreon`
207			`Minor performance improvements.`
208
209	134	sybreon	`Revision 1.3 2008/04/26 01:09:06 sybreon`
210			`Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.`
211
212	131	sybreon	`Revision 1.2 2008/04/20 16:34:32 sybreon`
213			`Basic version with some features left out.`
214
215			`Revision 1.1 2008/04/18 00:21:52 sybreon`
216			`Initial import.`
217			`*/`

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_iche.v] - Blame information for rev 206