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1 118 sybreon 
/* $Id: aeMB2_memif.v,v 1.1 2008-04-18 00:21:52 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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 * Memory Interface Wrapper
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 * @file aeMB2_memif.v
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 * A wrapper for the data/xsel bus interfaces.
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 */
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module aeMB2_memif (/*AUTOARG*/
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   // Outputs
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   xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_mx, xwb_fb,
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   xwb_dat_o, xwb_cyc_o, xwb_adr_o, sel_mx, dwb_wre_o, dwb_tag_o,
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   dwb_stb_o, dwb_sel_o, dwb_mx, dwb_fb, dwb_dat_o, dwb_cyc_o,
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   dwb_adr_o,
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   // Inputs
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   xwb_dat_i, xwb_ack_i, opd_of, opc_of, opb_of, opa_of, msr_ex,
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   mem_ex, imm_of, grst, gpha, gclk, dwb_dat_i, dwb_ack_i, dena
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   );
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   parameter AEMB_DWB = 32;
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   parameter AEMB_XWB = 3;
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   parameter AEMB_XSL = 1;
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   /*AUTOOUTPUT*/
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   // Beginning of automatic outputs (from unused autoinst outputs)
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   output [AEMB_DWB-1:2] dwb_adr_o;             // From dwbif0 of aeMB2_dwbif.v
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   output               dwb_cyc_o;              // From dwbif0 of aeMB2_dwbif.v
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   output [31:0] dwb_dat_o;              // From dwbif0 of aeMB2_dwbif.v
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   output               dwb_fb;                 // From dwbif0 of aeMB2_dwbif.v
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   output [31:0] dwb_mx;                 // From dwbif0 of aeMB2_dwbif.v
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   output [3:0]          dwb_sel_o;              // From dwbif0 of aeMB2_dwbif.v
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   output               dwb_stb_o;              // From dwbif0 of aeMB2_dwbif.v
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   output               dwb_tag_o;              // From dwbif0 of aeMB2_dwbif.v
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   output               dwb_wre_o;              // From dwbif0 of aeMB2_dwbif.v
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   output [3:0]          sel_mx;                 // From dwbif0 of aeMB2_dwbif.v
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   output [AEMB_XWB+1:2] xwb_adr_o;             // From xslif0 of aeMB2_xslif.v
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   output               xwb_cyc_o;              // From xslif0 of aeMB2_xslif.v
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   output [31:0] xwb_dat_o;              // From xslif0 of aeMB2_xslif.v
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   output               xwb_fb;                 // From xslif0 of aeMB2_xslif.v
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   output [31:0] xwb_mx;                 // From xslif0 of aeMB2_xslif.v
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   output [3:0]          xwb_sel_o;              // From xslif0 of aeMB2_xslif.v
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   output               xwb_stb_o;              // From xslif0 of aeMB2_xslif.v
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   output               xwb_tag_o;              // From xslif0 of aeMB2_xslif.v
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   output               xwb_wre_o;              // From xslif0 of aeMB2_xslif.v
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   // End of automatics
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   /*AUTOINPUT*/
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   // Beginning of automatic inputs (from unused autoinst inputs)
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   input                dena;                   // To xslif0 of aeMB2_xslif.v, ...
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   input                dwb_ack_i;              // To dwbif0 of aeMB2_dwbif.v
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   input [31:0]          dwb_dat_i;              // To dwbif0 of aeMB2_dwbif.v
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   input                gclk;                   // To xslif0 of aeMB2_xslif.v, ...
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   input                gpha;                   // To xslif0 of aeMB2_xslif.v, ...
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   input                grst;                   // To xslif0 of aeMB2_xslif.v, ...
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   input [15:0]          imm_of;                 // To xslif0 of aeMB2_xslif.v, ...
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   input [AEMB_DWB-1:2] mem_ex;                 // To dwbif0 of aeMB2_dwbif.v
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   input [7:0]           msr_ex;                 // To dwbif0 of aeMB2_dwbif.v
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   input [31:0]          opa_of;                 // To xslif0 of aeMB2_xslif.v, ...
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   input [1:0]           opb_of;                 // To dwbif0 of aeMB2_dwbif.v
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   input [5:0]           opc_of;                 // To xslif0 of aeMB2_xslif.v, ...
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   input [31:0]          opd_of;                 // To dwbif0 of aeMB2_dwbif.v
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   input                xwb_ack_i;              // To xslif0 of aeMB2_xslif.v
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   input [31:0]          xwb_dat_i;              // To xslif0 of aeMB2_xslif.v
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   // End of automatics
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   /*AUTOWIRE*/
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   aeMB2_xslif
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     #(/*AUTOINSTPARAM*/
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       // Parameters
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       .AEMB_XSL                        (AEMB_XSL),
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       .AEMB_XWB                        (AEMB_XWB))
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   xslif0
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     (/*AUTOINST*/
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      // Outputs
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      .xwb_adr_o                        (xwb_adr_o[AEMB_XWB+1:2]),
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      .xwb_dat_o                        (xwb_dat_o[31:0]),
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      .xwb_sel_o                        (xwb_sel_o[3:0]),
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      .xwb_tag_o                        (xwb_tag_o),
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      .xwb_stb_o                        (xwb_stb_o),
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      .xwb_cyc_o                        (xwb_cyc_o),
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      .xwb_wre_o                        (xwb_wre_o),
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      .xwb_fb                           (xwb_fb),
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      .xwb_mx                           (xwb_mx[31:0]),
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      // Inputs
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      .xwb_dat_i                        (xwb_dat_i[31:0]),
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      .xwb_ack_i                        (xwb_ack_i),
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      .imm_of                           (imm_of[15:0]),
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      .opc_of                           (opc_of[5:0]),
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      .opa_of                           (opa_of[31:0]),
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      .gclk                             (gclk),
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      .grst                             (grst),
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      .dena                             (dena),
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      .gpha                             (gpha));
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   aeMB2_dwbif
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     #(/*AUTOINSTPARAM*/
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       // Parameters
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       .AEMB_DWB                        (AEMB_DWB))
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   dwbif0
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     (/*AUTOINST*/
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      // Outputs
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      .dwb_adr_o                        (dwb_adr_o[AEMB_DWB-1:2]),
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      .dwb_sel_o                        (dwb_sel_o[3:0]),
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      .dwb_stb_o                        (dwb_stb_o),
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      .dwb_cyc_o                        (dwb_cyc_o),
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      .dwb_tag_o                        (dwb_tag_o),
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      .dwb_wre_o                        (dwb_wre_o),
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      .dwb_dat_o                        (dwb_dat_o[31:0]),
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      .dwb_fb                           (dwb_fb),
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      .sel_mx                           (sel_mx[3:0]),
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      .dwb_mx                           (dwb_mx[31:0]),
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      // Inputs
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      .dwb_dat_i                        (dwb_dat_i[31:0]),
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      .dwb_ack_i                        (dwb_ack_i),
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      .imm_of                           (imm_of[15:0]),
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      .opd_of                           (opd_of[31:0]),
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      .opc_of                           (opc_of[5:0]),
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      .opa_of                           (opa_of[1:0]),
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      .opb_of                           (opb_of[1:0]),
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      .msr_ex                           (msr_ex[7:0]),
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      .mem_ex                           (mem_ex[AEMB_DWB-1:2]),
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      .gclk                             (gclk),
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      .grst                             (grst),
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      .dena                             (dena),
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      .gpha                             (gpha));
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endmodule // aeMB2_memif
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