URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_core.v] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log


//                              -*- Mode: Verilog -*-
// Filename        : aeMB_core.v
// Description     : Microblaze Compatible Core
// Author          : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Created On      : Fri Dec 29 16:15:18 2006
// Last Modified By: $Author: sybreon $
// Last Modified On: $Date: 2007-04-04 06:13:23 $
// Update Count    : $Revision: 1.2 $
// Status          : $State: Exp $
 
/*
 * $Id: aeMB_core.v,v 1.2 2007-04-04 06:13:23 sybreon Exp $
 *
 * AEMB 32-bit Microblaze Compatible Core
 * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
 *
 * This library is free software; you can redistribute it and/or modify it
 * under the terms of the GNU Lesser General Public License as published by
 * the Free Software Foundation; either version 2.1 of the License,
 * or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
 * License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public License
 * along with this library; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * DESCRIPTION
 * Microblaze compatible, WISHBONE compliant hardware core. This core is
 * capable of executing software compile for EDK 2.1 using GCC. It has the
 * capability of handling interrupts as well as exceptions.
 *
 * HISTORY
 * $Log: not supported by cvs2svn $
 * Revision 1.1  2007/03/09 17:52:17  sybreon
 * initial import
 *
 */
 
module aeMB_core (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,
   // Inputs
   sys_run_i, sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i,
   iwb_ack_i, dwb_dat_i, dwb_ack_i
   );
   // Instruction WB address space
   parameter ISIZ = 32;
   // Data WB address space
   parameter DSIZ = 32;
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DSIZ-1:0]     dwb_adr_o;              // From aslu of aeMB_aslu.v
   output [31:0] dwb_dat_o;              // From regfile of aeMB_regfile.v
   output               dwb_stb_o;              // From decode of aeMB_decode.v
   output               dwb_we_o;               // From decode of aeMB_decode.v
   output [ISIZ-1:0]     iwb_adr_o;              // From fetch of aeMB_fetch.v
   output               iwb_stb_o;              // From decode of aeMB_decode.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To control of aeMB_control.v
   input [31:0]          dwb_dat_i;              // To regfile of aeMB_regfile.v, ...
   input                iwb_ack_i;              // To control of aeMB_control.v
   input [31:0]          iwb_dat_i;              // To fetch of aeMB_fetch.v, ...
   input                sys_clk_i;              // To control of aeMB_control.v
   input                sys_exc_i;              // To control of aeMB_control.v
   input                sys_int_i;              // To control of aeMB_control.v
   input                sys_rst_i;              // To control of aeMB_control.v
   input                sys_run_i;              // To control of aeMB_control.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 drst;                   // From control of aeMB_control.v
   wire                 drun;                   // From control of aeMB_control.v
   wire                 frst;                   // From control of aeMB_control.v
   wire                 frun;                   // From control of aeMB_control.v
   wire                 nclk;                   // From control of aeMB_control.v
   wire                 nrst;                   // From control of aeMB_control.v
   wire                 rBRA;                   // From decode of aeMB_decode.v
   wire                 rDLY;                   // From decode of aeMB_decode.v
   wire                 rDWBSTB;                // From decode of aeMB_decode.v
   wire                 rDWBWE;                 // From decode of aeMB_decode.v
   wire [1:0]            rFSM;                   // From control of aeMB_control.v
   wire [15:0]           rIMM;                   // From decode of aeMB_decode.v
   wire                 rIWBSTB;                // From decode of aeMB_decode.v
   wire                 rLNK;                   // From decode of aeMB_decode.v
   wire [1:0]            rMXALU;                 // From decode of aeMB_decode.v
   wire [1:0]            rMXLDST;                // From decode of aeMB_decode.v
   wire [1:0]            rMXSRC;                 // From decode of aeMB_decode.v
   wire [1:0]            rMXTGT;                 // From decode of aeMB_decode.v
   wire [5:0]            rOPC;                   // From decode of aeMB_decode.v
   wire [31:0]           rPC;                    // From fetch of aeMB_fetch.v
   wire [31:0]           rPCNXT;                 // From fetch of aeMB_fetch.v
   wire [4:0]            rRA;                    // From decode of aeMB_decode.v
   wire [4:0]            rRB;                    // From decode of aeMB_decode.v
   wire [4:0]            rRD;                    // From decode of aeMB_decode.v
   wire [4:0]            rRD_;                   // From decode of aeMB_decode.v
   wire [31:0]           rREGA;                  // From regfile of aeMB_regfile.v
   wire [31:0]           rREGB;                  // From regfile of aeMB_regfile.v
   wire [31:0]           rRESULT;                // From aslu of aeMB_aslu.v
   wire                 rRWE;                   // From decode of aeMB_decode.v
   wire [31:0]           rSIMM;                  // From decode of aeMB_decode.v
   // End of automatics
 
   aeMB_regfile #(DSIZ)
     regfile (/*AUTOINST*/
              // Outputs
              .dwb_dat_o                (dwb_dat_o[31:0]),
              .rREGA                    (rREGA[31:0]),
              .rREGB                    (rREGB[31:0]),
              // Inputs
              .dwb_dat_i                (dwb_dat_i[31:0]),
              .rDWBSTB                  (rDWBSTB),
              .rDWBWE                   (rDWBWE),
              .rRA                      (rRA[4:0]),
              .rRB                      (rRB[4:0]),
              .rRD                      (rRD[4:0]),
              .rRD_                     (rRD_[4:0]),
              .rRESULT                  (rRESULT[31:0]),
              .rFSM                     (rFSM[1:0]),
              .rPC                      (rPC[31:0]),
              .rPCNXT                   (rPCNXT[31:0]),
              .rLNK                     (rLNK),
              .rRWE                     (rRWE),
              .nclk                     (nclk),
              .nrst                     (nrst),
              .drun                     (drun),
              .drst                     (drst));
 
   aeMB_fetch #(ISIZ)
     fetch (/*AUTOINST*/
            // Outputs
            .iwb_adr_o                  (iwb_adr_o[ISIZ-1:0]),
            .rPC                        (rPC[31:0]),
            .rPCNXT                     (rPCNXT[31:0]),
            // Inputs
            .iwb_dat_i                  (iwb_dat_i[31:0]),
            .nclk                       (nclk),
            .nrst                       (nrst),
            .frun                       (frun),
            .rFSM                       (rFSM[1:0]),
            .rBRA                       (rBRA),
            .rRESULT                    (rRESULT[31:0]));
 
   aeMB_control
     control (/*AUTOINST*/
              // Outputs
              .rFSM                     (rFSM[1:0]),
              .nclk                     (nclk),
              .nrst                     (nrst),
              .frun                     (frun),
              .drun                     (drun),
              .frst                     (frst),
              .drst                     (drst),
              // Inputs
              .sys_rst_i                (sys_rst_i),
              .sys_clk_i                (sys_clk_i),
              .sys_int_i                (sys_int_i),
              .sys_exc_i                (sys_exc_i),
              .sys_run_i                (sys_run_i),
              .rIWBSTB                  (rIWBSTB),
              .iwb_ack_i                (iwb_ack_i),
              .rDWBSTB                  (rDWBSTB),
              .dwb_ack_i                (dwb_ack_i),
              .rBRA                     (rBRA),
              .rDLY                     (rDLY));
 
   aeMB_aslu #(DSIZ)
     aslu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DSIZ-1:0]),
           .rRESULT                     (rRESULT[31:0]),
           // Inputs
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALU                      (rMXALU[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rPC                         (rPC[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rMXLDST                     (rMXLDST[1:0]),
           .nclk                        (nclk),
           .nrst                        (nrst),
           .drun                        (drun),
           .drst                        (drst));
 
 
   aeMB_decode
     decode (/*AUTOINST*/
             // Outputs
             .rSIMM                     (rSIMM[31:0]),
             .rMXALU                    (rMXALU[1:0]),
             .rMXSRC                    (rMXSRC[1:0]),
             .rMXTGT                    (rMXTGT[1:0]),
             .rRA                       (rRA[4:0]),
             .rRB                       (rRB[4:0]),
             .rRD                       (rRD[4:0]),
             .rRD_                      (rRD_[4:0]),
             .rOPC                      (rOPC[5:0]),
             .rIMM                      (rIMM[15:0]),
             .rDWBSTB                   (rDWBSTB),
             .rDWBWE                    (rDWBWE),
             .rIWBSTB                   (rIWBSTB),
             .rDLY                      (rDLY),
             .rLNK                      (rLNK),
             .rBRA                      (rBRA),
             .rRWE                      (rRWE),
             .rMXLDST                   (rMXLDST[1:0]),
             .iwb_stb_o                 (iwb_stb_o),
             .dwb_stb_o                 (dwb_stb_o),
             .dwb_we_o                  (dwb_we_o),
             // Inputs
             .rREGA                     (rREGA[31:0]),
             .rRESULT                   (rRESULT[31:0]),
             .iwb_dat_i                 (iwb_dat_i[31:0]),
             .dwb_dat_i                 (dwb_dat_i[31:0]),
             .nclk                      (nclk),
             .nrst                      (nrst),
             .drun                      (drun),
             .frun                      (frun),
             .frst                      (frst),
             .drst                      (drst));
 
 
endmodule // aeMB_core

Line No.	Rev	Author	Line
1	3	sybreon	`// -- Mode: Verilog --`
2			`// Filename : aeMB_core.v`
3			`// Description : Microblaze Compatible Core`
4			`// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
5			`// Created On : Fri Dec 29 16:15:18 2006`
6	11	sybreon	`// Last Modified By: $Author: sybreon $`
7			`// Last Modified On: $Date: 2007-04-04 06:13:23 $`
8			`// Update Count : $Revision: 1.2 $`
9			`// Status : $State: Exp $`
10	3	sybreon
11			`/*`
12	11	sybreon	`* $Id: aeMB_core.v,v 1.2 2007-04-04 06:13:23 sybreon Exp $`
13	3	sybreon	`*`
14	11	sybreon	`* AEMB 32-bit Microblaze Compatible Core`
15	3	sybreon	`* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
16			`*`
17			`* This library is free software; you can redistribute it and/or modify it`
18			`* under the terms of the GNU Lesser General Public License as published by`
19			`* the Free Software Foundation; either version 2.1 of the License,`
20			`* or (at your option) any later version.`
21			`*`
22			`* This library is distributed in the hope that it will be useful, but`
23			`* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
24			`* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
25			`* License for more details.`
26			`*`
27			`* You should have received a copy of the GNU Lesser General Public License`
28			`* along with this library; if not, write to the Free Software Foundation, Inc.,`
29			`* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
30			`*`
31			`* DESCRIPTION`
32			`* Microblaze compatible, WISHBONE compliant hardware core. This core is`
33			`* capable of executing software compile for EDK 2.1 using GCC. It has the`
34			`* capability of handling interrupts as well as exceptions.`
35			`*`
36			`* HISTORY`
37			`* $Log: not supported by cvs2svn $`
38	11	sybreon	`* Revision 1.1 2007/03/09 17:52:17 sybreon`
39			`* initial import`
40	3	sybreon	`*`
41			`*/`
42
43			`module aeMB_core (/AUTOARG/`
44			`// Outputs`
45	11	sybreon	`iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,`
46	3	sybreon	`// Inputs`
47			`sys_run_i, sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i,`
48			`iwb_ack_i, dwb_dat_i, dwb_ack_i`
49			`);`
50			`// Instruction WB address space`
51			`parameter ISIZ = 32;`
52			`// Data WB address space`
53			`parameter DSIZ = 32;`
54
55			`/AUTOOUTPUT/`
56			`// Beginning of automatic outputs (from unused autoinst outputs)`
57			`output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v`
58			`output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v`
59			`output dwb_stb_o; // From decode of aeMB_decode.v`
60			`output dwb_we_o; // From decode of aeMB_decode.v`
61			`output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v`
62			`output iwb_stb_o; // From decode of aeMB_decode.v`
63			`// End of automatics`
64			`/AUTOINPUT/`
65			`// Beginning of automatic inputs (from unused autoinst inputs)`
66			`input dwb_ack_i; // To control of aeMB_control.v`
67			`input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v, ...`
68			`input iwb_ack_i; // To control of aeMB_control.v`
69			`input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ...`
70			`input sys_clk_i; // To control of aeMB_control.v`
71			`input sys_exc_i; // To control of aeMB_control.v`
72			`input sys_int_i; // To control of aeMB_control.v`
73			`input sys_rst_i; // To control of aeMB_control.v`
74			`input sys_run_i; // To control of aeMB_control.v`
75			`// End of automatics`
76			`/AUTOWIRE/`
77			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
78			`wire drst; // From control of aeMB_control.v`
79			`wire drun; // From control of aeMB_control.v`
80			`wire frst; // From control of aeMB_control.v`
81			`wire frun; // From control of aeMB_control.v`
82			`wire nclk; // From control of aeMB_control.v`
83			`wire nrst; // From control of aeMB_control.v`
84			`wire rBRA; // From decode of aeMB_decode.v`
85			`wire rDLY; // From decode of aeMB_decode.v`
86			`wire rDWBSTB; // From decode of aeMB_decode.v`
87			`wire rDWBWE; // From decode of aeMB_decode.v`
88			`wire [1:0] rFSM; // From control of aeMB_control.v`
89			`wire [15:0] rIMM; // From decode of aeMB_decode.v`
90			`wire rIWBSTB; // From decode of aeMB_decode.v`
91			`wire rLNK; // From decode of aeMB_decode.v`
92			`wire [1:0] rMXALU; // From decode of aeMB_decode.v`
93	11	sybreon	`wire [1:0] rMXLDST; // From decode of aeMB_decode.v`
94	3	sybreon	`wire [1:0] rMXSRC; // From decode of aeMB_decode.v`
95			`wire [1:0] rMXTGT; // From decode of aeMB_decode.v`
96			`wire [5:0] rOPC; // From decode of aeMB_decode.v`
97			`wire [31:0] rPC; // From fetch of aeMB_fetch.v`
98			`wire [31:0] rPCNXT; // From fetch of aeMB_fetch.v`
99			`wire [4:0] rRA; // From decode of aeMB_decode.v`
100			`wire [4:0] rRB; // From decode of aeMB_decode.v`
101			`wire [4:0] rRD; // From decode of aeMB_decode.v`
102			`wire [4:0] rRD_; // From decode of aeMB_decode.v`
103			`wire [31:0] rREGA; // From regfile of aeMB_regfile.v`
104			`wire [31:0] rREGB; // From regfile of aeMB_regfile.v`
105			`wire [31:0] rRESULT; // From aslu of aeMB_aslu.v`
106			`wire rRWE; // From decode of aeMB_decode.v`
107			`wire [31:0] rSIMM; // From decode of aeMB_decode.v`
108			`// End of automatics`
109
110			`aeMB_regfile #(DSIZ)`
111			`regfile (/AUTOINST/`
112			`// Outputs`
113			`.dwb_dat_o (dwb_dat_o[31:0]),`
114			`.rREGA (rREGA[31:0]),`
115			`.rREGB (rREGB[31:0]),`
116			`// Inputs`
117			`.dwb_dat_i (dwb_dat_i[31:0]),`
118			`.rDWBSTB (rDWBSTB),`
119			`.rDWBWE (rDWBWE),`
120			`.rRA (rRA[4:0]),`
121			`.rRB (rRB[4:0]),`
122			`.rRD (rRD[4:0]),`
123			`.rRD_ (rRD_[4:0]),`
124			`.rRESULT (rRESULT[31:0]),`
125			`.rFSM (rFSM[1:0]),`
126			`.rPC (rPC[31:0]),`
127			`.rPCNXT (rPCNXT[31:0]),`
128			`.rLNK (rLNK),`
129			`.rRWE (rRWE),`
130			`.nclk (nclk),`
131			`.nrst (nrst),`
132			`.drun (drun),`
133			`.drst (drst));`
134
135			`aeMB_fetch #(ISIZ)`
136			`fetch (/AUTOINST/`
137			`// Outputs`
138			`.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),`
139			`.rPC (rPC[31:0]),`
140			`.rPCNXT (rPCNXT[31:0]),`
141			`// Inputs`
142			`.iwb_dat_i (iwb_dat_i[31:0]),`
143			`.nclk (nclk),`
144			`.nrst (nrst),`
145			`.frun (frun),`
146			`.rFSM (rFSM[1:0]),`
147			`.rBRA (rBRA),`
148			`.rRESULT (rRESULT[31:0]));`
149
150			`aeMB_control`
151			`control (/AUTOINST/`
152			`// Outputs`
153			`.rFSM (rFSM[1:0]),`
154			`.nclk (nclk),`
155			`.nrst (nrst),`
156			`.frun (frun),`
157			`.drun (drun),`
158			`.frst (frst),`
159			`.drst (drst),`
160			`// Inputs`
161			`.sys_rst_i (sys_rst_i),`
162			`.sys_clk_i (sys_clk_i),`
163			`.sys_int_i (sys_int_i),`
164			`.sys_exc_i (sys_exc_i),`
165			`.sys_run_i (sys_run_i),`
166			`.rIWBSTB (rIWBSTB),`
167			`.iwb_ack_i (iwb_ack_i),`
168			`.rDWBSTB (rDWBSTB),`
169			`.dwb_ack_i (dwb_ack_i),`
170			`.rBRA (rBRA),`
171			`.rDLY (rDLY));`
172
173			`aeMB_aslu #(DSIZ)`
174			`aslu (/AUTOINST/`
175			`// Outputs`
176			`.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),`
177			`.rRESULT (rRESULT[31:0]),`
178			`// Inputs`
179			`.dwb_dat_i (dwb_dat_i[31:0]),`
180			`.rBRA (rBRA),`
181			`.rDLY (rDLY),`
182			`.rREGA (rREGA[31:0]),`
183			`.rREGB (rREGB[31:0]),`
184			`.rSIMM (rSIMM[31:0]),`
185			`.rMXSRC (rMXSRC[1:0]),`
186			`.rMXTGT (rMXTGT[1:0]),`
187			`.rMXALU (rMXALU[1:0]),`
188			`.rOPC (rOPC[5:0]),`
189			`.rPC (rPC[31:0]),`
190			`.rIMM (rIMM[15:0]),`
191			`.rRD (rRD[4:0]),`
192			`.rRA (rRA[4:0]),`
193	11	sybreon	`.rMXLDST (rMXLDST[1:0]),`
194	3	sybreon	`.nclk (nclk),`
195			`.nrst (nrst),`
196			`.drun (drun),`
197			`.drst (drst));`
198
199
200			`aeMB_decode`
201			`decode (/AUTOINST/`
202			`// Outputs`
203			`.rSIMM (rSIMM[31:0]),`
204			`.rMXALU (rMXALU[1:0]),`
205			`.rMXSRC (rMXSRC[1:0]),`
206			`.rMXTGT (rMXTGT[1:0]),`
207			`.rRA (rRA[4:0]),`
208			`.rRB (rRB[4:0]),`
209			`.rRD (rRD[4:0]),`
210			`.rRD_ (rRD_[4:0]),`
211			`.rOPC (rOPC[5:0]),`
212			`.rIMM (rIMM[15:0]),`
213			`.rDWBSTB (rDWBSTB),`
214			`.rDWBWE (rDWBWE),`
215			`.rIWBSTB (rIWBSTB),`
216			`.rDLY (rDLY),`
217			`.rLNK (rLNK),`
218			`.rBRA (rBRA),`
219			`.rRWE (rRWE),`
220	11	sybreon	`.rMXLDST (rMXLDST[1:0]),`
221	3	sybreon	`.iwb_stb_o (iwb_stb_o),`
222			`.dwb_stb_o (dwb_stb_o),`
223			`.dwb_we_o (dwb_we_o),`
224			`// Inputs`
225			`.rREGA (rREGA[31:0]),`
226			`.rRESULT (rRESULT[31:0]),`
227			`.iwb_dat_i (iwb_dat_i[31:0]),`
228			`.dwb_dat_i (dwb_dat_i[31:0]),`
229			`.nclk (nclk),`
230			`.nrst (nrst),`
231			`.drun (drun),`
232			`.frun (frun),`
233			`.frst (frst),`
234			`.drst (drst));`
235
236
237			`endmodule // aeMB_core`

Browse

Tools

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_core.v] - Blame information for rev 11