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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_ctrl.v] - Blame information for rev 191

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1 72 sybreon
// $Id: aeMB_ctrl.v,v 1.10 2007-11-30 16:44:40 sybreon Exp $
2 41 sybreon
//
3
// AEMB CONTROL UNIT
4
// 
5
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
6
//  
7 55 sybreon
// This file is part of AEMB.
8 41 sybreon
//
9 55 sybreon
// AEMB is free software: you can redistribute it and/or modify it
10
// under the terms of the GNU Lesser General Public License as
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// published by the Free Software Foundation, either version 3 of the
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// License, or (at your option) any later version.
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//
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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// Public License for more details.
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//
19 41 sybreon
// You should have received a copy of the GNU Lesser General Public
20 55 sybreon
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
21 41 sybreon
//
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// $Log: not supported by cvs2svn $
23 72 sybreon
// Revision 1.9  2007/11/15 09:26:43  sybreon
24
// Fixed minor typo causing synthesis failure.
25
//
26 65 sybreon
// Revision 1.8  2007/11/14 23:19:24  sybreon
27
// Fixed minor typo.
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//
29 62 sybreon
// Revision 1.7  2007/11/14 22:14:34  sybreon
30
// Changed interrupt handling system (reported by M. Ettus).
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//
32 61 sybreon
// Revision 1.6  2007/11/10 16:39:38  sybreon
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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//
36 55 sybreon
// Revision 1.5  2007/11/09 20:51:52  sybreon
37
// Added GET/PUT support through a FSL bus.
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//
39 53 sybreon
// Revision 1.4  2007/11/08 17:48:14  sybreon
40
// Fixed data WISHBONE arbitration problem (reported by J Lee).
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//
42 51 sybreon
// Revision 1.3  2007/11/08 14:17:47  sybreon
43
// Parameterised optional components.
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//
45 50 sybreon
// Revision 1.2  2007/11/02 19:20:58  sybreon
46
// Added better (beta) interrupt support.
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// Changed MSR_IE to disabled at reset as per MB docs.
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//
49 44 sybreon
// Revision 1.1  2007/11/02 03:25:40  sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
54 41 sybreon
 
55
module aeMB_ctrl (/*AUTOARG*/
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   // Outputs
57 62 sybreon
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
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   fsl_stb_o, fsl_wre_o,
59 41 sybreon
   // Inputs
60 61 sybreon
   rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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   dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
62 41 sybreon
   );
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   // INTERNAL   
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   //output [31:2] rPCLNK;
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   output [1:0]  rMXDST;
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   output [1:0]  rMXSRC, rMXTGT, rMXALT;
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   output [2:0]  rMXALU;
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   output [4:0]  rRW;
69 53 sybreon
 
70 41 sybreon
   input         rDLY;
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   input [15:0]  rIMM;
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   input [10:0]  rALT;
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   input [5:0]    rOPC;
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   input [4:0]    rRD, rRA, rRB;
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   input [31:2]  rPC;
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   input         rBRA;
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   input         rMSR_IE;
78 61 sybreon
   input [31:0]  xIREG;
79 41 sybreon
 
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   // DATA WISHBONE
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   output        dwb_stb_o;
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   output        dwb_wre_o;
83 51 sybreon
   input         dwb_ack_i;
84
 
85
   // INST WISHBONE
86 55 sybreon
   input         iwb_ack_i;
87 41 sybreon
 
88 53 sybreon
   // FSL WISHBONE
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   output        fsl_stb_o;
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   output        fsl_wre_o;
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   input         fsl_ack_i;
92
 
93 41 sybreon
   // SYSTEM
94
   input         gclk, grst, gena;
95
 
96
   // --- DECODE INSTRUCTIONS
97
   // TODO: Simplify
98
 
99 55 sybreon
   wire [5:0]     wOPC;
100
   wire [4:0]     wRD, wRA, wRB;
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   wire [10:0]    wALT;
102
 
103 61 sybreon
   assign        {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
104 55 sybreon
 
105 41 sybreon
   wire          fSFT = (rOPC == 6'o44);
106
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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108
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
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   wire          fDIV = (rOPC == 6'o22);
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112
   wire          fRTD = (rOPC == 6'o55);
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   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
115
   wire          fBRA = fBRU & rRA[3];
116
 
117
   wire          fIMM = (rOPC == 6'o54);
118
   wire          fMOV = (rOPC == 6'o45);
119
 
120
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
122
   wire          fLDST = (&rOPC[5:4]);
123
 
124 53 sybreon
   wire          fPUT = (rOPC == 6'o33) & rRB[4];
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   wire          fGET = (rOPC == 6'o33) & !rRB[4];
126 55 sybreon
 
127
 
128
   wire          wSFT = (wOPC == 6'o44);
129
   wire          wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
130
 
131
   wire          wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
132
   wire          wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
133
   wire          wDIV = (wOPC == 6'o22);
134 41 sybreon
 
135 55 sybreon
   wire          wRTD = (wOPC == 6'o55);
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   wire          wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
137
   wire          wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
138
   wire          wBRA = wBRU & wRA[3];
139
 
140
   wire          wIMM = (wOPC == 6'o54);
141
   wire          wMOV = (wOPC == 6'o45);
142
 
143
   wire          wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
144
   wire          wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
145
   wire          wLDST = (&wOPC[5:4]);
146
 
147
   wire          wPUT = (wOPC == 6'o33) & wRB[4];
148
   wire          wGET = (wOPC == 6'o33) & !wRB[4];
149
 
150
 
151
   // --- BRANCH SLOT REGISTERS ---------------------------
152
 
153
   reg [31:2]    rPCLNK, xPCLNK;
154
   reg [1:0]      rMXDST, xMXDST;
155
   reg [4:0]      rRW, xRW;
156
 
157
   reg [1:0]      rMXSRC, xMXSRC;
158
   reg [1:0]      rMXTGT, xMXTGT;
159
   reg [1:0]      rMXALT, xMXALT;
160
 
161
 
162 41 sybreon
   // --- OPERAND SELECTOR ---------------------------------
163
 
164 55 sybreon
   wire          wRDWE = |xRW;
165
   wire          wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
166
   wire          wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
167
   wire          wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
168
   wire          wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
169
 
170 61 sybreon
   always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
171
            or wBFWD_R or wBRU or wOPC)
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     //if (rBRA | |rXCE) begin
173
     if (rBRA) begin
174 55 sybreon
        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
176
        xMXALT <= 2'h0;
177
        xMXSRC <= 2'h0;
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        xMXTGT <= 2'h0;
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        // End of automatics
180
     end else begin
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        xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
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                  (wAFWD_M) ? 2'o2 : // RAM
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                  (wAFWD_R) ? 2'o1 : // FWD
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                  2'o0; // REG
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        xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
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                  (wBFWD_M) ? 2'o2 : // RAM
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                  (wBFWD_R) ? 2'o1 : // FWD
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                  2'o0; // REG
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        xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
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                  (wAFWD_R) ? 2'o1 : // FWD
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                  2'o0; // REG  
192 72 sybreon
     end // else: !if(rBRA)
193 41 sybreon
 
194
   // --- ALU CONTROL ---------------------------------------
195
 
196 55 sybreon
   reg [2:0]     rMXALU, xMXALU;
197
 
198 61 sybreon
   always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
199
            or wMUL or wSFT)
200
     //if (rBRA | |rXCE) begin
201
     if (rBRA) begin
202 55 sybreon
        /*AUTORESET*/
203
        // Beginning of autoreset for uninitialized flops
204
        xMXALU <= 3'h0;
205
        // End of automatics
206
     end else begin
207
        xMXALU <= (wBRA | wMOV) ? 3'o3 :
208
                  (wSFT) ? 3'o2 :
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                  (wLOG) ? 3'o1 :
210
                  (wMUL) ? 3'o4 :
211
                  (wBSF) ? 3'o5 :
212
                  (wDIV) ? 3'o6 :
213
                  3'o0;
214 72 sybreon
     end // else: !if(rBRA)
215 41 sybreon
 
216
   // --- DELAY SLOT REGISTERS ------------------------------
217
 
218 50 sybreon
   wire          fSKIP = (rBRA & !rDLY);
219 51 sybreon
 
220 53 sybreon
   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
221 61 sybreon
            or fSTR or rRD)
222 41 sybreon
     if (fSKIP) begin
223
        /*AUTORESET*/
224
        // Beginning of autoreset for uninitialized flops
225
        xMXDST <= 2'h0;
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        xRW <= 5'h0;
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        // End of automatics
228
     end else begin
229 61 sybreon
        xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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                  (fLOD | fGET) ? 2'o2 :
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                  (fBRU) ? 2'o1 :
232
                  2'o0;
233
        xRW <= rRD;
234 44 sybreon
     end // else: !if(fSKIP)
235 53 sybreon
 
236
 
237
   // --- DATA WISHBONE ----------------------------------
238
 
239 65 sybreon
   wire          fDACK = !(dwb_stb_o ^ dwb_ack_i);
240 41 sybreon
 
241 53 sybreon
   reg           rDWBSTB, xDWBSTB;
242
   reg           rDWBWRE, xDWBWRE;
243
 
244
   assign        dwb_stb_o = rDWBSTB;
245
   assign        dwb_wre_o = rDWBWRE;
246 41 sybreon
 
247 53 sybreon
 
248 61 sybreon
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
249
     //if (fSKIP | |rXCE) begin
250
     if (fSKIP) begin
251 41 sybreon
        /*AUTORESET*/
252
        // Beginning of autoreset for uninitialized flops
253 53 sybreon
        xDWBSTB <= 1'h0;
254
        xDWBWRE <= 1'h0;
255 41 sybreon
        // End of automatics
256 53 sybreon
     end else begin
257
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
258
        xDWBWRE <= fSTR & iwb_ack_i;
259 51 sybreon
     end
260 53 sybreon
 
261 51 sybreon
   always @(posedge gclk)
262
     if (grst) begin
263
        /*AUTORESET*/
264
        // Beginning of autoreset for uninitialized flops
265
        rDWBSTB <= 1'h0;
266
        rDWBWRE <= 1'h0;
267
        // End of automatics
268
     end else if (fDACK) begin
269 41 sybreon
        rDWBSTB <= #1 xDWBSTB;
270
        rDWBWRE <= #1 xDWBWRE;
271 72 sybreon
     end
272 41 sybreon
 
273 53 sybreon
 
274
   // --- FSL WISHBONE -----------------------------------
275
 
276 65 sybreon
   wire          fFACK = !(fsl_stb_o ^ fsl_ack_i);
277 53 sybreon
 
278
   reg           rFSLSTB, xFSLSTB;
279
   reg           rFSLWRE, xFSLWRE;
280
 
281
   assign        fsl_stb_o = rFSLSTB;
282
   assign        fsl_wre_o = rFSLWRE;
283
 
284 61 sybreon
   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
285
     //if (fSKIP | |rXCE) begin
286
     if (fSKIP) begin
287 53 sybreon
        /*AUTORESET*/
288
        // Beginning of autoreset for uninitialized flops
289
        xFSLSTB <= 1'h0;
290
        xFSLWRE <= 1'h0;
291
        // End of automatics
292
     end else begin
293
        xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
294
        xFSLWRE <= fPUT & iwb_ack_i;
295
     end
296
 
297
   always @(posedge gclk)
298
     if (grst) begin
299
        /*AUTORESET*/
300
        // Beginning of autoreset for uninitialized flops
301
        rFSLSTB <= 1'h0;
302
        rFSLWRE <= 1'h0;
303
        // End of automatics
304
     end else if (fFACK) begin
305
        rFSLSTB <= #1 xFSLSTB;
306
        rFSLWRE <= #1 xFSLWRE;
307
     end
308 41 sybreon
 
309 53 sybreon
   // --- PIPELINE CONTROL DELAY ----------------------------
310
 
311
   always @(posedge gclk)
312
     if (grst) begin
313
        /*AUTORESET*/
314
        // Beginning of autoreset for uninitialized flops
315 55 sybreon
        rMXALT <= 2'h0;
316
        rMXALU <= 3'h0;
317 53 sybreon
        rMXDST <= 2'h0;
318 55 sybreon
        rMXSRC <= 2'h0;
319
        rMXTGT <= 2'h0;
320 53 sybreon
        rRW <= 5'h0;
321
        // End of automatics
322 72 sybreon
     end else if (gena) begin // if (grst)
323 53 sybreon
        //rPCLNK <= #1 xPCLNK;
324
        rMXDST <= #1 xMXDST;
325
        rRW <= #1 xRW;
326 55 sybreon
        rMXSRC <= #1 xMXSRC;
327
        rMXTGT <= #1 xMXTGT;
328
        rMXALT <= #1 xMXALT;
329
        rMXALU <= #1 xMXALU;
330 53 sybreon
     end
331
 
332
 
333 41 sybreon
endmodule // aeMB_ctrl

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