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// $Id: aeMB_ctrl.v,v 1.6 2007-11-10 16:39:38 sybreon Exp $
//
// AEMB CONTROL UNIT
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.4  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_ctrl (/*AUTOARG*/
   // Outputs
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
   dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
   // Inputs
   rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
   dwb_ack_i, iwb_ack_i, iwb_dat_i, fsl_ack_i, gclk, grst, gena
   );
   // INTERNAL   
   //output [31:2] rPCLNK;
   output [1:0]  rMXDST;
   output [1:0]  rMXSRC, rMXTGT, rMXALT;
   output [2:0]  rMXALU;
   output [4:0]  rRW;
   output        rDWBSTB;
   output        rFSLSTB;
 
   input [1:0]    rXCE;
   input         rDLY;
   input [15:0]  rIMM;
   input [10:0]  rALT;
   input [5:0]    rOPC;
   input [4:0]    rRD, rRA, rRB;
   input [31:2]  rPC;
   input         rBRA;
   input         rMSR_IE;
 
   // DATA WISHBONE
   output        dwb_stb_o;
   output        dwb_wre_o;
   input         dwb_ack_i;
 
   // INST WISHBONE
   input         iwb_ack_i;
   input [31:0]  iwb_dat_i;
 
   // FSL WISHBONE
   output        fsl_stb_o;
   output        fsl_wre_o;
   input         fsl_ack_i;
 
   // SYSTEM
   input         gclk, grst, gena;
 
   // --- DECODE INSTRUCTIONS
   // TODO: Simplify
 
   wire [5:0]     wOPC;
   wire [4:0]     wRD, wRA, wRB;
   wire [10:0]    wALT;
 
   assign        {wOPC, wRD, wRA, wRB, wALT} = iwb_dat_i; // FIXME: Endian
 
   wire          fSFT = (rOPC == 6'o44);
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
 
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire          fDIV = (rOPC == 6'o22);
 
   wire          fRTD = (rOPC == 6'o55);
   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire          fBRA = fBRU & rRA[3];
 
   wire          fIMM = (rOPC == 6'o54);
   wire          fMOV = (rOPC == 6'o45);
 
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire          fLDST = (&rOPC[5:4]);
 
   wire          fPUT = (rOPC == 6'o33) & rRB[4];
   wire          fGET = (rOPC == 6'o33) & !rRB[4];
 
 
   wire          wSFT = (wOPC == 6'o44);
   wire          wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
 
   wire          wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire          wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   wire          wDIV = (wOPC == 6'o22);
 
   wire          wRTD = (wOPC == 6'o55);
   wire          wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire          wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   wire          wBRA = wBRU & wRA[3];
 
   wire          wIMM = (wOPC == 6'o54);
   wire          wMOV = (wOPC == 6'o45);
 
   wire          wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire          wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   wire          wLDST = (&wOPC[5:4]);
 
   wire          wPUT = (wOPC == 6'o33) & wRB[4];
   wire          wGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // --- BRANCH SLOT REGISTERS ---------------------------
 
   reg [31:2]    rPCLNK, xPCLNK;
   reg [1:0]      rMXDST, xMXDST;
   reg [4:0]      rRW, xRW;
 
   reg [1:0]      rMXSRC, xMXSRC;
   reg [1:0]      rMXTGT, xMXTGT;
   reg [1:0]      rMXALT, xMXALT;
 
 
   // --- OPERAND SELECTOR ---------------------------------
 
   /*
   wire          fRDWE = |rRW;
   wire          fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
   wire          fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
   wire          fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
   wire          fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
 
   assign        rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
                          (fAFWD_M) ? 2'o2: // RAM
                          (fAFWD_R) ? 2'o1: // FWD
                          2'o0; // REG
 
   assign        rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
                          (fBFWD_M) ? 2'o2 : // RAM
                          (fBFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
   assign        rMXALT = (fAFWD_M) ? 2'o2 : // RAM
                          (fAFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
   */
 
   wire          wRDWE = |xRW;
   wire          wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
   wire          wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
   wire          wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
   wire          wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
 
   always @(/*AUTOSENSE*/rBRA or rXCE or wAFWD_M or wAFWD_R or wBCC
            or wBFWD_M or wBFWD_R or wBRU or wOPC)
     if (rBRA | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALT <= 2'h0;
        xMXSRC <= 2'h0;
        xMXTGT <= 2'h0;
        // End of automatics
     end else begin
        xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
                  (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
                  (wBFWD_M) ? 2'o2 : // RAM
                  (wBFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG  
     end
 
   // --- ALU CONTROL ---------------------------------------
 
   /*
   reg [2:0]     rMXALU;
   always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
     or fSFT) begin
      rMXALU <= (fBRA | fMOV) ? 3'o3 :
                (fSFT) ? 3'o2 :
                (fLOG) ? 3'o1 :
                (fMUL) ? 3'o4 :
                (fBSF) ? 3'o5 :
                (fDIV) ? 3'o6 :
                3'o0;
   end
    */
 
   reg [2:0]     rMXALU, xMXALU;
 
   always @(/*AUTOSENSE*/rBRA or rXCE or wBRA or wBSF or wDIV or wLOG
            or wMOV or wMUL or wSFT)
     if (rBRA | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALU <= 3'h0;
        // End of automatics
     end else begin
        xMXALU <= (wBRA | wMOV) ? 3'o3 :
                  (wSFT) ? 3'o2 :
                  (wLOG) ? 3'o1 :
                  (wMUL) ? 3'o4 :
                  (wBSF) ? 3'o5 :
                  (wDIV) ? 3'o6 :
                  3'o0;
     end
 
   // --- DELAY SLOT REGISTERS ------------------------------
 
   wire          fSKIP = (rBRA & !rDLY);
 
   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
            or fSTR or rRD or rXCE)
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXDST <= 2'h0;
        xRW <= 5'h0;
        // End of automatics
     end else begin
        case (rXCE)
          2'o2: xMXDST <= 2'o1;
          default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                             (fLOD | fGET) ? 2'o2 :
                             (fBRU) ? 2'o1 :
                             2'o0;
        endcase
 
        case (rXCE)
          2'o2: xRW <= 5'd14;
          default: xRW <= rRD;
        endcase
 
     end // else: !if(fSKIP)
 
 
   // --- DATA WISHBONE ----------------------------------
 
   wire          fDACK = !(rDWBSTB ^ dwb_ack_i);
 
   reg           rDWBSTB, xDWBSTB;
   reg           rDWBWRE, xDWBWRE;
 
   assign        dwb_stb_o = rDWBSTB;
   assign        dwb_wre_o = rDWBWRE;
 
 
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
     if (fSKIP | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xDWBSTB <= 1'h0;
        xDWBWRE <= 1'h0;
        // End of automatics
     end else begin
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
        xDWBWRE <= fSTR & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rDWBSTB <= 1'h0;
        rDWBWRE <= 1'h0;
        // End of automatics
     end else if (fDACK) begin
        rDWBSTB <= #1 xDWBSTB;
        rDWBWRE <= #1 xDWBWRE;
     end
 
 
   // --- FSL WISHBONE -----------------------------------
 
   wire          fFACK = !(rFSLSTB ^ fsl_ack_i);
 
   reg           rFSLSTB, xFSLSTB;
   reg           rFSLWRE, xFSLWRE;
 
   assign        fsl_stb_o = rFSLSTB;
   assign        fsl_wre_o = rFSLWRE;
 
   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
     if (fSKIP | |rXCE) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xFSLSTB <= 1'h0;
        xFSLWRE <= 1'h0;
        // End of automatics
     end else begin
        xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
        xFSLWRE <= fPUT & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFSLSTB <= 1'h0;
        rFSLWRE <= 1'h0;
        // End of automatics
     end else if (fFACK) begin
        rFSLSTB <= #1 xFSLSTB;
        rFSLWRE <= #1 xFSLWRE;
     end
 
   // --- PIPELINE CONTROL DELAY ----------------------------
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMXALT <= 2'h0;
        rMXALU <= 3'h0;
        rMXDST <= 2'h0;
        rMXSRC <= 2'h0;
        rMXTGT <= 2'h0;
        rRW <= 5'h0;
        // End of automatics
     end else if (gena) begin
        //rPCLNK <= #1 xPCLNK;
        rMXDST <= #1 xMXDST;
        rRW <= #1 xRW;
        rMXSRC <= #1 xMXSRC;
        rMXTGT <= #1 xMXTGT;
        rMXALT <= #1 xMXALT;
        rMXALU <= #1 xMXALU;
     end
 
 
endmodule // aeMB_ctrl

Line No.	Rev	Author	Line
1	55	sybreon	`// $Id: aeMB_ctrl.v,v 1.6 2007-11-10 16:39:38 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB CONTROL UNIT`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	55	sybreon	`// Revision 1.5 2007/11/09 20:51:52 sybreon`
24			`// Added GET/PUT support through a FSL bus.`
25			`//`
26	53	sybreon	`// Revision 1.4 2007/11/08 17:48:14 sybreon`
27			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
28			`//`
29	51	sybreon	`// Revision 1.3 2007/11/08 14:17:47 sybreon`
30			`// Parameterised optional components.`
31			`//`
32	50	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
33			`// Added better (beta) interrupt support.`
34			`// Changed MSR_IE to disabled at reset as per MB docs.`
35			`//`
36	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
37			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
38			`// Fixed various minor data hazard bugs.`
39			`// Code compatible with -O0/1/2/3/s generated code.`
40			`//`
41	41	sybreon
42			`module aeMB_ctrl (/AUTOARG/`
43			`// Outputs`
44	53	sybreon	`rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,`
45			`dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,`
46	41	sybreon	`// Inputs`
47	44	sybreon	`rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,`
48	55	sybreon	`dwb_ack_i, iwb_ack_i, iwb_dat_i, fsl_ack_i, gclk, grst, gena`
49	41	sybreon	`);`
50			`// INTERNAL`
51			`//output [31:2] rPCLNK;`
52			`output [1:0] rMXDST;`
53			`output [1:0] rMXSRC, rMXTGT, rMXALT;`
54			`output [2:0] rMXALU;`
55			`output [4:0] rRW;`
56	53	sybreon	`output rDWBSTB;`
57			`output rFSLSTB;`
58
59	44	sybreon	`input [1:0] rXCE;`
60	41	sybreon	`input rDLY;`
61			`input [15:0] rIMM;`
62			`input [10:0] rALT;`
63			`input [5:0] rOPC;`
64			`input [4:0] rRD, rRA, rRB;`
65			`input [31:2] rPC;`
66			`input rBRA;`
67			`input rMSR_IE;`
68
69			`// DATA WISHBONE`
70			`output dwb_stb_o;`
71			`output dwb_wre_o;`
72	51	sybreon	`input dwb_ack_i;`
73
74			`// INST WISHBONE`
75	55	sybreon	`input iwb_ack_i;`
76			`input [31:0] iwb_dat_i;`
77	41	sybreon
78	53	sybreon	`// FSL WISHBONE`
79			`output fsl_stb_o;`
80			`output fsl_wre_o;`
81			`input fsl_ack_i;`
82
83	41	sybreon	`// SYSTEM`
84			`input gclk, grst, gena;`
85
86			`// --- DECODE INSTRUCTIONS`
87			`// TODO: Simplify`
88
89	55	sybreon	`wire [5:0] wOPC;`
90			`wire [4:0] wRD, wRA, wRB;`
91			`wire [10:0] wALT;`
92
93			`assign {wOPC, wRD, wRA, wRB, wALT} = iwb_dat_i; // FIXME: Endian`
94
95	41	sybreon	`wire fSFT = (rOPC == 6'o44);`
96			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
97
98			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
99			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
100			`wire fDIV = (rOPC == 6'o22);`
101
102			`wire fRTD = (rOPC == 6'o55);`
103			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
104			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
105			`wire fBRA = fBRU & rRA[3];`
106
107			`wire fIMM = (rOPC == 6'o54);`
108			`wire fMOV = (rOPC == 6'o45);`
109
110			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
111			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
112			`wire fLDST = (&rOPC[5:4]);`
113
114	53	sybreon	`wire fPUT = (rOPC == 6'o33) & rRB[4];`
115			`wire fGET = (rOPC == 6'o33) & !rRB[4];`
116	55	sybreon
117
118			`wire wSFT = (wOPC == 6'o44);`
119			`wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
120
121			`wire wMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
122			`wire wBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
123			`wire wDIV = (wOPC == 6'o22);`
124	41	sybreon
125	55	sybreon	`wire wRTD = (wOPC == 6'o55);`
126			`wire wBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
127			`wire wBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
128			`wire wBRA = wBRU & wRA[3];`
129
130			`wire wIMM = (wOPC == 6'o54);`
131			`wire wMOV = (wOPC == 6'o45);`
132
133			`wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
134			`wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
135			`wire wLDST = (&wOPC[5:4]);`
136
137			`wire wPUT = (wOPC == 6'o33) & wRB[4];`
138			`wire wGET = (wOPC == 6'o33) & !wRB[4];`
139
140
141			`// --- BRANCH SLOT REGISTERS ---------------------------`
142
143			`reg [31:2] rPCLNK, xPCLNK;`
144			`reg [1:0] rMXDST, xMXDST;`
145			`reg [4:0] rRW, xRW;`
146
147			`reg [1:0] rMXSRC, xMXSRC;`
148			`reg [1:0] rMXTGT, xMXTGT;`
149			`reg [1:0] rMXALT, xMXALT;`
150
151
152	41	sybreon	`// --- OPERAND SELECTOR ---------------------------------`
153
154	55	sybreon	`/*`
155	41	sybreon	`wire fRDWE = \|rRW;`
156			`wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;`
157			`wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;`
158			`wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;`
159			`wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;`
160
161			`assign rMXSRC = (fBRU \| fBCC) ? 2'o3 : // PC`
162			`(fAFWD_M) ? 2'o2: // RAM`
163			`(fAFWD_R) ? 2'o1: // FWD`
164			`2'o0; // REG`
165
166			`assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM`
167			`(fBFWD_M) ? 2'o2 : // RAM`
168			`(fBFWD_R) ? 2'o1 : // FWD`
169			`2'o0; // REG`
170
171			`assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM`
172			`(fAFWD_R) ? 2'o1 : // FWD`
173			`2'o0; // REG`
174	55	sybreon	`*/`
175
176			`wire wRDWE = \|xRW;`
177			`wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;`
178			`wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;`
179			`wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;`
180			`wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;`
181
182			`always @(/AUTOSENSE/rBRA or rXCE or wAFWD_M or wAFWD_R or wBCC`
183			`or wBFWD_M or wBFWD_R or wBRU or wOPC)`
184			`if (rBRA \| \|rXCE) begin`
185			`/AUTORESET/`
186			`// Beginning of autoreset for uninitialized flops`
187			`xMXALT <= 2'h0;`
188			`xMXSRC <= 2'h0;`
189			`xMXTGT <= 2'h0;`
190			`// End of automatics`
191			`end else begin`
192			`xMXSRC <= (wBRU \| wBCC) ? 2'o3 : // PC`
193			`(wAFWD_M) ? 2'o2 : // RAM`
194			`(wAFWD_R) ? 2'o1 : // FWD`
195			`2'o0; // REG`
196			`xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM`
197			`(wBFWD_M) ? 2'o2 : // RAM`
198			`(wBFWD_R) ? 2'o1 : // FWD`
199			`2'o0; // REG`
200			`xMXALT <= (wAFWD_M) ? 2'o2 : // RAM`
201			`(wAFWD_R) ? 2'o1 : // FWD`
202			`2'o0; // REG`
203			`end`
204	41	sybreon
205			`// --- ALU CONTROL ---------------------------------------`
206
207	55	sybreon	`/*`
208	41	sybreon	`reg [2:0] rMXALU;`
209	55	sybreon	`always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL`
210			`or fSFT) begin`
211	41	sybreon	`rMXALU <= (fBRA \| fMOV) ? 3'o3 :`
212			`(fSFT) ? 3'o2 :`
213			`(fLOG) ? 3'o1 :`
214			`(fMUL) ? 3'o4 :`
215			`(fBSF) ? 3'o5 :`
216			`(fDIV) ? 3'o6 :`
217			`3'o0;`
218			`end`
219	55	sybreon	`*/`
220
221			`reg [2:0] rMXALU, xMXALU;`
222
223			`always @(/AUTOSENSE/rBRA or rXCE or wBRA or wBSF or wDIV or wLOG`
224			`or wMOV or wMUL or wSFT)`
225			`if (rBRA \| \|rXCE) begin`
226			`/AUTORESET/`
227			`// Beginning of autoreset for uninitialized flops`
228			`xMXALU <= 3'h0;`
229			`// End of automatics`
230			`end else begin`
231			`xMXALU <= (wBRA \| wMOV) ? 3'o3 :`
232			`(wSFT) ? 3'o2 :`
233			`(wLOG) ? 3'o1 :`
234			`(wMUL) ? 3'o4 :`
235			`(wBSF) ? 3'o5 :`
236			`(wDIV) ? 3'o6 :`
237			`3'o0;`
238			`end`
239	41	sybreon
240			`// --- DELAY SLOT REGISTERS ------------------------------`
241
242	50	sybreon	`wire fSKIP = (rBRA & !rDLY);`
243	51	sybreon
244	53	sybreon	`always @(/AUTOSENSE/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP`
245			`or fSTR or rRD or rXCE)`
246	41	sybreon	`if (fSKIP) begin`
247			`/AUTORESET/`
248			`// Beginning of autoreset for uninitialized flops`
249			`xMXDST <= 2'h0;`
250			`xRW <= 5'h0;`
251			`// End of automatics`
252			`end else begin`
253			`case (rXCE)`
254	44	sybreon	`2'o2: xMXDST <= 2'o1;`
255	41	sybreon	`default: xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
256	53	sybreon	`(fLOD \| fGET) ? 2'o2 :`
257	41	sybreon	`(fBRU) ? 2'o1 :`
258			`2'o0;`
259	44	sybreon	`endcase`
260
261	41	sybreon	`case (rXCE)`
262	44	sybreon	`2'o2: xRW <= 5'd14;`
263	41	sybreon	`default: xRW <= rRD;`
264	44	sybreon	`endcase`
265	41	sybreon
266	44	sybreon	`end // else: !if(fSKIP)`
267	53	sybreon
268
269			`// --- DATA WISHBONE ----------------------------------`
270
271			`wire fDACK = !(rDWBSTB ^ dwb_ack_i);`
272	41	sybreon
273	53	sybreon	`reg rDWBSTB, xDWBSTB;`
274			`reg rDWBWRE, xDWBWRE;`
275
276			`assign dwb_stb_o = rDWBSTB;`
277			`assign dwb_wre_o = rDWBWRE;`
278	41	sybreon
279	53	sybreon
280			`always @(/AUTOSENSE/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)`
281			`if (fSKIP \| \|rXCE) begin`
282	41	sybreon	`/AUTORESET/`
283			`// Beginning of autoreset for uninitialized flops`
284	53	sybreon	`xDWBSTB <= 1'h0;`
285			`xDWBWRE <= 1'h0;`
286	41	sybreon	`// End of automatics`
287	53	sybreon	`end else begin`
288			`xDWBSTB <= (fLOD \| fSTR) & iwb_ack_i;`
289			`xDWBWRE <= fSTR & iwb_ack_i;`
290	51	sybreon	`end`
291	53	sybreon
292	51	sybreon	`always @(posedge gclk)`
293			`if (grst) begin`
294			`/AUTORESET/`
295			`// Beginning of autoreset for uninitialized flops`
296			`rDWBSTB <= 1'h0;`
297			`rDWBWRE <= 1'h0;`
298			`// End of automatics`
299			`end else if (fDACK) begin`
300	41	sybreon	`rDWBSTB <= #1 xDWBSTB;`
301			`rDWBWRE <= #1 xDWBWRE;`
302	51	sybreon	`end`
303	41	sybreon
304	53	sybreon
305			`// --- FSL WISHBONE -----------------------------------`
306
307			`wire fFACK = !(rFSLSTB ^ fsl_ack_i);`
308
309			`reg rFSLSTB, xFSLSTB;`
310			`reg rFSLWRE, xFSLWRE;`
311
312			`assign fsl_stb_o = rFSLSTB;`
313			`assign fsl_wre_o = rFSLWRE;`
314
315			`always @(/AUTOSENSE/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)`
316			`if (fSKIP \| \|rXCE) begin`
317			`/AUTORESET/`
318			`// Beginning of autoreset for uninitialized flops`
319			`xFSLSTB <= 1'h0;`
320			`xFSLWRE <= 1'h0;`
321			`// End of automatics`
322			`end else begin`
323			`xFSLSTB <= (fPUT \| fGET) & iwb_ack_i;`
324			`xFSLWRE <= fPUT & iwb_ack_i;`
325			`end`
326
327			`always @(posedge gclk)`
328			`if (grst) begin`
329			`/AUTORESET/`
330			`// Beginning of autoreset for uninitialized flops`
331			`rFSLSTB <= 1'h0;`
332			`rFSLWRE <= 1'h0;`
333			`// End of automatics`
334			`end else if (fFACK) begin`
335			`rFSLSTB <= #1 xFSLSTB;`
336			`rFSLWRE <= #1 xFSLWRE;`
337			`end`
338	41	sybreon
339	53	sybreon	`// --- PIPELINE CONTROL DELAY ----------------------------`
340
341			`always @(posedge gclk)`
342			`if (grst) begin`
343			`/AUTORESET/`
344			`// Beginning of autoreset for uninitialized flops`
345	55	sybreon	`rMXALT <= 2'h0;`
346			`rMXALU <= 3'h0;`
347	53	sybreon	`rMXDST <= 2'h0;`
348	55	sybreon	`rMXSRC <= 2'h0;`
349			`rMXTGT <= 2'h0;`
350	53	sybreon	`rRW <= 5'h0;`
351			`// End of automatics`
352			`end else if (gena) begin`
353			`//rPCLNK <= #1 xPCLNK;`
354			`rMXDST <= #1 xMXDST;`
355			`rRW <= #1 xRW;`
356	55	sybreon	`rMXSRC <= #1 xMXSRC;`
357			`rMXTGT <= #1 xMXTGT;`
358			`rMXALT <= #1 xMXALT;`
359			`rMXALU <= #1 xMXALU;`
360	53	sybreon	`end`
361
362
363	41	sybreon	`endmodule // aeMB_ctrl`

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