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// $Id: aeMB_ctrl.v,v 1.8 2007-11-14 23:19:24 sybreon Exp $
//
// AEMB CONTROL UNIT
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2007/11/14 22:14:34  sybreon
// Changed interrupt handling system (reported by M. Ettus).
//
// Revision 1.6  2007/11/10 16:39:38  sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.5  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.4  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_ctrl (/*AUTOARG*/
   // Outputs
   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
   fsl_stb_o, fsl_wre_o,
   // Inputs
   rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
   dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
   );
   // INTERNAL   
   //output [31:2] rPCLNK;
   output [1:0]  rMXDST;
   output [1:0]  rMXSRC, rMXTGT, rMXALT;
   output [2:0]  rMXALU;
   output [4:0]  rRW;
   //output      rDWBSTB;
   //output      rFSLSTB;
 
   //input [1:0]         rXCE;
   input         rDLY;
   input [15:0]  rIMM;
   input [10:0]  rALT;
   input [5:0]    rOPC;
   input [4:0]    rRD, rRA, rRB;
   input [31:2]  rPC;
   input         rBRA;
   input         rMSR_IE;
   input [31:0]  xIREG;
 
   // DATA WISHBONE
   output        dwb_stb_o;
   output        dwb_wre_o;
   input         dwb_ack_i;
 
   // INST WISHBONE
   input         iwb_ack_i;
 
   // FSL WISHBONE
   output        fsl_stb_o;
   output        fsl_wre_o;
   input         fsl_ack_i;
 
   // SYSTEM
   input         gclk, grst, gena;
 
   // --- DECODE INSTRUCTIONS
   // TODO: Simplify
 
   wire [5:0]     wOPC;
   wire [4:0]     wRD, wRA, wRB;
   wire [10:0]    wALT;
 
   assign        {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
 
   wire          fSFT = (rOPC == 6'o44);
   wire          fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
 
   wire          fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
   wire          fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
   wire          fDIV = (rOPC == 6'o22);
 
   wire          fRTD = (rOPC == 6'o55);
   wire          fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
   wire          fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
   wire          fBRA = fBRU & rRA[3];
 
   wire          fIMM = (rOPC == 6'o54);
   wire          fMOV = (rOPC == 6'o45);
 
   wire          fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
   wire          fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
   wire          fLDST = (&rOPC[5:4]);
 
   wire          fPUT = (rOPC == 6'o33) & rRB[4];
   wire          fGET = (rOPC == 6'o33) & !rRB[4];
 
 
   wire          wSFT = (wOPC == 6'o44);
   wire          wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
 
   wire          wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire          wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   wire          wDIV = (wOPC == 6'o22);
 
   wire          wRTD = (wOPC == 6'o55);
   wire          wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire          wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   wire          wBRA = wBRU & wRA[3];
 
   wire          wIMM = (wOPC == 6'o54);
   wire          wMOV = (wOPC == 6'o45);
 
   wire          wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire          wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   wire          wLDST = (&wOPC[5:4]);
 
   wire          wPUT = (wOPC == 6'o33) & wRB[4];
   wire          wGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // --- BRANCH SLOT REGISTERS ---------------------------
 
   reg [31:2]    rPCLNK, xPCLNK;
   reg [1:0]      rMXDST, xMXDST;
   reg [4:0]      rRW, xRW;
 
   reg [1:0]      rMXSRC, xMXSRC;
   reg [1:0]      rMXTGT, xMXTGT;
   reg [1:0]      rMXALT, xMXALT;
 
 
   // --- OPERAND SELECTOR ---------------------------------
 
   /*
   wire          fRDWE = |rRW;
   wire          fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
   wire          fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
   wire          fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
   wire          fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
 
   assign        rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
                          (fAFWD_M) ? 2'o2: // RAM
                          (fAFWD_R) ? 2'o1: // FWD
                          2'o0; // REG
 
   assign        rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
                          (fBFWD_M) ? 2'o2 : // RAM
                          (fBFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
 
   assign        rMXALT = (fAFWD_M) ? 2'o2 : // RAM
                          (fAFWD_R) ? 2'o1 : // FWD
                          2'o0; // REG
   */
 
   wire          wRDWE = |xRW;
   wire          wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
   wire          wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
   wire          wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
   wire          wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
 
   always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
            or wBFWD_R or wBRU or wOPC)
     //if (rBRA | |rXCE) begin
     if (rBRA) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALT <= 2'h0;
        xMXSRC <= 2'h0;
        xMXTGT <= 2'h0;
        // End of automatics
     end else begin
        xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
                  (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
                  (wBFWD_M) ? 2'o2 : // RAM
                  (wBFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG
        xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
                  (wAFWD_R) ? 2'o1 : // FWD
                  2'o0; // REG  
     end
 
   // --- ALU CONTROL ---------------------------------------
 
   /*
   reg [2:0]     rMXALU;
   always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
     or fSFT) begin
      rMXALU <= (fBRA | fMOV) ? 3'o3 :
                (fSFT) ? 3'o2 :
                (fLOG) ? 3'o1 :
                (fMUL) ? 3'o4 :
                (fBSF) ? 3'o5 :
                (fDIV) ? 3'o6 :
                3'o0;
   end
    */
 
   reg [2:0]     rMXALU, xMXALU;
 
   always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
            or wMUL or wSFT)
     //if (rBRA | |rXCE) begin
     if (rBRA) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXALU <= 3'h0;
        // End of automatics
     end else begin
        xMXALU <= (wBRA | wMOV) ? 3'o3 :
                  (wSFT) ? 3'o2 :
                  (wLOG) ? 3'o1 :
                  (wMUL) ? 3'o4 :
                  (wBSF) ? 3'o5 :
                  (wDIV) ? 3'o6 :
                  3'o0;
     end
 
   // --- DELAY SLOT REGISTERS ------------------------------
 
   wire          fSKIP = (rBRA & !rDLY);
 
   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
            or fSTR or rRD)
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xMXDST <= 2'h0;
        xRW <= 5'h0;
        // End of automatics
     end else begin
        /*
        case (rXCE)
          2'o2: xMXDST <= 2'o1;
          default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                             (fLOD | fGET) ? 2'o2 :
                             (fBRU) ? 2'o1 :
                             2'o0;
        endcase
 
        case (rXCE)
          2'o2: xRW <= 5'd14;
          default: xRW <= rRD;
        endcase
        */
        xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
                  (fLOD | fGET) ? 2'o2 :
                  (fBRU) ? 2'o1 :
                  2'o0;
        xRW <= rRD;
     end // else: !if(fSKIP)
 
 
   // --- DATA WISHBONE ----------------------------------
 
   wire          fDACK = !(rDWBSTB ^ dwb_ack_i);
 
   reg           rDWBSTB, xDWBSTB;
   reg           rDWBWRE, xDWBWRE;
 
   assign        dwb_stb_o = rDWBSTB;
   assign        dwb_wre_o = rDWBWRE;
 
 
   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
     //if (fSKIP | |rXCE) begin
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xDWBSTB <= 1'h0;
        xDWBWRE <= 1'h0;
        // End of automatics
     end else begin
        xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
        xDWBWRE <= fSTR & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rDWBSTB <= 1'h0;
        rDWBWRE <= 1'h0;
        // End of automatics
     end else if (fDACK) begin
        rDWBSTB <= #1 xDWBSTB;
        rDWBWRE <= #1 xDWBWRE;
     end
 
 
   // --- FSL WISHBONE -----------------------------------
 
   wire          fFACK = !(rFSLSTB ^ fsl_ack_i);
 
   reg           rFSLSTB, xFSLSTB;
   reg           rFSLWRE, xFSLWRE;
 
   assign        fsl_stb_o = rFSLSTB;
   assign        fsl_wre_o = rFSLWRE;
 
   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
     //if (fSKIP | |rXCE) begin
     if (fSKIP) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        xFSLSTB <= 1'h0;
        xFSLWRE <= 1'h0;
        // End of automatics
     end else begin
        xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
        xFSLWRE <= fPUT & iwb_ack_i;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFSLSTB <= 1'h0;
        rFSLWRE <= 1'h0;
        // End of automatics
     end else if (fFACK) begin
        rFSLSTB <= #1 xFSLSTB;
        rFSLWRE <= #1 xFSLWRE;
     end
 
   // --- PIPELINE CONTROL DELAY ----------------------------
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rMXALT <= 2'h0;
        rMXALU <= 3'h0;
        rMXDST <= 2'h0;
        rMXSRC <= 2'h0;
        rMXTGT <= 2'h0;
        rRW <= 5'h0;
        // End of automatics
     end else if (gena) begin
        //rPCLNK <= #1 xPCLNK;
        rMXDST <= #1 xMXDST;
        rRW <= #1 xRW;
        rMXSRC <= #1 xMXSRC;
        rMXTGT <= #1 xMXTGT;
        rMXALT <= #1 xMXALT;
        rMXALU <= #1 xMXALU;
     end
 
 
endmodule // aeMB_ctrl

Line No.	Rev	Author	Line
1	62	sybreon	`// $Id: aeMB_ctrl.v,v 1.8 2007-11-14 23:19:24 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB CONTROL UNIT`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	62	sybreon	`// Revision 1.7 2007/11/14 22:14:34 sybreon`
24			`// Changed interrupt handling system (reported by M. Ettus).`
25			`//`
26	61	sybreon	`// Revision 1.6 2007/11/10 16:39:38 sybreon`
27			`// Upgraded license to LGPLv3.`
28			`// Significant performance optimisations.`
29			`//`
30	55	sybreon	`// Revision 1.5 2007/11/09 20:51:52 sybreon`
31			`// Added GET/PUT support through a FSL bus.`
32			`//`
33	53	sybreon	`// Revision 1.4 2007/11/08 17:48:14 sybreon`
34			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
35			`//`
36	51	sybreon	`// Revision 1.3 2007/11/08 14:17:47 sybreon`
37			`// Parameterised optional components.`
38			`//`
39	50	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
40			`// Added better (beta) interrupt support.`
41			`// Changed MSR_IE to disabled at reset as per MB docs.`
42			`//`
43	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
44			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
45			`// Fixed various minor data hazard bugs.`
46			`// Code compatible with -O0/1/2/3/s generated code.`
47			`//`
48	41	sybreon
49			`module aeMB_ctrl (/AUTOARG/`
50			`// Outputs`
51	62	sybreon	`rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,`
52			`fsl_stb_o, fsl_wre_o,`
53	41	sybreon	`// Inputs`
54	61	sybreon	`rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,`
55			`dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena`
56	41	sybreon	`);`
57			`// INTERNAL`
58			`//output [31:2] rPCLNK;`
59			`output [1:0] rMXDST;`
60			`output [1:0] rMXSRC, rMXTGT, rMXALT;`
61			`output [2:0] rMXALU;`
62			`output [4:0] rRW;`
63	62	sybreon	`//output rDWBSTB;`
64			`//output rFSLSTB;`
65	53	sybreon
66	61	sybreon	`//input [1:0] rXCE;`
67	41	sybreon	`input rDLY;`
68			`input [15:0] rIMM;`
69			`input [10:0] rALT;`
70			`input [5:0] rOPC;`
71			`input [4:0] rRD, rRA, rRB;`
72			`input [31:2] rPC;`
73			`input rBRA;`
74			`input rMSR_IE;`
75	61	sybreon	`input [31:0] xIREG;`
76	41	sybreon
77			`// DATA WISHBONE`
78			`output dwb_stb_o;`
79			`output dwb_wre_o;`
80	51	sybreon	`input dwb_ack_i;`
81
82			`// INST WISHBONE`
83	55	sybreon	`input iwb_ack_i;`
84	41	sybreon
85	53	sybreon	`// FSL WISHBONE`
86			`output fsl_stb_o;`
87			`output fsl_wre_o;`
88			`input fsl_ack_i;`
89
90	41	sybreon	`// SYSTEM`
91			`input gclk, grst, gena;`
92
93			`// --- DECODE INSTRUCTIONS`
94			`// TODO: Simplify`
95
96	55	sybreon	`wire [5:0] wOPC;`
97			`wire [4:0] wRD, wRA, wRB;`
98			`wire [10:0] wALT;`
99
100	61	sybreon	`assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian`
101	55	sybreon
102	41	sybreon	`wire fSFT = (rOPC == 6'o44);`
103			`wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);`
104
105			`wire fMUL = (rOPC == 6'o20) \| (rOPC == 6'o30);`
106			`wire fBSF = (rOPC == 6'o21) \| (rOPC == 6'o31);`
107			`wire fDIV = (rOPC == 6'o22);`
108
109			`wire fRTD = (rOPC == 6'o55);`
110			`wire fBCC = (rOPC == 6'o47) \| (rOPC == 6'o57);`
111			`wire fBRU = (rOPC == 6'o46) \| (rOPC == 6'o56);`
112			`wire fBRA = fBRU & rRA[3];`
113
114			`wire fIMM = (rOPC == 6'o54);`
115			`wire fMOV = (rOPC == 6'o45);`
116
117			`wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);`
118			`wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);`
119			`wire fLDST = (&rOPC[5:4]);`
120
121	53	sybreon	`wire fPUT = (rOPC == 6'o33) & rRB[4];`
122			`wire fGET = (rOPC == 6'o33) & !rRB[4];`
123	55	sybreon
124
125			`wire wSFT = (wOPC == 6'o44);`
126			`wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
127
128			`wire wMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
129			`wire wBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
130			`wire wDIV = (wOPC == 6'o22);`
131	41	sybreon
132	55	sybreon	`wire wRTD = (wOPC == 6'o55);`
133			`wire wBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
134			`wire wBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
135			`wire wBRA = wBRU & wRA[3];`
136
137			`wire wIMM = (wOPC == 6'o54);`
138			`wire wMOV = (wOPC == 6'o45);`
139
140			`wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
141			`wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
142			`wire wLDST = (&wOPC[5:4]);`
143
144			`wire wPUT = (wOPC == 6'o33) & wRB[4];`
145			`wire wGET = (wOPC == 6'o33) & !wRB[4];`
146
147
148			`// --- BRANCH SLOT REGISTERS ---------------------------`
149
150			`reg [31:2] rPCLNK, xPCLNK;`
151			`reg [1:0] rMXDST, xMXDST;`
152			`reg [4:0] rRW, xRW;`
153
154			`reg [1:0] rMXSRC, xMXSRC;`
155			`reg [1:0] rMXTGT, xMXTGT;`
156			`reg [1:0] rMXALT, xMXALT;`
157
158
159	41	sybreon	`// --- OPERAND SELECTOR ---------------------------------`
160
161	55	sybreon	`/*`
162	41	sybreon	`wire fRDWE = \|rRW;`
163			`wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;`
164			`wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;`
165			`wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;`
166			`wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;`
167
168			`assign rMXSRC = (fBRU \| fBCC) ? 2'o3 : // PC`
169			`(fAFWD_M) ? 2'o2: // RAM`
170			`(fAFWD_R) ? 2'o1: // FWD`
171			`2'o0; // REG`
172
173			`assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM`
174			`(fBFWD_M) ? 2'o2 : // RAM`
175			`(fBFWD_R) ? 2'o1 : // FWD`
176			`2'o0; // REG`
177
178			`assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM`
179			`(fAFWD_R) ? 2'o1 : // FWD`
180			`2'o0; // REG`
181	55	sybreon	`*/`
182
183			`wire wRDWE = \|xRW;`
184			`wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;`
185			`wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;`
186			`wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;`
187			`wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;`
188
189	61	sybreon	`always @(/AUTOSENSE/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M`
190			`or wBFWD_R or wBRU or wOPC)`
191			`//if (rBRA \| \|rXCE) begin`
192			`if (rBRA) begin`
193	55	sybreon	`/AUTORESET/`
194			`// Beginning of autoreset for uninitialized flops`
195			`xMXALT <= 2'h0;`
196			`xMXSRC <= 2'h0;`
197			`xMXTGT <= 2'h0;`
198			`// End of automatics`
199			`end else begin`
200			`xMXSRC <= (wBRU \| wBCC) ? 2'o3 : // PC`
201			`(wAFWD_M) ? 2'o2 : // RAM`
202			`(wAFWD_R) ? 2'o1 : // FWD`
203			`2'o0; // REG`
204			`xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM`
205			`(wBFWD_M) ? 2'o2 : // RAM`
206			`(wBFWD_R) ? 2'o1 : // FWD`
207			`2'o0; // REG`
208			`xMXALT <= (wAFWD_M) ? 2'o2 : // RAM`
209			`(wAFWD_R) ? 2'o1 : // FWD`
210			`2'o0; // REG`
211			`end`
212	41	sybreon
213			`// --- ALU CONTROL ---------------------------------------`
214
215	55	sybreon	`/*`
216	41	sybreon	`reg [2:0] rMXALU;`
217	55	sybreon	`always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL`
218			`or fSFT) begin`
219	41	sybreon	`rMXALU <= (fBRA \| fMOV) ? 3'o3 :`
220			`(fSFT) ? 3'o2 :`
221			`(fLOG) ? 3'o1 :`
222			`(fMUL) ? 3'o4 :`
223			`(fBSF) ? 3'o5 :`
224			`(fDIV) ? 3'o6 :`
225			`3'o0;`
226			`end`
227	55	sybreon	`*/`
228
229			`reg [2:0] rMXALU, xMXALU;`
230
231	61	sybreon	`always @(/AUTOSENSE/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV`
232			`or wMUL or wSFT)`
233			`//if (rBRA \| \|rXCE) begin`
234			`if (rBRA) begin`
235	55	sybreon	`/AUTORESET/`
236			`// Beginning of autoreset for uninitialized flops`
237			`xMXALU <= 3'h0;`
238			`// End of automatics`
239			`end else begin`
240			`xMXALU <= (wBRA \| wMOV) ? 3'o3 :`
241			`(wSFT) ? 3'o2 :`
242			`(wLOG) ? 3'o1 :`
243			`(wMUL) ? 3'o4 :`
244			`(wBSF) ? 3'o5 :`
245			`(wDIV) ? 3'o6 :`
246			`3'o0;`
247			`end`
248	41	sybreon
249			`// --- DELAY SLOT REGISTERS ------------------------------`
250
251	50	sybreon	`wire fSKIP = (rBRA & !rDLY);`
252	51	sybreon
253	53	sybreon	`always @(/AUTOSENSE/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP`
254	61	sybreon	`or fSTR or rRD)`
255	41	sybreon	`if (fSKIP) begin`
256			`/AUTORESET/`
257			`// Beginning of autoreset for uninitialized flops`
258			`xMXDST <= 2'h0;`
259			`xRW <= 5'h0;`
260			`// End of automatics`
261			`end else begin`
262	61	sybreon	`/*`
263	41	sybreon	`case (rXCE)`
264	44	sybreon	`2'o2: xMXDST <= 2'o1;`
265	41	sybreon	`default: xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
266	53	sybreon	`(fLOD \| fGET) ? 2'o2 :`
267	41	sybreon	`(fBRU) ? 2'o1 :`
268			`2'o0;`
269	44	sybreon	`endcase`
270
271	41	sybreon	`case (rXCE)`
272	44	sybreon	`2'o2: xRW <= 5'd14;`
273	41	sybreon	`default: xRW <= rRD;`
274	44	sybreon	`endcase`
275	61	sybreon	`*/`
276			`xMXDST <= (fSTR \| fRTD \| fBCC) ? 2'o3 :`
277			`(fLOD \| fGET) ? 2'o2 :`
278			`(fBRU) ? 2'o1 :`
279			`2'o0;`
280			`xRW <= rRD;`
281	44	sybreon	`end // else: !if(fSKIP)`
282	53	sybreon
283
284			`// --- DATA WISHBONE ----------------------------------`
285
286			`wire fDACK = !(rDWBSTB ^ dwb_ack_i);`
287	41	sybreon
288	53	sybreon	`reg rDWBSTB, xDWBSTB;`
289			`reg rDWBWRE, xDWBWRE;`
290
291			`assign dwb_stb_o = rDWBSTB;`
292			`assign dwb_wre_o = rDWBWRE;`
293	41	sybreon
294	53	sybreon
295	61	sybreon	`always @(/AUTOSENSE/fLOD or fSKIP or fSTR or iwb_ack_i)`
296			`//if (fSKIP \| \|rXCE) begin`
297			`if (fSKIP) begin`
298	41	sybreon	`/AUTORESET/`
299			`// Beginning of autoreset for uninitialized flops`
300	53	sybreon	`xDWBSTB <= 1'h0;`
301			`xDWBWRE <= 1'h0;`
302	41	sybreon	`// End of automatics`
303	53	sybreon	`end else begin`
304			`xDWBSTB <= (fLOD \| fSTR) & iwb_ack_i;`
305			`xDWBWRE <= fSTR & iwb_ack_i;`
306	51	sybreon	`end`
307	53	sybreon
308	51	sybreon	`always @(posedge gclk)`
309			`if (grst) begin`
310			`/AUTORESET/`
311			`// Beginning of autoreset for uninitialized flops`
312			`rDWBSTB <= 1'h0;`
313			`rDWBWRE <= 1'h0;`
314			`// End of automatics`
315			`end else if (fDACK) begin`
316	41	sybreon	`rDWBSTB <= #1 xDWBSTB;`
317			`rDWBWRE <= #1 xDWBWRE;`
318	51	sybreon	`end`
319	41	sybreon
320	53	sybreon
321			`// --- FSL WISHBONE -----------------------------------`
322
323			`wire fFACK = !(rFSLSTB ^ fsl_ack_i);`
324
325			`reg rFSLSTB, xFSLSTB;`
326			`reg rFSLWRE, xFSLWRE;`
327
328			`assign fsl_stb_o = rFSLSTB;`
329			`assign fsl_wre_o = rFSLWRE;`
330
331	61	sybreon	`always @(/AUTOSENSE/fGET or fPUT or fSKIP or iwb_ack_i)`
332			`//if (fSKIP \| \|rXCE) begin`
333			`if (fSKIP) begin`
334	53	sybreon	`/AUTORESET/`
335			`// Beginning of autoreset for uninitialized flops`
336			`xFSLSTB <= 1'h0;`
337			`xFSLWRE <= 1'h0;`
338			`// End of automatics`
339			`end else begin`
340			`xFSLSTB <= (fPUT \| fGET) & iwb_ack_i;`
341			`xFSLWRE <= fPUT & iwb_ack_i;`
342			`end`
343
344			`always @(posedge gclk)`
345			`if (grst) begin`
346			`/AUTORESET/`
347			`// Beginning of autoreset for uninitialized flops`
348			`rFSLSTB <= 1'h0;`
349			`rFSLWRE <= 1'h0;`
350			`// End of automatics`
351			`end else if (fFACK) begin`
352			`rFSLSTB <= #1 xFSLSTB;`
353			`rFSLWRE <= #1 xFSLWRE;`
354			`end`
355	41	sybreon
356	53	sybreon	`// --- PIPELINE CONTROL DELAY ----------------------------`
357
358			`always @(posedge gclk)`
359			`if (grst) begin`
360			`/AUTORESET/`
361			`// Beginning of autoreset for uninitialized flops`
362	55	sybreon	`rMXALT <= 2'h0;`
363			`rMXALU <= 3'h0;`
364	53	sybreon	`rMXDST <= 2'h0;`
365	55	sybreon	`rMXSRC <= 2'h0;`
366			`rMXTGT <= 2'h0;`
367	53	sybreon	`rRW <= 5'h0;`
368			`// End of automatics`
369			`end else if (gena) begin`
370			`//rPCLNK <= #1 xPCLNK;`
371			`rMXDST <= #1 xMXDST;`
372			`rRW <= #1 xRW;`
373	55	sybreon	`rMXSRC <= #1 xMXSRC;`
374			`rMXTGT <= #1 xMXTGT;`
375			`rMXALT <= #1 xMXALT;`
376			`rMXALU <= #1 xMXALU;`
377	53	sybreon	`end`
378
379
380	41	sybreon	`endmodule // aeMB_ctrl`

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