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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_edk32.v] - Blame information for rev 202

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1 103 sybreon
/* $Id: aeMB_edk32.v,v 1.14 2008-01-19 16:01:22 sybreon Exp $
2 95 sybreon
**
3
** AEMB EDK 3.2 Compatible Core
4
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
5
**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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22
module aeMB_edk32 (/*AUTOARG*/
23
   // Outputs
24 66 sybreon
   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
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   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
26 41 sybreon
   // Inputs
27 61 sybreon
   sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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   dwb_ack_i, sys_clk_i, sys_rst_i
29 41 sybreon
   );
30 50 sybreon
   // Bus widths
31
   parameter IW = 32; /// Instruction bus address width
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   parameter DW = 32; /// Data bus address width
33 41 sybreon
 
34 50 sybreon
   // Optional functions
35 103 sybreon
   parameter MUL = 0; // Multiplier
36 50 sybreon
   parameter BSF = 1; // Barrel Shifter
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38
   /*AUTOOUTPUT*/
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   // Beginning of automatic outputs (from unused autoinst outputs)
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   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
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   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
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   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
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   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
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   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
45 66 sybreon
   output [6:2]         fsl_adr_o;              // From xecu of aeMB_xecu.v
46 53 sybreon
   output [31:0] fsl_dat_o;              // From regf of aeMB_regf.v
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   output               fsl_stb_o;              // From ctrl of aeMB_ctrl.v
48 66 sybreon
   output [1:0]          fsl_tag_o;              // From xecu of aeMB_xecu.v
49 53 sybreon
   output               fsl_wre_o;              // From ctrl of aeMB_ctrl.v
50 41 sybreon
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
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   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
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   // End of automatics
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   /*AUTOINPUT*/
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   // Beginning of automatic inputs (from unused autoinst inputs)
55 61 sybreon
   input                dwb_ack_i;              // To ctrl of aeMB_ctrl.v
56 41 sybreon
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
57 61 sybreon
   input                fsl_ack_i;              // To ctrl of aeMB_ctrl.v
58 53 sybreon
   input [31:0]          fsl_dat_i;              // To regf of aeMB_regf.v
59 61 sybreon
   input                iwb_ack_i;              // To ibuf of aeMB_ibuf.v, ...
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   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v
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   input                sys_int_i;              // To ibuf of aeMB_ibuf.v
62 41 sybreon
   // End of automatics
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   /*AUTOWIRE*/
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   // Beginning of automatic wires (for undeclared instantiated-module outputs)
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   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
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   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
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   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
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   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
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   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
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   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
71 44 sybreon
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
72 41 sybreon
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
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   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
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   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
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   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
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   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
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   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
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   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
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   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
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   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
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   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
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   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
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   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
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   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
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   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
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   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
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   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
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   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
89 96 sybreon
   wire                 rSTALL;                 // From ibuf of aeMB_ibuf.v
90 61 sybreon
   wire [31:0]           xIREG;                  // From ibuf of aeMB_ibuf.v
91 41 sybreon
   // End of automatics
92 61 sybreon
 
93
   input                sys_clk_i;
94
   input                sys_rst_i;
95 96 sybreon
 
96 61 sybreon
   wire                 grst = sys_rst_i;
97
   wire                 gclk = sys_clk_i;
98 96 sybreon
   wire                 gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
99 103 sybreon
   wire                 oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
100 73 sybreon
 
101
   // --- INSTANTIATIONS -------------------------------------
102 50 sybreon
 
103 41 sybreon
   aeMB_ibuf
104
     ibuf (/*AUTOINST*/
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           // Outputs
106
           .rIMM                        (rIMM[15:0]),
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           .rRA                         (rRA[4:0]),
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           .rRD                         (rRD[4:0]),
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           .rRB                         (rRB[4:0]),
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           .rALT                        (rALT[10:0]),
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           .rOPC                        (rOPC[5:0]),
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           .rSIMM                       (rSIMM[31:0]),
113 61 sybreon
           .xIREG                       (xIREG[31:0]),
114 96 sybreon
           .rSTALL                      (rSTALL),
115 41 sybreon
           .iwb_stb_o                   (iwb_stb_o),
116
           // Inputs
117
           .rBRA                        (rBRA),
118 61 sybreon
           .rMSR_IE                     (rMSR_IE),
119
           .rMSR_BIP                    (rMSR_BIP),
120 41 sybreon
           .iwb_dat_i                   (iwb_dat_i[31:0]),
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           .iwb_ack_i                   (iwb_ack_i),
122 61 sybreon
           .sys_int_i                   (sys_int_i),
123 41 sybreon
           .gclk                        (gclk),
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           .grst                        (grst),
125 103 sybreon
           .gena                        (gena),
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           .oena                        (oena));
127 41 sybreon
 
128
   aeMB_ctrl
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     ctrl (/*AUTOINST*/
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           // Outputs
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           .rMXDST                      (rMXDST[1:0]),
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           .rMXSRC                      (rMXSRC[1:0]),
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           .rMXTGT                      (rMXTGT[1:0]),
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           .rMXALT                      (rMXALT[1:0]),
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           .rMXALU                      (rMXALU[2:0]),
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           .rRW                         (rRW[4:0]),
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           .dwb_stb_o                   (dwb_stb_o),
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           .dwb_wre_o                   (dwb_wre_o),
139 53 sybreon
           .fsl_stb_o                   (fsl_stb_o),
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           .fsl_wre_o                   (fsl_wre_o),
141 41 sybreon
           // Inputs
142
           .rDLY                        (rDLY),
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           .rIMM                        (rIMM[15:0]),
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           .rALT                        (rALT[10:0]),
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           .rOPC                        (rOPC[5:0]),
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           .rRD                         (rRD[4:0]),
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           .rRA                         (rRA[4:0]),
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           .rRB                         (rRB[4:0]),
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           .rPC                         (rPC[31:2]),
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           .rBRA                        (rBRA),
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           .rMSR_IE                     (rMSR_IE),
152 61 sybreon
           .xIREG                       (xIREG[31:0]),
153 50 sybreon
           .dwb_ack_i                   (dwb_ack_i),
154 51 sybreon
           .iwb_ack_i                   (iwb_ack_i),
155 53 sybreon
           .fsl_ack_i                   (fsl_ack_i),
156 41 sybreon
           .gclk                        (gclk),
157
           .grst                        (grst),
158 44 sybreon
           .gena                        (gena));
159 41 sybreon
 
160
   aeMB_bpcu #(IW)
161
     bpcu (/*AUTOINST*/
162
           // Outputs
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           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
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           .rPC                         (rPC[31:2]),
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           .rPCLNK                      (rPCLNK[31:2]),
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           .rBRA                        (rBRA),
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           .rDLY                        (rDLY),
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           // Inputs
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           .rMXALT                      (rMXALT[1:0]),
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           .rOPC                        (rOPC[5:0]),
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           .rRD                         (rRD[4:0]),
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           .rRA                         (rRA[4:0]),
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           .rRESULT                     (rRESULT[31:0]),
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           .rDWBDI                      (rDWBDI[31:0]),
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           .rREGA                       (rREGA[31:0]),
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           .gclk                        (gclk),
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           .grst                        (grst),
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           .gena                        (gena));
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   aeMB_regf
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     regf (/*AUTOINST*/
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           // Outputs
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           .rREGA                       (rREGA[31:0]),
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           .rREGB                       (rREGB[31:0]),
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           .rDWBDI                      (rDWBDI[31:0]),
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           .dwb_dat_o                   (dwb_dat_o[31:0]),
187 53 sybreon
           .fsl_dat_o                   (fsl_dat_o[31:0]),
188 41 sybreon
           // Inputs
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           .rOPC                        (rOPC[5:0]),
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           .rRA                         (rRA[4:0]),
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           .rRB                         (rRB[4:0]),
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           .rRW                         (rRW[4:0]),
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           .rRD                         (rRD[4:0]),
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           .rMXDST                      (rMXDST[1:0]),
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           .rPCLNK                      (rPCLNK[31:2]),
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           .rRESULT                     (rRESULT[31:0]),
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           .rDWBSEL                     (rDWBSEL[3:0]),
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           .rBRA                        (rBRA),
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           .rDLY                        (rDLY),
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           .dwb_dat_i                   (dwb_dat_i[31:0]),
201 53 sybreon
           .fsl_dat_i                   (fsl_dat_i[31:0]),
202 41 sybreon
           .gclk                        (gclk),
203
           .grst                        (grst),
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           .gena                        (gena));
205
 
206 50 sybreon
   aeMB_xecu #(DW, MUL, BSF)
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     xecu (/*AUTOINST*/
208 41 sybreon
           // Outputs
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           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
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           .dwb_sel_o                   (dwb_sel_o[3:0]),
211 66 sybreon
           .fsl_adr_o                   (fsl_adr_o[6:2]),
212
           .fsl_tag_o                   (fsl_tag_o[1:0]),
213 41 sybreon
           .rRESULT                     (rRESULT[31:0]),
214
           .rDWBSEL                     (rDWBSEL[3:0]),
215
           .rMSR_IE                     (rMSR_IE),
216 44 sybreon
           .rMSR_BIP                    (rMSR_BIP),
217 41 sybreon
           // Inputs
218
           .rREGA                       (rREGA[31:0]),
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           .rREGB                       (rREGB[31:0]),
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           .rMXSRC                      (rMXSRC[1:0]),
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           .rMXTGT                      (rMXTGT[1:0]),
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           .rRA                         (rRA[4:0]),
223 53 sybreon
           .rRB                         (rRB[4:0]),
224 41 sybreon
           .rMXALU                      (rMXALU[2:0]),
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           .rBRA                        (rBRA),
226
           .rDLY                        (rDLY),
227 50 sybreon
           .rALT                        (rALT[10:0]),
228 96 sybreon
           .rSTALL                      (rSTALL),
229 41 sybreon
           .rSIMM                       (rSIMM[31:0]),
230
           .rIMM                        (rIMM[15:0]),
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           .rOPC                        (rOPC[5:0]),
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           .rRD                         (rRD[4:0]),
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           .rDWBDI                      (rDWBDI[31:0]),
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           .rPC                         (rPC[31:2]),
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           .gclk                        (gclk),
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           .grst                        (grst),
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           .gena                        (gena));
238 73 sybreon
 
239 41 sybreon
 
240 95 sybreon
endmodule // aeMB_edk32
241 73 sybreon
 
242 95 sybreon
/*
243
 $Log: not supported by cvs2svn $
244 103 sybreon
 Revision 1.13  2007/12/25 22:15:09  sybreon
245
 Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
246
 
247 96 sybreon
 Revision 1.12  2007/12/23 20:40:44  sybreon
248
 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
249
 
250 95 sybreon
 Revision 1.11  2007/11/30 17:08:29  sybreon
251
 Moved simulation kernel into code.
252
 
253
 Revision 1.10  2007/11/16 21:52:03  sybreon
254
 Added fsl_tag_o to FSL bus (tag either address or data).
255 73 sybreon
 
256 95 sybreon
 Revision 1.9  2007/11/14 23:19:24  sybreon
257
 Fixed minor typo.
258 73 sybreon
 
259 95 sybreon
 Revision 1.8  2007/11/14 22:14:34  sybreon
260
 Changed interrupt handling system (reported by M. Ettus).
261 73 sybreon
 
262 95 sybreon
 Revision 1.7  2007/11/10 16:39:38  sybreon
263
 Upgraded license to LGPLv3.
264
 Significant performance optimisations.
265 73 sybreon
 
266 95 sybreon
 Revision 1.6  2007/11/09 20:51:52  sybreon
267
 Added GET/PUT support through a FSL bus.
268 73 sybreon
 
269 95 sybreon
 Revision 1.5  2007/11/08 17:48:14  sybreon
270
 Fixed data WISHBONE arbitration problem (reported by J Lee).
271 73 sybreon
 
272 95 sybreon
 Revision 1.4  2007/11/08 14:17:47  sybreon
273
 Parameterised optional components.
274
 
275
 Revision 1.3  2007/11/03 08:34:55  sybreon
276
 Minor code cleanup.
277
 
278
 Revision 1.2  2007/11/02 19:20:58  sybreon
279
 Added better (beta) interrupt support.
280
 Changed MSR_IE to disabled at reset as per MB docs.
281
 
282
 Revision 1.1  2007/11/02 03:25:40  sybreon
283
 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
284
 Fixed various minor data hazard bugs.
285
 Code compatible with -O0/1/2/3/s generated code.
286
*/

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