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// $Id: aeMB_edk32.v,v 1.7 2007-11-10 16:39:38 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2007/11/09 20:51:52  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.5  2007/11/08 17:48:14  sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.4  2007/11/08 14:17:47  sybreon
// Parameterised optional components.
//
// Revision 1.3  2007/11/03 08:34:55  sybreon
// Minor code cleanup.
//
// Revision 1.2  2007/11/02 19:20:58  sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1  2007/11/02 03:25:40  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_edk32 (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
   dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
   fsl_ack_i, dwb_dat_i, dwb_ack_i
   );
   // Bus widths
   parameter IW = 32; /// Instruction bus address width
   parameter DW = 32; /// Data bus address width
 
   // Optional functions
   parameter MUL = 1; // Multiplier
   parameter BSF = 1; // Barrel Shifter
 
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] dwb_dat_o;              // From regf of aeMB_regf.v
   output [3:0]          dwb_sel_o;              // From xecu of aeMB_xecu.v
   output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
   output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
   output [14:2]        fsl_adr_o;              // From xecu of aeMB_xecu.v
   output [31:0] fsl_dat_o;              // From regf of aeMB_regf.v
   output               fsl_stb_o;              // From ctrl of aeMB_ctrl.v
   output               fsl_wre_o;              // From ctrl of aeMB_ctrl.v
   output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
   output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                dwb_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          dwb_dat_i;              // To regf of aeMB_regf.v
   input                fsl_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          fsl_dat_i;              // To regf of aeMB_regf.v
   input                iwb_ack_i;              // To scon of aeMB_scon.v, ...
   input [31:0]          iwb_dat_i;              // To ibuf of aeMB_ibuf.v, ...
   input                sys_clk_i;              // To scon of aeMB_scon.v
   input                sys_int_i;              // To scon of aeMB_scon.v
   input                sys_rst_i;              // To scon of aeMB_scon.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire                 gclk;                   // From scon of aeMB_scon.v
   wire                 gena;                   // From scon of aeMB_scon.v
   wire                 grst;                   // From scon of aeMB_scon.v
   wire [10:0]           rALT;                   // From ibuf of aeMB_ibuf.v
   wire [1:0]            rATOM;                  // From bpcu of aeMB_bpcu.v
   wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
   wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
   wire [31:0]           rDWBDI;                 // From regf of aeMB_regf.v
   wire [3:0]            rDWBSEL;                // From xecu of aeMB_xecu.v
   wire                 rDWBSTB;                // From ctrl of aeMB_ctrl.v
   wire                 rFSLSTB;                // From ctrl of aeMB_ctrl.v
   wire [15:0]           rIMM;                   // From ibuf of aeMB_ibuf.v
   wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
   wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
   wire [1:0]            rMXALT;                 // From ctrl of aeMB_ctrl.v
   wire [2:0]            rMXALU;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXDST;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXSRC;                 // From ctrl of aeMB_ctrl.v
   wire [1:0]            rMXTGT;                 // From ctrl of aeMB_ctrl.v
   wire [5:0]            rOPC;                   // From ibuf of aeMB_ibuf.v
   wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
   wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
   wire [4:0]            rRA;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRB;                    // From ibuf of aeMB_ibuf.v
   wire [4:0]            rRD;                    // From ibuf of aeMB_ibuf.v
   wire [31:0]           rREGA;                  // From regf of aeMB_regf.v
   wire [31:0]           rREGB;                  // From regf of aeMB_regf.v
   wire [31:0]           rRESULT;                // From xecu of aeMB_xecu.v
   wire [4:0]            rRW;                    // From ctrl of aeMB_ctrl.v
   wire [31:0]           rSIMM;                  // From ibuf of aeMB_ibuf.v
   wire [1:0]            rXCE;                   // From scon of aeMB_scon.v
   // End of automatics
 
   aeMB_scon
     scon (/*AUTOINST*/
           // Outputs
           .rXCE                        (rXCE[1:0]),
           .grst                        (grst),
           .gclk                        (gclk),
           .gena                        (gena),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rATOM                       (rATOM[1:0]),
           .rDWBSTB                     (rDWBSTB),
           .rFSLSTB                     (rFSLSTB),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .fsl_ack_i                   (fsl_ack_i),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .sys_clk_i                   (sys_clk_i),
           .sys_rst_i                   (sys_rst_i),
           .sys_int_i                   (sys_int_i));
 
   aeMB_ibuf
     ibuf (/*AUTOINST*/
           // Outputs
           .rIMM                        (rIMM[15:0]),
           .rRA                         (rRA[4:0]),
           .rRD                         (rRD[4:0]),
           .rRB                         (rRB[4:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rSIMM                       (rSIMM[31:0]),
           .iwb_stb_o                   (iwb_stb_o),
           // Inputs
           .rBRA                        (rBRA),
           .rXCE                        (rXCE[1:0]),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .iwb_ack_i                   (iwb_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_ctrl
     ctrl (/*AUTOINST*/
           // Outputs
           .rMXDST                      (rMXDST[1:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rMXALT                      (rMXALT[1:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rRW                         (rRW[4:0]),
           .rDWBSTB                     (rDWBSTB),
           .rFSLSTB                     (rFSLSTB),
           .dwb_stb_o                   (dwb_stb_o),
           .dwb_wre_o                   (dwb_wre_o),
           .fsl_stb_o                   (fsl_stb_o),
           .fsl_wre_o                   (fsl_wre_o),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rDLY                        (rDLY),
           .rIMM                        (rIMM[15:0]),
           .rALT                        (rALT[10:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rPC                         (rPC[31:2]),
           .rBRA                        (rBRA),
           .rMSR_IE                     (rMSR_IE),
           .dwb_ack_i                   (dwb_ack_i),
           .iwb_ack_i                   (iwb_ack_i),
           .iwb_dat_i                   (iwb_dat_i[31:0]),
           .fsl_ack_i                   (fsl_ack_i),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_bpcu #(IW)
     bpcu (/*AUTOINST*/
           // Outputs
           .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
           .rPC                         (rPC[31:2]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rATOM                       (rATOM[1:0]),
           // Inputs
           .rMXALT                      (rMXALT[1:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rRA                         (rRA[4:0]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rREGA                       (rREGA[31:0]),
           .rXCE                        (rXCE[1:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_regf
     regf (/*AUTOINST*/
           // Outputs
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .dwb_dat_o                   (dwb_dat_o[31:0]),
           .fsl_dat_o                   (fsl_dat_o[31:0]),
           // Inputs
           .rOPC                        (rOPC[5:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rRW                         (rRW[4:0]),
           .rRD                         (rRD[4:0]),
           .rMXDST                      (rMXDST[1:0]),
           .rPCLNK                      (rPCLNK[31:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .dwb_dat_i                   (dwb_dat_i[31:0]),
           .fsl_dat_i                   (fsl_dat_i[31:0]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
   aeMB_xecu #(DW, MUL, BSF)
     xecu (/*AUTOINST*/
           // Outputs
           .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
           .dwb_sel_o                   (dwb_sel_o[3:0]),
           .fsl_adr_o                   (fsl_adr_o[14:2]),
           .rRESULT                     (rRESULT[31:0]),
           .rDWBSEL                     (rDWBSEL[3:0]),
           .rMSR_IE                     (rMSR_IE),
           .rMSR_BIP                    (rMSR_BIP),
           // Inputs
           .rXCE                        (rXCE[1:0]),
           .rREGA                       (rREGA[31:0]),
           .rREGB                       (rREGB[31:0]),
           .rMXSRC                      (rMXSRC[1:0]),
           .rMXTGT                      (rMXTGT[1:0]),
           .rRA                         (rRA[4:0]),
           .rRB                         (rRB[4:0]),
           .rMXALU                      (rMXALU[2:0]),
           .rBRA                        (rBRA),
           .rDLY                        (rDLY),
           .rALT                        (rALT[10:0]),
           .rSIMM                       (rSIMM[31:0]),
           .rIMM                        (rIMM[15:0]),
           .rOPC                        (rOPC[5:0]),
           .rRD                         (rRD[4:0]),
           .rDWBDI                      (rDWBDI[31:0]),
           .rPC                         (rPC[31:2]),
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena));
 
 
endmodule // aeMB_edk32

Line No.	Rev	Author	Line
1	55	sybreon	`// $Id: aeMB_edk32.v,v 1.7 2007-11-10 16:39:38 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	55	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	55	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	55	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	55	sybreon	`// Revision 1.6 2007/11/09 20:51:52 sybreon`
24			`// Added GET/PUT support through a FSL bus.`
25			`//`
26	53	sybreon	`// Revision 1.5 2007/11/08 17:48:14 sybreon`
27			`// Fixed data WISHBONE arbitration problem (reported by J Lee).`
28			`//`
29	51	sybreon	`// Revision 1.4 2007/11/08 14:17:47 sybreon`
30			`// Parameterised optional components.`
31			`//`
32	50	sybreon	`// Revision 1.3 2007/11/03 08:34:55 sybreon`
33			`// Minor code cleanup.`
34			`//`
35	45	sybreon	`// Revision 1.2 2007/11/02 19:20:58 sybreon`
36			`// Added better (beta) interrupt support.`
37			`// Changed MSR_IE to disabled at reset as per MB docs.`
38			`//`
39	44	sybreon	`// Revision 1.1 2007/11/02 03:25:40 sybreon`
40			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
41			`// Fixed various minor data hazard bugs.`
42			`// Code compatible with -O0/1/2/3/s generated code.`
43			`//`
44	41	sybreon
45			`module aeMB_edk32 (/AUTOARG/`
46			`// Outputs`
47	53	sybreon	`iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,`
48			`dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,`
49	41	sybreon	`// Inputs`
50	53	sybreon	`sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,`
51			`fsl_ack_i, dwb_dat_i, dwb_ack_i`
52	41	sybreon	`);`
53	50	sybreon	`// Bus widths`
54			`parameter IW = 32; /// Instruction bus address width`
55			`parameter DW = 32; /// Data bus address width`
56	41	sybreon
57	50	sybreon	`// Optional functions`
58			`parameter MUL = 1; // Multiplier`
59			`parameter BSF = 1; // Barrel Shifter`
60	41	sybreon
61			`/AUTOOUTPUT/`
62			`// Beginning of automatic outputs (from unused autoinst outputs)`
63			`output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v`
64			`output [31:0] dwb_dat_o; // From regf of aeMB_regf.v`
65			`output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v`
66			`output dwb_stb_o; // From ctrl of aeMB_ctrl.v`
67			`output dwb_wre_o; // From ctrl of aeMB_ctrl.v`
68	53	sybreon	`output [14:2] fsl_adr_o; // From xecu of aeMB_xecu.v`
69			`output [31:0] fsl_dat_o; // From regf of aeMB_regf.v`
70			`output fsl_stb_o; // From ctrl of aeMB_ctrl.v`
71			`output fsl_wre_o; // From ctrl of aeMB_ctrl.v`
72	41	sybreon	`output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v`
73			`output iwb_stb_o; // From ibuf of aeMB_ibuf.v`
74			`// End of automatics`
75			`/AUTOINPUT/`
76			`// Beginning of automatic inputs (from unused autoinst inputs)`
77	50	sybreon	`input dwb_ack_i; // To scon of aeMB_scon.v, ...`
78	41	sybreon	`input [31:0] dwb_dat_i; // To regf of aeMB_regf.v`
79	53	sybreon	`input fsl_ack_i; // To scon of aeMB_scon.v, ...`
80			`input [31:0] fsl_dat_i; // To regf of aeMB_regf.v`
81	41	sybreon	`input iwb_ack_i; // To scon of aeMB_scon.v, ...`
82	55	sybreon	`input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v, ...`
83	41	sybreon	`input sys_clk_i; // To scon of aeMB_scon.v`
84	44	sybreon	`input sys_int_i; // To scon of aeMB_scon.v`
85	41	sybreon	`input sys_rst_i; // To scon of aeMB_scon.v`
86			`// End of automatics`
87			`/AUTOWIRE/`
88			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
89			`wire gclk; // From scon of aeMB_scon.v`
90			`wire gena; // From scon of aeMB_scon.v`
91			`wire grst; // From scon of aeMB_scon.v`
92			`wire [10:0] rALT; // From ibuf of aeMB_ibuf.v`
93	44	sybreon	`wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v`
94	41	sybreon	`wire rBRA; // From bpcu of aeMB_bpcu.v`
95			`wire rDLY; // From bpcu of aeMB_bpcu.v`
96			`wire [31:0] rDWBDI; // From regf of aeMB_regf.v`
97			`wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v`
98			`wire rDWBSTB; // From ctrl of aeMB_ctrl.v`
99	53	sybreon	`wire rFSLSTB; // From ctrl of aeMB_ctrl.v`
100	41	sybreon	`wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v`
101	44	sybreon	`wire rMSR_BIP; // From xecu of aeMB_xecu.v`
102	41	sybreon	`wire rMSR_IE; // From xecu of aeMB_xecu.v`
103			`wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v`
104			`wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v`
105			`wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v`
106			`wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v`
107			`wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v`
108			`wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v`
109			`wire [31:2] rPC; // From bpcu of aeMB_bpcu.v`
110			`wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v`
111			`wire [4:0] rRA; // From ibuf of aeMB_ibuf.v`
112			`wire [4:0] rRB; // From ibuf of aeMB_ibuf.v`
113			`wire [4:0] rRD; // From ibuf of aeMB_ibuf.v`
114			`wire [31:0] rREGA; // From regf of aeMB_regf.v`
115			`wire [31:0] rREGB; // From regf of aeMB_regf.v`
116			`wire [31:0] rRESULT; // From xecu of aeMB_xecu.v`
117			`wire [4:0] rRW; // From ctrl of aeMB_ctrl.v`
118			`wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v`
119	44	sybreon	`wire [1:0] rXCE; // From scon of aeMB_scon.v`
120	41	sybreon	`// End of automatics`
121	50	sybreon
122	41	sybreon	`aeMB_scon`
123			`scon (/AUTOINST/`
124			`// Outputs`
125	44	sybreon	`.rXCE (rXCE[1:0]),`
126	41	sybreon	`.grst (grst),`
127			`.gclk (gclk),`
128			`.gena (gena),`
129			`// Inputs`
130			`.rOPC (rOPC[5:0]),`
131	44	sybreon	`.rATOM (rATOM[1:0]),`
132	41	sybreon	`.rDWBSTB (rDWBSTB),`
133	53	sybreon	`.rFSLSTB (rFSLSTB),`
134	41	sybreon	`.dwb_ack_i (dwb_ack_i),`
135			`.iwb_ack_i (iwb_ack_i),`
136	53	sybreon	`.fsl_ack_i (fsl_ack_i),`
137	41	sybreon	`.rMSR_IE (rMSR_IE),`
138	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
139	41	sybreon	`.rBRA (rBRA),`
140			`.rDLY (rDLY),`
141			`.sys_clk_i (sys_clk_i),`
142			`.sys_rst_i (sys_rst_i),`
143			`.sys_int_i (sys_int_i));`
144
145			`aeMB_ibuf`
146			`ibuf (/AUTOINST/`
147			`// Outputs`
148			`.rIMM (rIMM[15:0]),`
149			`.rRA (rRA[4:0]),`
150			`.rRD (rRD[4:0]),`
151			`.rRB (rRB[4:0]),`
152			`.rALT (rALT[10:0]),`
153			`.rOPC (rOPC[5:0]),`
154			`.rSIMM (rSIMM[31:0]),`
155			`.iwb_stb_o (iwb_stb_o),`
156			`// Inputs`
157			`.rBRA (rBRA),`
158			`.rXCE (rXCE[1:0]),`
159			`.iwb_dat_i (iwb_dat_i[31:0]),`
160			`.iwb_ack_i (iwb_ack_i),`
161			`.gclk (gclk),`
162			`.grst (grst),`
163			`.gena (gena));`
164
165			`aeMB_ctrl`
166			`ctrl (/AUTOINST/`
167			`// Outputs`
168			`.rMXDST (rMXDST[1:0]),`
169			`.rMXSRC (rMXSRC[1:0]),`
170			`.rMXTGT (rMXTGT[1:0]),`
171			`.rMXALT (rMXALT[1:0]),`
172			`.rMXALU (rMXALU[2:0]),`
173			`.rRW (rRW[4:0]),`
174			`.rDWBSTB (rDWBSTB),`
175	53	sybreon	`.rFSLSTB (rFSLSTB),`
176	41	sybreon	`.dwb_stb_o (dwb_stb_o),`
177			`.dwb_wre_o (dwb_wre_o),`
178	53	sybreon	`.fsl_stb_o (fsl_stb_o),`
179			`.fsl_wre_o (fsl_wre_o),`
180	41	sybreon	`// Inputs`
181	44	sybreon	`.rXCE (rXCE[1:0]),`
182	41	sybreon	`.rDLY (rDLY),`
183			`.rIMM (rIMM[15:0]),`
184			`.rALT (rALT[10:0]),`
185			`.rOPC (rOPC[5:0]),`
186			`.rRD (rRD[4:0]),`
187			`.rRA (rRA[4:0]),`
188			`.rRB (rRB[4:0]),`
189			`.rPC (rPC[31:2]),`
190			`.rBRA (rBRA),`
191			`.rMSR_IE (rMSR_IE),`
192	50	sybreon	`.dwb_ack_i (dwb_ack_i),`
193	51	sybreon	`.iwb_ack_i (iwb_ack_i),`
194	55	sybreon	`.iwb_dat_i (iwb_dat_i[31:0]),`
195	53	sybreon	`.fsl_ack_i (fsl_ack_i),`
196	41	sybreon	`.gclk (gclk),`
197			`.grst (grst),`
198	44	sybreon	`.gena (gena));`
199	41	sybreon
200			`aeMB_bpcu #(IW)`
201			`bpcu (/AUTOINST/`
202			`// Outputs`
203			`.iwb_adr_o (iwb_adr_o[IW-1:2]),`
204			`.rPC (rPC[31:2]),`
205			`.rPCLNK (rPCLNK[31:2]),`
206			`.rBRA (rBRA),`
207			`.rDLY (rDLY),`
208	44	sybreon	`.rATOM (rATOM[1:0]),`
209	41	sybreon	`// Inputs`
210			`.rMXALT (rMXALT[1:0]),`
211			`.rOPC (rOPC[5:0]),`
212			`.rRD (rRD[4:0]),`
213			`.rRA (rRA[4:0]),`
214			`.rRESULT (rRESULT[31:0]),`
215			`.rDWBDI (rDWBDI[31:0]),`
216			`.rREGA (rREGA[31:0]),`
217			`.rXCE (rXCE[1:0]),`
218			`.gclk (gclk),`
219			`.grst (grst),`
220			`.gena (gena));`
221
222			`aeMB_regf`
223			`regf (/AUTOINST/`
224			`// Outputs`
225			`.rREGA (rREGA[31:0]),`
226			`.rREGB (rREGB[31:0]),`
227			`.rDWBDI (rDWBDI[31:0]),`
228			`.dwb_dat_o (dwb_dat_o[31:0]),`
229	53	sybreon	`.fsl_dat_o (fsl_dat_o[31:0]),`
230	41	sybreon	`// Inputs`
231			`.rOPC (rOPC[5:0]),`
232			`.rRA (rRA[4:0]),`
233			`.rRB (rRB[4:0]),`
234			`.rRW (rRW[4:0]),`
235			`.rRD (rRD[4:0]),`
236			`.rMXDST (rMXDST[1:0]),`
237			`.rPCLNK (rPCLNK[31:2]),`
238			`.rRESULT (rRESULT[31:0]),`
239			`.rDWBSEL (rDWBSEL[3:0]),`
240			`.rBRA (rBRA),`
241			`.rDLY (rDLY),`
242			`.dwb_dat_i (dwb_dat_i[31:0]),`
243	53	sybreon	`.fsl_dat_i (fsl_dat_i[31:0]),`
244	41	sybreon	`.gclk (gclk),`
245			`.grst (grst),`
246			`.gena (gena));`
247
248	50	sybreon	`aeMB_xecu #(DW, MUL, BSF)`
249			`xecu (/AUTOINST/`
250	41	sybreon	`// Outputs`
251			`.dwb_adr_o (dwb_adr_o[DW-1:2]),`
252			`.dwb_sel_o (dwb_sel_o[3:0]),`
253	53	sybreon	`.fsl_adr_o (fsl_adr_o[14:2]),`
254	41	sybreon	`.rRESULT (rRESULT[31:0]),`
255			`.rDWBSEL (rDWBSEL[3:0]),`
256			`.rMSR_IE (rMSR_IE),`
257	44	sybreon	`.rMSR_BIP (rMSR_BIP),`
258	41	sybreon	`// Inputs`
259	44	sybreon	`.rXCE (rXCE[1:0]),`
260	41	sybreon	`.rREGA (rREGA[31:0]),`
261			`.rREGB (rREGB[31:0]),`
262			`.rMXSRC (rMXSRC[1:0]),`
263			`.rMXTGT (rMXTGT[1:0]),`
264			`.rRA (rRA[4:0]),`
265	53	sybreon	`.rRB (rRB[4:0]),`
266	41	sybreon	`.rMXALU (rMXALU[2:0]),`
267			`.rBRA (rBRA),`
268			`.rDLY (rDLY),`
269	50	sybreon	`.rALT (rALT[10:0]),`
270	41	sybreon	`.rSIMM (rSIMM[31:0]),`
271			`.rIMM (rIMM[15:0]),`
272			`.rOPC (rOPC[5:0]),`
273			`.rRD (rRD[4:0]),`
274			`.rDWBDI (rDWBDI[31:0]),`
275			`.rPC (rPC[31:2]),`
276			`.gclk (gclk),`
277			`.grst (grst),`
278			`.gena (gena));`
279
280
281			`endmodule // aeMB_edk32`

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