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/* $Id: edk32.v,v 1.13 2008-05-30 14:02:49 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core TEST
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
`include "random.v"
 
module edk32 ();
 
   // INITIAL SETUP //////////////////////////////////////////////////////
 
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
   reg       svc;
   integer   inttime;
   integer   seed;
   integer   theend;
 
   always #5 sys_clk_i = ~sys_clk_i;
 
   initial begin
      `ifdef VCD_DUMP
      $dumpfile("dump.vcd");
      $dumpvars(1,dut);
      `endif
 
      //seed = `randseed;
      theend = 0;
      svc = 0;
      sys_clk_i = $random(`randseed);
      sys_rst_i = 1;
      sys_int_i = 0;
      sys_exc_i = 0;
      #50 sys_rst_i = 0;
      #40000000 $displayh("\n*** TIMEOUT ",$stime," ***"); $finish;
 
   end
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
   wire        fsl_stb_o;
   wire        fsl_wre_o;
   wire [31:0] fsl_dat_o;
   wire [31:0] fsl_dat_i;
   wire [6:2]  fsl_adr_o;
 
   wire [15:2] iwb_adr_o;
   wire        iwb_stb_o;
   wire        dwb_stb_o;
   reg [31:0]  rom [0:65535];
   wire [31:0] iwb_dat_i;
   reg         iwb_ack_i, dwb_ack_i, fsl_ack_i;
 
   reg [31:0]  ram[0:65535];
   wire [31:0] dwb_dat_i;
   reg [31:0]  dwblat;
   wire        dwb_we_o;
   reg [15:2]  dadr,iadr;
   wire [3:0]  dwb_sel_o;
   wire [31:0] dwb_dat_o;
   wire [15:2] dwb_adr_o;
   wire [31:0] dwb_dat_t;
 
   initial begin
      dwb_ack_i = 0;
      iwb_ack_i = 0;
      fsl_ack_i = 0;
   end
 
   assign      dwb_dat_t = ram[dwb_adr_o];
   assign      iwb_dat_i = ram[iadr];
   assign      dwb_dat_i = ram[dadr];
   assign      fsl_dat_i = fsl_adr_o;
 
`ifdef POSEDGE
 
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
        dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
        fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
     end // else: !if(sys_rst_i)
 
   always @(posedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (posedge sys_clk_i)
 
`else // !`ifdef POSEDGE
 
   always @(negedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o;
        dwb_ack_i <= #1 dwb_stb_o;
        fsl_ack_i <= #1 fsl_stb_o;
     end // else: !if(sys_rst_i)
 
   always @(negedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (negedge sys_clk_i)
 
`endif // !`ifdef POSEDGE
 
 
   integer i;
   initial begin
      for (i=0;i<65535;i=i+1) begin
         ram[i] <= $random;
      end
      #1 $readmemh("dump.vmem",ram);
   end
 
   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
 
   integer rnd;
 
   always @(posedge sys_clk_i) begin
 
      // Interrupt Monitors
      if (!dut.cpu.rMSR_IE) begin
         rnd = $random % 30;
         inttime = $stime + 1000 + (rnd*rnd * 10);
      end
      if ($stime > inttime) begin
         sys_int_i = 1;
         svc = 0;
      end
      if (($stime > inttime + 500) && !svc) begin
         $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
         $finish;
      end
      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
      if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin
         svc = 1;
         //$display("\nLATENCY: ", ($stime - inttime)/10);       
      end
 
      // Pass/Fail Monitors
      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
         $display("\n\tFAIL");
         $finish;
      end
 
      if (iwb_dat_i == 32'hb8000000) begin
         theend = theend + 1;
      end
 
      if (theend == 5) begin
         $display("\n\t*** PASSED ALL TESTS ***");
         $finish;
      end
   end // always @ (posedge sys_clk_i)
 
   // INTERNAL WIRING ////////////////////////////////////////////////////
 
   aeMB_sim #(16,16)
     dut (
          .sys_int_i(sys_int_i),
          .dwb_ack_i(dwb_ack_i),
          .dwb_stb_o(dwb_stb_o),
          .dwb_adr_o(dwb_adr_o),
          .dwb_dat_o(dwb_dat_o),
          .dwb_dat_i(dwb_dat_i),
          .dwb_wre_o(dwb_we_o),
          .dwb_sel_o(dwb_sel_o),
 
          .fsl_ack_i(fsl_ack_i),
          .fsl_stb_o(fsl_stb_o),
          .fsl_adr_o(fsl_adr_o),
          .fsl_dat_o(fsl_dat_o),
          .fsl_dat_i(fsl_dat_i),
          .fsl_wre_o(fsl_we_o),
 
          .iwb_adr_o(iwb_adr_o),
          .iwb_dat_i(iwb_dat_i),
          .iwb_stb_o(iwb_stb_o),
          .iwb_ack_i(iwb_ack_i),
          .sys_clk_i(sys_clk_i),
          .sys_rst_i(sys_rst_i)
          );
 
endmodule // edk32
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.12  2007/12/23 20:40:51  sybreon
 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
 
 Revision 1.11  2007/12/11 00:44:31  sybreon
 Modified for AEMB2
 
 Revision 1.10  2007/11/30 17:08:30  sybreon
 Moved simulation kernel into code.
 
 Revision 1.9  2007/11/20 18:36:00  sybreon
 Removed unnecessary byte acrobatics with VMEM data.
 
 Revision 1.8  2007/11/18 19:41:45  sybreon
 Minor simulation fixes.
 
 Revision 1.7  2007/11/14 22:11:41  sybreon
 Added posedge/negedge bus interface.
 Modified interrupt test system.
 
 Revision 1.6  2007/11/13 23:37:28  sybreon
 Updated simulation to also check BRI 0x00 instruction.
 
 Revision 1.5  2007/11/09 20:51:53  sybreon
 Added GET/PUT support through a FSL bus.
 
 Revision 1.4  2007/11/08 14:18:00  sybreon
 Parameterised optional components.
 
 Revision 1.3  2007/11/05 10:59:31  sybreon
 Added random seed for simulation.
 
 Revision 1.2  2007/11/02 19:16:10  sybreon
 Added interrupt simulation.
 Changed "human readable" simulation output.
 
 Revision 1.1  2007/11/02 03:25:45  sybreon
 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
 Fixed various minor data hazard bugs.
 Code compatible with -O0/1/2/3/s generated code.
 */

Line No.	Rev	Author	Line
1	163	sybreon	`/* $Id: edk32.v,v 1.13 2008-05-30 14:02:49 sybreon Exp $`
2	95	sybreon	`**`
3			`** AEMB EDK 3.2 Compatible Core TEST`
4			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
20			`*/`
21	41	sybreon
22	163	sybreon	`include "random.v"
23
24	41	sybreon	`module edk32 ();`
25	79	sybreon
26	41	sybreon	`// INITIAL SETUP //////////////////////////////////////////////////////`
27
28			`reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;`
29			`reg svc;`
30			`integer inttime;`
31	49	sybreon	`integer seed;`
32	58	sybreon	`integer theend;`
33	41	sybreon
34			`always #5 sys_clk_i = ~sys_clk_i;`
35
36			`initial begin`
37	163	sybreon	`ifdef VCD_DUMP
38			`$dumpfile("dump.vcd");`
39			`$dumpvars(1,dut);`
40			`endif
41
42			//seed = `randseed;
43	58	sybreon	`theend = 0;`
44	41	sybreon	`svc = 0;`
45	163	sybreon	sys_clk_i = $random(`randseed);
46	41	sybreon	`sys_rst_i = 1;`
47			`sys_int_i = 0;`
48			`sys_exc_i = 0;`
49	59	sybreon	`#50 sys_rst_i = 0;`
50	163	sybreon	`#40000000 $displayh("\n* TIMEOUT ",$stime," *"); $finish;`
51
52	41	sybreon	`end`
53
54			`// FAKE MEMORY ////////////////////////////////////////////////////////`
55	53	sybreon
56			`wire fsl_stb_o;`
57			`wire fsl_wre_o;`
58			`wire [31:0] fsl_dat_o;`
59			`wire [31:0] fsl_dat_i;`
60	67	sybreon	`wire [6:2] fsl_adr_o;`
61	41	sybreon
62			`wire [15:2] iwb_adr_o;`
63			`wire iwb_stb_o;`
64			`wire dwb_stb_o;`
65			`reg [31:0] rom [0:65535];`
66			`wire [31:0] iwb_dat_i;`
67	53	sybreon	`reg iwb_ack_i, dwb_ack_i, fsl_ack_i;`
68	41	sybreon
69			`reg [31:0] ram[0:65535];`
70			`wire [31:0] dwb_dat_i;`
71			`reg [31:0] dwblat;`
72			`wire dwb_we_o;`
73			`reg [15:2] dadr,iadr;`
74			`wire [3:0] dwb_sel_o;`
75			`wire [31:0] dwb_dat_o;`
76			`wire [15:2] dwb_adr_o;`
77	59	sybreon	`wire [31:0] dwb_dat_t;`
78
79			`initial begin`
80			`dwb_ack_i = 0;`
81			`iwb_ack_i = 0;`
82			`fsl_ack_i = 0;`
83			`end`
84	41	sybreon
85	69	sybreon	`assign dwb_dat_t = ram[dwb_adr_o];`
86			`assign iwb_dat_i = ram[iadr];`
87			`assign dwb_dat_i = ram[dadr];`
88	53	sybreon	`assign fsl_dat_i = fsl_adr_o;`
89	59	sybreon
90			`ifdef POSEDGE
91	41	sybreon
92	59	sybreon	`always @(posedge sys_clk_i)`
93			`if (sys_rst_i) begin`
94			`/AUTORESET/`
95			`// Beginning of autoreset for uninitialized flops`
96			`dwb_ack_i <= 1'h0;`
97			`fsl_ack_i <= 1'h0;`
98			`iwb_ack_i <= 1'h0;`
99			`// End of automatics`
100			`end else begin`
101			`iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;`
102			`dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;`
103			`fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;`
104	73	sybreon	`end // else: !if(sys_rst_i)`
105	59	sybreon
106			`always @(posedge sys_clk_i) begin`
107			`iadr <= #1 iwb_adr_o;`
108			`dadr <= #1 dwb_adr_o;`
109
110			`if (dwb_we_o & dwb_stb_o) begin`
111			`case (dwb_sel_o)`
112	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
113			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
114			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
115			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
116			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
117			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
118			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
119	59	sybreon	`endcase // case (dwb_sel_o)`
120			`end // if (dwb_we_o & dwb_stb_o)`
121	73	sybreon	`end // always @ (posedge sys_clk_i)`
122	59	sybreon
123			`else // !`ifdef POSEDGE
124
125			`always @(negedge sys_clk_i)`
126			`if (sys_rst_i) begin`
127			`/AUTORESET/`
128			`// Beginning of autoreset for uninitialized flops`
129			`dwb_ack_i <= 1'h0;`
130			`fsl_ack_i <= 1'h0;`
131			`iwb_ack_i <= 1'h0;`
132			`// End of automatics`
133			`end else begin`
134			`iwb_ack_i <= #1 iwb_stb_o;`
135			`dwb_ack_i <= #1 dwb_stb_o;`
136			`fsl_ack_i <= #1 fsl_stb_o;`
137	73	sybreon	`end // else: !if(sys_rst_i)`
138	59	sybreon
139	41	sybreon	`always @(negedge sys_clk_i) begin`
140	59	sybreon	`iadr <= #1 iwb_adr_o;`
141			`dadr <= #1 dwb_adr_o;`
142	53	sybreon
143	41	sybreon	`if (dwb_we_o & dwb_stb_o) begin`
144			`case (dwb_sel_o)`
145	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
146			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
147			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
148			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
149			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
150			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
151			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
152	43	sybreon	`endcase // case (dwb_sel_o)`
153			`end // if (dwb_we_o & dwb_stb_o)`
154			`end // always @ (negedge sys_clk_i)`
155	59	sybreon
156			`endif // !`ifdef POSEDGE
157
158	41	sybreon
159			`integer i;`
160			`initial begin`
161			`for (i=0;i<65535;i=i+1) begin`
162			`ram[i] <= $random;`
163	43	sybreon	`end`
164	79	sybreon	`#1 $readmemh("dump.vmem",ram);`
165	41	sybreon	`end`
166
167			`// DISPLAY OUTPUTS ///////////////////////////////////////////////////`
168
169	58	sybreon	`integer rnd;`
170
171	41	sybreon	`always @(posedge sys_clk_i) begin`
172	43	sybreon
173			`// Interrupt Monitors`
174	95	sybreon	`if (!dut.cpu.rMSR_IE) begin`
175	43	sybreon	`rnd = $random % 30;`
176			`inttime = $stime + 1000 + (rndrnd 10);`
177			`end`
178			`if ($stime > inttime) begin`
179			`sys_int_i = 1;`
180			`svc = 0;`
181			`end`
182			`if (($stime > inttime + 500) && !svc) begin`
183			`$display("\n\t* INTERRUPT TIMEOUT *", inttime);`
184			`$finish;`
185			`end`
186			`if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;`
187	95	sybreon	`if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin`
188	59	sybreon	`svc = 1;`
189			`//$display("\nLATENCY: ", ($stime - inttime)/10);`
190			`end`
191	41	sybreon
192			`// Pass/Fail Monitors`
193			`if (dwb_we_o & (dwb_dat_o == "FAIL")) begin`
194			`$display("\n\tFAIL");`
195			`$finish;`
196	43	sybreon	`end`
197	58	sybreon
198	41	sybreon	`if (iwb_dat_i == 32'hb8000000) begin`
199	58	sybreon	`theend = theend + 1;`
200			`end`
201
202			`if (theend == 5) begin`
203	41	sybreon	`$display("\n\t* PASSED ALL TESTS *");`
204			`$finish;`
205			`end`
206			`end // always @ (posedge sys_clk_i)`
207
208			`// INTERNAL WIRING ////////////////////////////////////////////////////`
209
210	95	sybreon	`aeMB_sim #(16,16)`
211	41	sybreon	`dut (`
212			`.sys_int_i(sys_int_i),`
213			`.dwb_ack_i(dwb_ack_i),`
214			`.dwb_stb_o(dwb_stb_o),`
215			`.dwb_adr_o(dwb_adr_o),`
216			`.dwb_dat_o(dwb_dat_o),`
217			`.dwb_dat_i(dwb_dat_i),`
218			`.dwb_wre_o(dwb_we_o),`
219			`.dwb_sel_o(dwb_sel_o),`
220	53	sybreon
221			`.fsl_ack_i(fsl_ack_i),`
222			`.fsl_stb_o(fsl_stb_o),`
223			`.fsl_adr_o(fsl_adr_o),`
224			`.fsl_dat_o(fsl_dat_o),`
225			`.fsl_dat_i(fsl_dat_i),`
226			`.fsl_wre_o(fsl_we_o),`
227
228	41	sybreon	`.iwb_adr_o(iwb_adr_o),`
229			`.iwb_dat_i(iwb_dat_i),`
230			`.iwb_stb_o(iwb_stb_o),`
231			`.iwb_ack_i(iwb_ack_i),`
232			`.sys_clk_i(sys_clk_i),`
233			`.sys_rst_i(sys_rst_i)`
234			`);`
235
236	43	sybreon	`endmodule // edk32`
237	95	sybreon
238			`/*`
239			$Log: not supported by cvs2svn $
240	163	sybreon	`Revision 1.12 2007/12/23 20:40:51 sybreon`
241			`Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.`
242
243	95	sybreon	`Revision 1.11 2007/12/11 00:44:31 sybreon`
244			`Modified for AEMB2`
245
246			`Revision 1.10 2007/11/30 17:08:30 sybreon`
247			`Moved simulation kernel into code.`
248
249			`Revision 1.9 2007/11/20 18:36:00 sybreon`
250			`Removed unnecessary byte acrobatics with VMEM data.`
251
252			`Revision 1.8 2007/11/18 19:41:45 sybreon`
253			`Minor simulation fixes.`
254
255			`Revision 1.7 2007/11/14 22:11:41 sybreon`
256			`Added posedge/negedge bus interface.`
257			`Modified interrupt test system.`
258
259			`Revision 1.6 2007/11/13 23:37:28 sybreon`
260			`Updated simulation to also check BRI 0x00 instruction.`
261
262			`Revision 1.5 2007/11/09 20:51:53 sybreon`
263			`Added GET/PUT support through a FSL bus.`
264
265			`Revision 1.4 2007/11/08 14:18:00 sybreon`
266			`Parameterised optional components.`
267
268			`Revision 1.3 2007/11/05 10:59:31 sybreon`
269			`Added random seed for simulation.`
270
271			`Revision 1.2 2007/11/02 19:16:10 sybreon`
272			`Added interrupt simulation.`
273			`Changed "human readable" simulation output.`
274
275			`Revision 1.1 2007/11/02 03:25:45 sybreon`
276			`New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
277			`Fixed various minor data hazard bugs.`
278			`Code compatible with -O0/1/2/3/s generated code.`
279			`*/`

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