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// $Id: edk32.v,v 1.9 2007-11-20 18:36:00 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core TEST
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2007/11/18 19:41:45  sybreon
// Minor simulation fixes.
//
// Revision 1.7  2007/11/14 22:11:41  sybreon
// Added posedge/negedge bus interface.
// Modified interrupt test system.
//
// Revision 1.6  2007/11/13 23:37:28  sybreon
// Updated simulation to also check BRI 0x00 instruction.
//
// Revision 1.5  2007/11/09 20:51:53  sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.4  2007/11/08 14:18:00  sybreon
// Parameterised optional components.
//
// Revision 1.3  2007/11/05 10:59:31  sybreon
// Added random seed for simulation.
//
// Revision 1.2  2007/11/02 19:16:10  sybreon
// Added interrupt simulation.
// Changed "human readable" simulation output.
//
// Revision 1.1  2007/11/02 03:25:45  sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module edk32 ();
 
`include "random.v"
 
   // INITIAL SETUP //////////////////////////////////////////////////////
 
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
   reg       svc;
   integer   inttime;
   integer   seed;
   integer   theend;
 
   always #5 sys_clk_i = ~sys_clk_i;
 
   initial begin
      //$dumpfile("dump.vcd");
      //$dumpvars(1,dut);
   end
 
   initial begin
      seed = randseed;
      theend = 0;
      svc = 0;
      sys_clk_i = $random(seed);
      sys_rst_i = 1;
      sys_int_i = 0;
      sys_exc_i = 0;
      #50 sys_rst_i = 0;
   end
 
   initial fork
      //inttime $display("FSADFASDFSDAF");      
      //#10000 sys_int_i = 1;
      //#1100 sys_int_i = 0;
      //#100000 $displayh("\nTest Completed."); 
      //#4000 $finish;
   join
 
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
   wire        fsl_stb_o;
   wire        fsl_wre_o;
   wire [31:0] fsl_dat_o;
   wire [31:0] fsl_dat_i;
   wire [6:2]  fsl_adr_o;
 
   wire [15:2] iwb_adr_o;
   wire        iwb_stb_o;
   wire        dwb_stb_o;
   reg [31:0]  rom [0:65535];
   wire [31:0] iwb_dat_i;
   reg         iwb_ack_i, dwb_ack_i, fsl_ack_i;
 
   reg [31:0]  ram[0:65535];
   wire [31:0] dwb_dat_i;
   reg [31:0]  dwblat;
   wire        dwb_we_o;
   reg [15:2]  dadr,iadr;
   wire [3:0]  dwb_sel_o;
   wire [31:0] dwb_dat_o;
   wire [15:2] dwb_adr_o;
   wire [31:0] dwb_dat_t;
 
   initial begin
      dwb_ack_i = 0;
      iwb_ack_i = 0;
      fsl_ack_i = 0;
   end
 
   assign      dwb_dat_t = ram[dwb_adr_o];
   assign      iwb_dat_i = ram[iadr];
   assign      dwb_dat_i = ram[dadr];
   assign      fsl_dat_i = fsl_adr_o;
 
//`define POSEDGE
`ifdef POSEDGE
 
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
        dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
        fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
     end
 
   always @(posedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (negedge sys_clk_i)
 
`else // !`ifdef POSEDGE
 
   always @(negedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o;
        dwb_ack_i <= #1 dwb_stb_o;
        fsl_ack_i <= #1 fsl_stb_o;
     end
 
   always @(negedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (negedge sys_clk_i)
 
`endif // !`ifdef POSEDGE
 
 
   integer i;
   initial begin
      for (i=0;i<65535;i=i+1) begin
         ram[i] <= $random;
      end
      #1 $readmemh("dump.rom",ram);
   end
 
   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
 
   //assign dut.rRESULT = dut.rSIMM;   
 
   integer rnd;
 
   always @(posedge sys_clk_i) begin
 
      // Interrupt Monitors
      if (!dut.rMSR_IE) begin
         rnd = $random % 30;
         inttime = $stime + 1000 + (rnd*rnd * 10);
      end
      if ($stime > inttime) begin
         sys_int_i = 1;
         svc = 0;
      end
      if (($stime > inttime + 500) && !svc) begin
         $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
         $finish;
      end
      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
      if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
         svc = 1;
         //$display("\nLATENCY: ", ($stime - inttime)/10);       
      end
 
      // Pass/Fail Monitors
      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
         $display("\n\tFAIL");
         $finish;
      end
 
      if (iwb_dat_i == 32'hb8000000) begin
         theend = theend + 1;
      end
 
      if (theend == 5) begin
         $display("\n\t*** PASSED ALL TESTS ***");
         $finish;
      end
   end // always @ (posedge sys_clk_i)
 
 
   always @(posedge sys_clk_i) if (dut.gena) begin
      $write ("\n", ($stime/10));
      $writeh ("\tPC=", {iwb_adr_o,2'd0});
 
      // DECODE
      $writeh ("\t");
 
      case ({dut.rBRA, dut.rDLY})
        2'b00: $write(" ");
        2'b01: $write(".");
        2'b10: $write("-");
        2'b11: $write("+");
      endcase // case ({dut.rBRA, dut.rDLY})
 
      case (dut.rOPC)
        6'o00: if (dut.rRD == 0) $write("   "); else $write("ADD");
        6'o01: $write("RSUB");
        6'o02: $write("ADDC");
        6'o03: $write("RSUBC");
        6'o04: $write("ADDK");
        6'o05: case (dut.rIMM[1:0])
                 2'o0: $write("RSUBK");
                 2'o1: $write("CMP");
                 2'o3: $write("CMPU");
                 default: $write("XXX");
               endcase // case (dut.rIMM[1:0])
        6'o06: $write("ADDKC");
        6'o07: $write("RSUBKC");
 
        6'o10: $write("ADDI");
        6'o11: $write("RSUBI");
        6'o12: $write("ADDIC");
        6'o13: $write("RSUBIC");
        6'o14: $write("ADDIK");
        6'o15: $write("RSUBIK");
        6'o16: $write("ADDIKC");
        6'o17: $write("RSUBIKC");
 
        6'o20: $write("MUL");
        6'o21: case (dut.rALT[10:9])
                 2'o0: $write("BSRL");
                 2'o1: $write("BSRA");
                 2'o2: $write("BSLL");
                 default: $write("XXX");
               endcase // case (dut.rALT[10:9])
        6'o22: $write("IDIV");
 
        6'o30: $write("MULI");
        6'o31: case (dut.rALT[10:9])
                 2'o0: $write("BSRLI");
                 2'o1: $write("BSRAI");
                 2'o2: $write("BSLLI");
                 default: $write("XXX");
               endcase // case (dut.rALT[10:9])
        6'o33: case (dut.rRB[4:2])
                 3'o0: $write("GET");
                 3'o4: $write("PUT");
                 3'o2: $write("NGET");
                 3'o6: $write("NPUT");
                 3'o1: $write("CGET");
                 3'o5: $write("CPUT");
                 3'o3: $write("NCGET");
                 3'o7: $write("NCPUT");
               endcase // case (dut.rRB[4:2])
 
 
        6'o40: $write("OR");
        6'o41: $write("AND");
        6'o42: if (dut.rRD == 0) $write("   "); else $write("XOR");
        6'o43: $write("ANDN");
        6'o44: case (dut.rIMM[6:5])
                 2'o0: $write("SRA");
                 2'o1: $write("SRC");
                 2'o2: $write("SRL");
                 2'o3: if (dut.rIMM[0]) $write("SEXT16"); else $write("SEXT8");
               endcase // case (dut.rIMM[6:5])
 
        6'o45: $write("MOV");
        6'o46: case (dut.rRA[3:2])
                 3'o0: $write("BR");
                 3'o1: $write("BRL");
                 3'o2: $write("BRA");
                 3'o3: $write("BRAL");
               endcase // case (dut.rRA[3:2])
 
        6'o47: case (dut.rRD[2:0])
                 3'o0: $write("BEQ");
                 3'o1: $write("BNE");
                 3'o2: $write("BLT");
                 3'o3: $write("BLE");
                 3'o4: $write("BGT");
                 3'o5: $write("BGE");
                 default: $write("XXX");
               endcase // case (dut.rRD[2:0])
 
        6'o50: $write("ORI");
        6'o51: $write("ANDI");
        6'o52: $write("XORI");
        6'o53: $write("ANDNI");
        6'o54: $write("IMMI");
        6'o55: case (dut.rRD[1:0])
                 2'o0: $write("RTSD");
                 2'o1: $write("RTID");
                 2'o2: $write("RTBD");
                 default: $write("XXX");
               endcase
        6'o56: case (dut.rRA[3:2])
                 3'o0: $write("BRI");
                 3'o1: $write("BRLI");
                 3'o2: $write("BRAI");
                 3'o3: $write("BRALI");
               endcase // case (dut.rRA[3:2])
        6'o57: case (dut.rRD[2:0])
                 3'o0: $write("BEQI");
                 3'o1: $write("BNEI");
                 3'o2: $write("BLTI");
                 3'o3: $write("BLEI");
                 3'o4: $write("BGTI");
                 3'o5: $write("BGEI");
                 default: $write("XXX");
               endcase // case (dut.rRD[2:0])
 
        6'o60: $write("LBU");
        6'o61: $write("LHU");
        6'o62: $write("LW");
        6'o64: $write("SB");
        6'o65: $write("SH");
        6'o66: $write("SW");
 
        6'o70: $write("LBUI");
        6'o71: $write("LHUI");
        6'o72: $write("LWI");
        6'o74: $write("SBI");
        6'o75: $write("SHI");
        6'o76: $write("SWI");
 
        default: $write("XXX");
      endcase // case (dut.rOPC)
 
      case (dut.rOPC[3])
        1'b1: $writeh("\tr",dut.rRD,", r",dut.rRA,", h",dut.rIMM);
        1'b0: $writeh("\tr",dut.rRD,", r",dut.rRA,", r",dut.rRB,"  ");
      endcase // case (dut.rOPC[3])
 
 
      // ALU
      $write("\t");
      //$writeh(" I=",dut.rSIMM);
      $writeh(" A=",dut.xecu.rOPA);
      $writeh(" B=",dut.xecu.rOPB);
 
      case (dut.rMXALU)
        3'o0: $write(" ADD");
        3'o1: $write(" LOG");
        3'o2: $write(" SFT");
        3'o3: $write(" MOV");
        3'o4: $write(" MUL");
        3'o5: $write(" BSF");
        default: $write(" XXX");
      endcase // case (dut.rMXALU)
      $writeh("=h",dut.xecu.xRESULT);
 
      // WRITEBACK
      $writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");
 
      if (dut.regf.fRDWE) begin
         case (dut.rMXDST)
           2'o2: begin
              if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
              if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
           end
           2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
           2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
         endcase // case (dut.rMXDST)
      end
 
      // STORE
      if (dwb_stb_o & dwb_we_o) $writeh("RAM(",{dwb_adr_o,2'd0},")=",dwb_dat_o,":",dwb_sel_o);
 
   end // if (dut.gena)
 
 
   // INTERNAL WIRING ////////////////////////////////////////////////////
 
   aeMB_edk32 #(16,16)
     dut (
          .sys_int_i(sys_int_i),
          .dwb_ack_i(dwb_ack_i),
          .dwb_stb_o(dwb_stb_o),
          .dwb_adr_o(dwb_adr_o),
          .dwb_dat_o(dwb_dat_o),
          .dwb_dat_i(dwb_dat_i),
          .dwb_wre_o(dwb_we_o),
          .dwb_sel_o(dwb_sel_o),
 
          .fsl_ack_i(fsl_ack_i),
          .fsl_stb_o(fsl_stb_o),
          .fsl_adr_o(fsl_adr_o),
          .fsl_dat_o(fsl_dat_o),
          .fsl_dat_i(fsl_dat_i),
          .fsl_wre_o(fsl_we_o),
 
          .iwb_adr_o(iwb_adr_o),
          .iwb_dat_i(iwb_dat_i),
          .iwb_stb_o(iwb_stb_o),
          .iwb_ack_i(iwb_ack_i),
          .sys_clk_i(sys_clk_i),
          .sys_rst_i(sys_rst_i)
          );
 
 
 
 
 
endmodule // edk32

Line No.	Rev	Author	Line
1	69	sybreon	`// $Id: edk32.v,v 1.9 2007-11-20 18:36:00 sybreon Exp $`
2	41	sybreon	`//`
3			`// AEMB EDK 3.2 Compatible Core TEST`
4			`//`
5			`// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
6			`//`
7	59	sybreon	`// This file is part of AEMB.`
8	41	sybreon	`//`
9	59	sybreon	`// AEMB is free software: you can redistribute it and/or modify it`
10			`// under the terms of the GNU Lesser General Public License as`
11			`// published by the Free Software Foundation, either version 3 of the`
12			`// License, or (at your option) any later version.`
13			`//`
14			`// AEMB is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`// Public License for more details.`
18			`//`
19	41	sybreon	`// You should have received a copy of the GNU Lesser General Public`
20	59	sybreon	`// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
21	41	sybreon	`//`
22			`// $Log: not supported by cvs2svn $`
23	69	sybreon	`// Revision 1.8 2007/11/18 19:41:45 sybreon`
24			`// Minor simulation fixes.`
25			`//`
26	67	sybreon	`// Revision 1.7 2007/11/14 22:11:41 sybreon`
27			`// Added posedge/negedge bus interface.`
28			`// Modified interrupt test system.`
29			`//`
30	59	sybreon	`// Revision 1.6 2007/11/13 23:37:28 sybreon`
31			`// Updated simulation to also check BRI 0x00 instruction.`
32			`//`
33	58	sybreon	`// Revision 1.5 2007/11/09 20:51:53 sybreon`
34			`// Added GET/PUT support through a FSL bus.`
35			`//`
36	53	sybreon	`// Revision 1.4 2007/11/08 14:18:00 sybreon`
37			`// Parameterised optional components.`
38			`//`
39	50	sybreon	`// Revision 1.3 2007/11/05 10:59:31 sybreon`
40			`// Added random seed for simulation.`
41			`//`
42	49	sybreon	`// Revision 1.2 2007/11/02 19:16:10 sybreon`
43			`// Added interrupt simulation.`
44			`// Changed "human readable" simulation output.`
45			`//`
46	43	sybreon	`// Revision 1.1 2007/11/02 03:25:45 sybreon`
47			`// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
48			`// Fixed various minor data hazard bugs.`
49			`// Code compatible with -O0/1/2/3/s generated code.`
50			`//`
51	41	sybreon
52			`module edk32 ();`
53	49	sybreon
54			`include "random.v"
55
56	41	sybreon	`// INITIAL SETUP //////////////////////////////////////////////////////`
57
58			`reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;`
59			`reg svc;`
60			`integer inttime;`
61	49	sybreon	`integer seed;`
62	58	sybreon	`integer theend;`
63	41	sybreon
64			`always #5 sys_clk_i = ~sys_clk_i;`
65
66			`initial begin`
67	69	sybreon	`//$dumpfile("dump.vcd");`
68			`//$dumpvars(1,dut);`
69	41	sybreon	`end`
70
71			`initial begin`
72	58	sybreon	`seed = randseed;`
73			`theend = 0;`
74	41	sybreon	`svc = 0;`
75	49	sybreon	`sys_clk_i = $random(seed);`
76	41	sybreon	`sys_rst_i = 1;`
77			`sys_int_i = 0;`
78			`sys_exc_i = 0;`
79	59	sybreon	`#50 sys_rst_i = 0;`
80	41	sybreon	`end`
81
82			`initial fork`
83			`//inttime $display("FSADFASDFSDAF");`
84	43	sybreon	`//#10000 sys_int_i = 1;`
85	41	sybreon	`//#1100 sys_int_i = 0;`
86			`//#100000 $displayh("\nTest Completed.");`
87			`//#4000 $finish;`
88			`join`
89
90
91			`// FAKE MEMORY ////////////////////////////////////////////////////////`
92	53	sybreon
93			`wire fsl_stb_o;`
94			`wire fsl_wre_o;`
95			`wire [31:0] fsl_dat_o;`
96			`wire [31:0] fsl_dat_i;`
97	67	sybreon	`wire [6:2] fsl_adr_o;`
98	41	sybreon
99			`wire [15:2] iwb_adr_o;`
100			`wire iwb_stb_o;`
101			`wire dwb_stb_o;`
102			`reg [31:0] rom [0:65535];`
103			`wire [31:0] iwb_dat_i;`
104	53	sybreon	`reg iwb_ack_i, dwb_ack_i, fsl_ack_i;`
105	41	sybreon
106			`reg [31:0] ram[0:65535];`
107			`wire [31:0] dwb_dat_i;`
108			`reg [31:0] dwblat;`
109			`wire dwb_we_o;`
110			`reg [15:2] dadr,iadr;`
111			`wire [3:0] dwb_sel_o;`
112			`wire [31:0] dwb_dat_o;`
113			`wire [15:2] dwb_adr_o;`
114	59	sybreon	`wire [31:0] dwb_dat_t;`
115
116			`initial begin`
117			`dwb_ack_i = 0;`
118			`iwb_ack_i = 0;`
119			`fsl_ack_i = 0;`
120			`end`
121	41	sybreon
122	69	sybreon	`assign dwb_dat_t = ram[dwb_adr_o];`
123			`assign iwb_dat_i = ram[iadr];`
124			`assign dwb_dat_i = ram[dadr];`
125	53	sybreon	`assign fsl_dat_i = fsl_adr_o;`
126	59	sybreon
127			//`define POSEDGE
128			`ifdef POSEDGE
129	41	sybreon
130	59	sybreon	`always @(posedge sys_clk_i)`
131			`if (sys_rst_i) begin`
132			`/AUTORESET/`
133			`// Beginning of autoreset for uninitialized flops`
134			`dwb_ack_i <= 1'h0;`
135			`fsl_ack_i <= 1'h0;`
136			`iwb_ack_i <= 1'h0;`
137			`// End of automatics`
138			`end else begin`
139			`iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;`
140			`dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;`
141			`fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;`
142			`end`
143
144			`always @(posedge sys_clk_i) begin`
145			`iadr <= #1 iwb_adr_o;`
146			`dadr <= #1 dwb_adr_o;`
147
148			`if (dwb_we_o & dwb_stb_o) begin`
149			`case (dwb_sel_o)`
150	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
151			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
152			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
153			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
154			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
155			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
156			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
157	59	sybreon	`endcase // case (dwb_sel_o)`
158			`end // if (dwb_we_o & dwb_stb_o)`
159			`end // always @ (negedge sys_clk_i)`
160
161			`else // !`ifdef POSEDGE
162
163			`always @(negedge sys_clk_i)`
164			`if (sys_rst_i) begin`
165			`/AUTORESET/`
166			`// Beginning of autoreset for uninitialized flops`
167			`dwb_ack_i <= 1'h0;`
168			`fsl_ack_i <= 1'h0;`
169			`iwb_ack_i <= 1'h0;`
170			`// End of automatics`
171			`end else begin`
172			`iwb_ack_i <= #1 iwb_stb_o;`
173			`dwb_ack_i <= #1 dwb_stb_o;`
174			`fsl_ack_i <= #1 fsl_stb_o;`
175			`end`
176
177	41	sybreon	`always @(negedge sys_clk_i) begin`
178	59	sybreon	`iadr <= #1 iwb_adr_o;`
179			`dadr <= #1 dwb_adr_o;`
180	53	sybreon
181	41	sybreon	`if (dwb_we_o & dwb_stb_o) begin`
182			`case (dwb_sel_o)`
183	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
184			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
185			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
186			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
187			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
188			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
189			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
190	43	sybreon	`endcase // case (dwb_sel_o)`
191			`end // if (dwb_we_o & dwb_stb_o)`
192			`end // always @ (negedge sys_clk_i)`
193	59	sybreon
194			`endif // !`ifdef POSEDGE
195
196	41	sybreon
197			`integer i;`
198			`initial begin`
199			`for (i=0;i<65535;i=i+1) begin`
200			`ram[i] <= $random;`
201	43	sybreon	`end`
202	69	sybreon	`#1 $readmemh("dump.rom",ram);`
203	41	sybreon	`end`
204
205			`// DISPLAY OUTPUTS ///////////////////////////////////////////////////`
206
207			`//assign dut.rRESULT = dut.rSIMM;`
208	43	sybreon
209	58	sybreon	`integer rnd;`
210
211	41	sybreon	`always @(posedge sys_clk_i) begin`
212	43	sybreon
213			`// Interrupt Monitors`
214			`if (!dut.rMSR_IE) begin`
215			`rnd = $random % 30;`
216			`inttime = $stime + 1000 + (rndrnd 10);`
217			`end`
218			`if ($stime > inttime) begin`
219			`sys_int_i = 1;`
220			`svc = 0;`
221			`end`
222			`if (($stime > inttime + 500) && !svc) begin`
223			`$display("\n\t* INTERRUPT TIMEOUT *", inttime);`
224			`$finish;`
225			`end`
226			`if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;`
227	59	sybreon	`if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin`
228			`svc = 1;`
229			`//$display("\nLATENCY: ", ($stime - inttime)/10);`
230			`end`
231	41	sybreon
232			`// Pass/Fail Monitors`
233			`if (dwb_we_o & (dwb_dat_o == "FAIL")) begin`
234			`$display("\n\tFAIL");`
235			`$finish;`
236	43	sybreon	`end`
237	58	sybreon
238	41	sybreon	`if (iwb_dat_i == 32'hb8000000) begin`
239	58	sybreon	`theend = theend + 1;`
240			`end`
241
242			`if (theend == 5) begin`
243	41	sybreon	`$display("\n\t* PASSED ALL TESTS *");`
244			`$finish;`
245			`end`
246			`end // always @ (posedge sys_clk_i)`
247
248
249			`always @(posedge sys_clk_i) if (dut.gena) begin`
250			`$write ("\n", ($stime/10));`
251	43	sybreon	`$writeh ("\tPC=", {iwb_adr_o,2'd0});`
252	41	sybreon
253			`// DECODE`
254			`$writeh ("\t");`
255
256			`case ({dut.rBRA, dut.rDLY})`
257			`2'b00: $write(" ");`
258			`2'b01: $write(".");`
259			`2'b10: $write("-");`
260			`2'b11: $write("+");`
261			`endcase // case ({dut.rBRA, dut.rDLY})`
262
263			`case (dut.rOPC)`
264			`6'o00: if (dut.rRD == 0) $write(" "); else $write("ADD");`
265			`6'o01: $write("RSUB");`
266			`6'o02: $write("ADDC");`
267			`6'o03: $write("RSUBC");`
268			`6'o04: $write("ADDK");`
269			`6'o05: case (dut.rIMM[1:0])`
270			`2'o0: $write("RSUBK");`
271			`2'o1: $write("CMP");`
272			`2'o3: $write("CMPU");`
273			`default: $write("XXX");`
274	43	sybreon	`endcase // case (dut.rIMM[1:0])`
275	41	sybreon	`6'o06: $write("ADDKC");`
276			`6'o07: $write("RSUBKC");`
277
278			`6'o10: $write("ADDI");`
279			`6'o11: $write("RSUBI");`
280			`6'o12: $write("ADDIC");`
281			`6'o13: $write("RSUBIC");`
282			`6'o14: $write("ADDIK");`
283			`6'o15: $write("RSUBIK");`
284			`6'o16: $write("ADDIKC");`
285			`6'o17: $write("RSUBIKC");`
286
287			`6'o20: $write("MUL");`
288			`6'o21: case (dut.rALT[10:9])`
289			`2'o0: $write("BSRL");`
290			`2'o1: $write("BSRA");`
291			`2'o2: $write("BSLL");`
292			`default: $write("XXX");`
293	43	sybreon	`endcase // case (dut.rALT[10:9])`
294	41	sybreon	`6'o22: $write("IDIV");`
295
296			`6'o30: $write("MULI");`
297			`6'o31: case (dut.rALT[10:9])`
298			`2'o0: $write("BSRLI");`
299			`2'o1: $write("BSRAI");`
300			`2'o2: $write("BSLLI");`
301			`default: $write("XXX");`
302	43	sybreon	`endcase // case (dut.rALT[10:9])`
303	53	sybreon	`6'o33: case (dut.rRB[4:2])`
304			`3'o0: $write("GET");`
305			`3'o4: $write("PUT");`
306			`3'o2: $write("NGET");`
307			`3'o6: $write("NPUT");`
308			`3'o1: $write("CGET");`
309			`3'o5: $write("CPUT");`
310			`3'o3: $write("NCGET");`
311			`3'o7: $write("NCPUT");`
312			`endcase // case (dut.rRB[4:2])`
313
314	41	sybreon
315			`6'o40: $write("OR");`
316			`6'o41: $write("AND");`
317			`6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");`
318			`6'o43: $write("ANDN");`
319	43	sybreon	`6'o44: case (dut.rIMM[6:5])`
320			`2'o0: $write("SRA");`
321			`2'o1: $write("SRC");`
322			`2'o2: $write("SRL");`
323			`2'o3: if (dut.rIMM[0]) $write("SEXT16"); else $write("SEXT8");`
324			`endcase // case (dut.rIMM[6:5])`
325
326	41	sybreon	`6'o45: $write("MOV");`
327	43	sybreon	`6'o46: case (dut.rRA[3:2])`
328			`3'o0: $write("BR");`
329			`3'o1: $write("BRL");`
330			`3'o2: $write("BRA");`
331			`3'o3: $write("BRAL");`
332			`endcase // case (dut.rRA[3:2])`
333
334	41	sybreon	`6'o47: case (dut.rRD[2:0])`
335			`3'o0: $write("BEQ");`
336			`3'o1: $write("BNE");`
337			`3'o2: $write("BLT");`
338			`3'o3: $write("BLE");`
339			`3'o4: $write("BGT");`
340			`3'o5: $write("BGE");`
341			`default: $write("XXX");`
342			`endcase // case (dut.rRD[2:0])`
343
344			`6'o50: $write("ORI");`
345			`6'o51: $write("ANDI");`
346			`6'o52: $write("XORI");`
347			`6'o53: $write("ANDNI");`
348			`6'o54: $write("IMMI");`
349	43	sybreon	`6'o55: case (dut.rRD[1:0])`
350			`2'o0: $write("RTSD");`
351			`2'o1: $write("RTID");`
352			`2'o2: $write("RTBD");`
353			`default: $write("XXX");`
354			`endcase`
355			`6'o56: case (dut.rRA[3:2])`
356			`3'o0: $write("BRI");`
357			`3'o1: $write("BRLI");`
358			`3'o2: $write("BRAI");`
359			`3'o3: $write("BRALI");`
360			`endcase // case (dut.rRA[3:2])`
361	41	sybreon	`6'o57: case (dut.rRD[2:0])`
362			`3'o0: $write("BEQI");`
363			`3'o1: $write("BNEI");`
364			`3'o2: $write("BLTI");`
365			`3'o3: $write("BLEI");`
366			`3'o4: $write("BGTI");`
367			`3'o5: $write("BGEI");`
368			`default: $write("XXX");`
369			`endcase // case (dut.rRD[2:0])`
370
371			`6'o60: $write("LBU");`
372			`6'o61: $write("LHU");`
373			`6'o62: $write("LW");`
374			`6'o64: $write("SB");`
375			`6'o65: $write("SH");`
376			`6'o66: $write("SW");`
377
378			`6'o70: $write("LBUI");`
379			`6'o71: $write("LHUI");`
380			`6'o72: $write("LWI");`
381			`6'o74: $write("SBI");`
382			`6'o75: $write("SHI");`
383			`6'o76: $write("SWI");`
384
385			`default: $write("XXX");`
386	43	sybreon	`endcase // case (dut.rOPC)`
387	41	sybreon
388			`case (dut.rOPC[3])`
389			`1'b1: $writeh("\tr",dut.rRD,", r",dut.rRA,", h",dut.rIMM);`
390			`1'b0: $writeh("\tr",dut.rRD,", r",dut.rRA,", r",dut.rRB," ");`
391	43	sybreon	`endcase // case (dut.rOPC[3])`
392	41	sybreon
393
394			`// ALU`
395			`$write("\t");`
396	43	sybreon	`//$writeh(" I=",dut.rSIMM);`
397	50	sybreon	`$writeh(" A=",dut.xecu.rOPA);`
398			`$writeh(" B=",dut.xecu.rOPB);`
399	41	sybreon
400			`case (dut.rMXALU)`
401			`3'o0: $write(" ADD");`
402			`3'o1: $write(" LOG");`
403			`3'o2: $write(" SFT");`
404			`3'o3: $write(" MOV");`
405			`3'o4: $write(" MUL");`
406			`3'o5: $write(" BSF");`
407			`default: $write(" XXX");`
408	43	sybreon	`endcase // case (dut.rMXALU)`
409	41	sybreon	`$writeh("=h",dut.xecu.xRESULT);`
410
411			`// WRITEBACK`
412	43	sybreon	`$writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");`
413	41	sybreon
414			`if (dut.regf.fRDWE) begin`
415			`case (dut.rMXDST)`
416	53	sybreon	`2'o2: begin`
417			`if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");`
418			`if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");`
419			`end`
420	41	sybreon	`2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");`
421			`2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");`
422	43	sybreon	`endcase // case (dut.rMXDST)`
423	41	sybreon	`end`
424
425			`// STORE`
426			`if (dwb_stb_o & dwb_we_o) $writeh("RAM(",{dwb_adr_o,2'd0},")=",dwb_dat_o,":",dwb_sel_o);`
427
428	43	sybreon	`end // if (dut.gena)`
429	41	sybreon
430
431			`// INTERNAL WIRING ////////////////////////////////////////////////////`
432
433			`aeMB_edk32 #(16,16)`
434			`dut (`
435			`.sys_int_i(sys_int_i),`
436			`.dwb_ack_i(dwb_ack_i),`
437			`.dwb_stb_o(dwb_stb_o),`
438			`.dwb_adr_o(dwb_adr_o),`
439			`.dwb_dat_o(dwb_dat_o),`
440			`.dwb_dat_i(dwb_dat_i),`
441			`.dwb_wre_o(dwb_we_o),`
442			`.dwb_sel_o(dwb_sel_o),`
443	53	sybreon
444			`.fsl_ack_i(fsl_ack_i),`
445			`.fsl_stb_o(fsl_stb_o),`
446			`.fsl_adr_o(fsl_adr_o),`
447			`.fsl_dat_o(fsl_dat_o),`
448			`.fsl_dat_i(fsl_dat_i),`
449			`.fsl_wre_o(fsl_we_o),`
450
451	41	sybreon	`.iwb_adr_o(iwb_adr_o),`
452			`.iwb_dat_i(iwb_dat_i),`
453			`.iwb_stb_o(iwb_stb_o),`
454			`.iwb_ack_i(iwb_ack_i),`
455			`.sys_clk_i(sys_clk_i),`
456			`.sys_rst_i(sys_rst_i)`
457			`);`
458
459
460
461
462
463	43	sybreon	`endmodule // edk32`

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