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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk32.v] - Blame information for rev 73

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1 73 sybreon 
// $Id: edk32.v,v 1.10 2007-11-30 17:08:30 sybreon Exp $
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//
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// AEMB EDK 3.2 Compatible Core TEST
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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// This file is part of AEMB.
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//
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// AEMB is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as
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// published by the Free Software Foundation, either version 3 of the
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// License, or (at your option) any later version.
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//
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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// Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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// $Log: not supported by cvs2svn $
23 73 sybreon 
// Revision 1.9  2007/11/20 18:36:00  sybreon
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// Removed unnecessary byte acrobatics with VMEM data.
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//
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// Revision 1.8  2007/11/18 19:41:45  sybreon
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// Minor simulation fixes.
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//
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// Revision 1.7  2007/11/14 22:11:41  sybreon
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// Added posedge/negedge bus interface.
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// Modified interrupt test system.
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//
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// Revision 1.6  2007/11/13 23:37:28  sybreon
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// Updated simulation to also check BRI 0x00 instruction.
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//
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// Revision 1.5  2007/11/09 20:51:53  sybreon
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// Added GET/PUT support through a FSL bus.
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//
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// Revision 1.4  2007/11/08 14:18:00  sybreon
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// Parameterised optional components.
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//
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// Revision 1.3  2007/11/05 10:59:31  sybreon
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// Added random seed for simulation.
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//
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// Revision 1.2  2007/11/02 19:16:10  sybreon
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// Added interrupt simulation.
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// Changed "human readable" simulation output.
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//
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// Revision 1.1  2007/11/02 03:25:45  sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module edk32 ();
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`include "random.v"
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   // INITIAL SETUP //////////////////////////////////////////////////////
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   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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   reg       svc;
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   integer   inttime;
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   integer   seed;
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   integer   theend;
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   always #5 sys_clk_i = ~sys_clk_i;
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   initial begin
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      //$dumpfile("dump.vcd");
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      //$dumpvars(1,dut);
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   end
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   initial begin
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      seed = randseed;
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      theend = 0;
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      svc = 0;
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      sys_clk_i = $random(seed);
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      sys_rst_i = 1;
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      sys_int_i = 0;
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      sys_exc_i = 0;
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      #50 sys_rst_i = 0;
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   end
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85 
   initial fork
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      //inttime $display("FSADFASDFSDAF");
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      //#10000 sys_int_i = 1;
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      //#1100 sys_int_i = 0;
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      //#100000 $displayh("\nTest Completed.");
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      //#4000 $finish;
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   join
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93 
 
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   // FAKE MEMORY ////////////////////////////////////////////////////////
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   wire        fsl_stb_o;
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   wire        fsl_wre_o;
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   wire [31:0] fsl_dat_o;
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   wire [31:0] fsl_dat_i;
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   wire [6:2]  fsl_adr_o;
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   wire [15:2] iwb_adr_o;
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   wire        iwb_stb_o;
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   wire        dwb_stb_o;
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   reg [31:0]  rom [0:65535];
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   wire [31:0] iwb_dat_i;
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   reg         iwb_ack_i, dwb_ack_i, fsl_ack_i;
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   reg [31:0]  ram[0:65535];
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   wire [31:0] dwb_dat_i;
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   reg [31:0]  dwblat;
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   wire        dwb_we_o;
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   reg [15:2]  dadr,iadr;
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   wire [3:0]  dwb_sel_o;
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   wire [31:0] dwb_dat_o;
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   wire [15:2] dwb_adr_o;
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   wire [31:0] dwb_dat_t;
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119 
   initial begin
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      dwb_ack_i = 0;
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      iwb_ack_i = 0;
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      fsl_ack_i = 0;
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   end
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125 69 sybreon 
   assign      dwb_dat_t = ram[dwb_adr_o];
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   assign      iwb_dat_i = ram[iadr];
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   assign      dwb_dat_i = ram[dadr];
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   assign      fsl_dat_i = fsl_adr_o;
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`ifdef POSEDGE
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132 59 sybreon 
   always @(posedge sys_clk_i)
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     if (sys_rst_i) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        dwb_ack_i <= 1'h0;
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        fsl_ack_i <= 1'h0;
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        iwb_ack_i <= 1'h0;
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        // End of automatics
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     end else begin
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        iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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        dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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        fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
144 73 sybreon 
     end // else: !if(sys_rst_i)
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146 
   always @(posedge sys_clk_i) begin
147 
      iadr <= #1 iwb_adr_o;
148 
      dadr <= #1 dwb_adr_o;
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150 
      if (dwb_we_o & dwb_stb_o) begin
151 
         case (dwb_sel_o)
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           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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         endcase // case (dwb_sel_o)
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      end // if (dwb_we_o & dwb_stb_o)
161 73 sybreon 
   end // always @ (posedge sys_clk_i)
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`else // !`ifdef POSEDGE
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165 
   always @(negedge sys_clk_i)
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     if (sys_rst_i) begin
167 
        /*AUTORESET*/
168 
        // Beginning of autoreset for uninitialized flops
169 
        dwb_ack_i <= 1'h0;
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        fsl_ack_i <= 1'h0;
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        iwb_ack_i <= 1'h0;
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        // End of automatics
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     end else begin
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        iwb_ack_i <= #1 iwb_stb_o;
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        dwb_ack_i <= #1 dwb_stb_o;
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        fsl_ack_i <= #1 fsl_stb_o;
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     end // else: !if(sys_rst_i)
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   always @(negedge sys_clk_i) begin
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      iadr <= #1 iwb_adr_o;
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      dadr <= #1 dwb_adr_o;
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183 41 sybreon 
      if (dwb_we_o & dwb_stb_o) begin
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         case (dwb_sel_o)
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           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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         endcase // case (dwb_sel_o)
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      end // if (dwb_we_o & dwb_stb_o)
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   end // always @ (negedge sys_clk_i)
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196 
`endif // !`ifdef POSEDGE
197 
 
198 41 sybreon 
 
199 
   integer i;
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   initial begin
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      for (i=0;i<65535;i=i+1) begin
202 
         ram[i] <= $random;
203 43 sybreon 
      end
204 69 sybreon 
      #1 $readmemh("dump.rom",ram);
205 41 sybreon 
   end
206 
 
207 
   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
208 
 
209 58 sybreon 
   integer rnd;
210 
 
211 41 sybreon 
   always @(posedge sys_clk_i) begin
212 43 sybreon 
 
213 
      // Interrupt Monitors
214 
      if (!dut.rMSR_IE) begin
215 
         rnd = $random % 30;
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         inttime = $stime + 1000 + (rnd*rnd * 10);
217 
      end
218 
      if ($stime > inttime) begin
219 
         sys_int_i = 1;
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         svc = 0;
221 
      end
222 
      if (($stime > inttime + 500) && !svc) begin
223 
         $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
224 
         $finish;
225 
      end
226 
      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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      if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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         svc = 1;
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         //$display("\nLATENCY: ", ($stime - inttime)/10);
230 
      end
231 41 sybreon 
 
232 
      // Pass/Fail Monitors
233 
      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
234 
         $display("\n\tFAIL");
235 
         $finish;
236 43 sybreon 
      end
237 58 sybreon 
 
238 41 sybreon 
      if (iwb_dat_i == 32'hb8000000) begin
239 58 sybreon 
         theend = theend + 1;
240 
      end
241 
 
242 
      if (theend == 5) begin
243 41 sybreon 
         $display("\n\t*** PASSED ALL TESTS ***");
244 
         $finish;
245 
      end
246 
   end // always @ (posedge sys_clk_i)
247 
 
248 
   // INTERNAL WIRING ////////////////////////////////////////////////////
249 
 
250 
   aeMB_edk32 #(16,16)
251 
     dut (
252 
          .sys_int_i(sys_int_i),
253 
          .dwb_ack_i(dwb_ack_i),
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          .dwb_stb_o(dwb_stb_o),
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          .dwb_adr_o(dwb_adr_o),
256 
          .dwb_dat_o(dwb_dat_o),
257 
          .dwb_dat_i(dwb_dat_i),
258 
          .dwb_wre_o(dwb_we_o),
259 
          .dwb_sel_o(dwb_sel_o),
260 53 sybreon 
 
261 
          .fsl_ack_i(fsl_ack_i),
262 
          .fsl_stb_o(fsl_stb_o),
263 
          .fsl_adr_o(fsl_adr_o),
264 
          .fsl_dat_o(fsl_dat_o),
265 
          .fsl_dat_i(fsl_dat_i),
266 
          .fsl_wre_o(fsl_we_o),
267 
 
268 41 sybreon 
          .iwb_adr_o(iwb_adr_o),
269 
          .iwb_dat_i(iwb_dat_i),
270 
          .iwb_stb_o(iwb_stb_o),
271 
          .iwb_ack_i(iwb_ack_i),
272 
          .sys_clk_i(sys_clk_i),
273 
          .sys_rst_i(sys_rst_i)
274 
          );
275 
 
276 43 sybreon 
endmodule // edk32

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