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/* $Id: edk32.v,v 1.12 2007-12-23 20:40:51 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core TEST
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
`define AEMB_SIMULATION_KERNEL
 
module edk32 ();
 
`include "random.v"
 
   // INITIAL SETUP //////////////////////////////////////////////////////
 
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
   reg       svc;
   integer   inttime;
   integer   seed;
   integer   theend;
 
   always #5 sys_clk_i = ~sys_clk_i;
 
   initial begin
      //$dumpfile("dump.vcd");
      //$dumpvars(1,dut);
   end
 
   initial begin
      seed = randseed;
      theend = 0;
      svc = 0;
      sys_clk_i = $random(seed);
      sys_rst_i = 1;
      sys_int_i = 0;
      sys_exc_i = 0;
      #50 sys_rst_i = 0;
   end
 
   initial fork
      //inttime $display("FSADFASDFSDAF");      
      //#10000 sys_int_i = 1;
      //#1100 sys_int_i = 0;
      //#100000 $displayh("\nTest Completed."); 
      //#4000 $finish;
   join
 
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
   wire        fsl_stb_o;
   wire        fsl_wre_o;
   wire [31:0] fsl_dat_o;
   wire [31:0] fsl_dat_i;
   wire [6:2]  fsl_adr_o;
 
   wire [15:2] iwb_adr_o;
   wire        iwb_stb_o;
   wire        dwb_stb_o;
   reg [31:0]  rom [0:65535];
   wire [31:0] iwb_dat_i;
   reg         iwb_ack_i, dwb_ack_i, fsl_ack_i;
 
   reg [31:0]  ram[0:65535];
   wire [31:0] dwb_dat_i;
   reg [31:0]  dwblat;
   wire        dwb_we_o;
   reg [15:2]  dadr,iadr;
   wire [3:0]  dwb_sel_o;
   wire [31:0] dwb_dat_o;
   wire [15:2] dwb_adr_o;
   wire [31:0] dwb_dat_t;
 
   initial begin
      dwb_ack_i = 0;
      iwb_ack_i = 0;
      fsl_ack_i = 0;
   end
 
   assign      dwb_dat_t = ram[dwb_adr_o];
   assign      iwb_dat_i = ram[iadr];
   assign      dwb_dat_i = ram[dadr];
   assign      fsl_dat_i = fsl_adr_o;
 
`ifdef POSEDGE
 
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
        dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
        fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
     end // else: !if(sys_rst_i)
 
   always @(posedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (posedge sys_clk_i)
 
`else // !`ifdef POSEDGE
 
   always @(negedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        fsl_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o;
        dwb_ack_i <= #1 dwb_stb_o;
        fsl_ack_i <= #1 fsl_stb_o;
     end // else: !if(sys_rst_i)
 
   always @(negedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (dwb_we_o & dwb_stb_o) begin
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
         endcase // case (dwb_sel_o)
      end // if (dwb_we_o & dwb_stb_o)
   end // always @ (negedge sys_clk_i)
 
`endif // !`ifdef POSEDGE
 
 
   integer i;
   initial begin
      for (i=0;i<65535;i=i+1) begin
         ram[i] <= $random;
      end
      #1 $readmemh("dump.vmem",ram);
   end
 
   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
 
   integer rnd;
 
   always @(posedge sys_clk_i) begin
 
      // Interrupt Monitors
      if (!dut.cpu.rMSR_IE) begin
         rnd = $random % 30;
         inttime = $stime + 1000 + (rnd*rnd * 10);
      end
      if ($stime > inttime) begin
         sys_int_i = 1;
         svc = 0;
      end
      if (($stime > inttime + 500) && !svc) begin
         $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
         $finish;
      end
      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
      if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin
         svc = 1;
         //$display("\nLATENCY: ", ($stime - inttime)/10);       
      end
 
      // Pass/Fail Monitors
      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
         $display("\n\tFAIL");
         $finish;
      end
 
      if (iwb_dat_i == 32'hb8000000) begin
         theend = theend + 1;
      end
 
      if (theend == 5) begin
         $display("\n\t*** PASSED ALL TESTS ***");
         $finish;
      end
   end // always @ (posedge sys_clk_i)
 
   // INTERNAL WIRING ////////////////////////////////////////////////////
 
   aeMB_sim #(16,16)
     dut (
          .sys_int_i(sys_int_i),
          .dwb_ack_i(dwb_ack_i),
          .dwb_stb_o(dwb_stb_o),
          .dwb_adr_o(dwb_adr_o),
          .dwb_dat_o(dwb_dat_o),
          .dwb_dat_i(dwb_dat_i),
          .dwb_wre_o(dwb_we_o),
          .dwb_sel_o(dwb_sel_o),
 
          .fsl_ack_i(fsl_ack_i),
          .fsl_stb_o(fsl_stb_o),
          .fsl_adr_o(fsl_adr_o),
          .fsl_dat_o(fsl_dat_o),
          .fsl_dat_i(fsl_dat_i),
          .fsl_wre_o(fsl_we_o),
 
          .iwb_adr_o(iwb_adr_o),
          .iwb_dat_i(iwb_dat_i),
          .iwb_stb_o(iwb_stb_o),
          .iwb_ack_i(iwb_ack_i),
          .sys_clk_i(sys_clk_i),
          .sys_rst_i(sys_rst_i)
          );
 
endmodule // edk32
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.11  2007/12/11 00:44:31  sybreon
 Modified for AEMB2
 
 Revision 1.10  2007/11/30 17:08:30  sybreon
 Moved simulation kernel into code.
 
 Revision 1.9  2007/11/20 18:36:00  sybreon
 Removed unnecessary byte acrobatics with VMEM data.
 
 Revision 1.8  2007/11/18 19:41:45  sybreon
 Minor simulation fixes.
 
 Revision 1.7  2007/11/14 22:11:41  sybreon
 Added posedge/negedge bus interface.
 Modified interrupt test system.
 
 Revision 1.6  2007/11/13 23:37:28  sybreon
 Updated simulation to also check BRI 0x00 instruction.
 
 Revision 1.5  2007/11/09 20:51:53  sybreon
 Added GET/PUT support through a FSL bus.
 
 Revision 1.4  2007/11/08 14:18:00  sybreon
 Parameterised optional components.
 
 Revision 1.3  2007/11/05 10:59:31  sybreon
 Added random seed for simulation.
 
 Revision 1.2  2007/11/02 19:16:10  sybreon
 Added interrupt simulation.
 Changed "human readable" simulation output.
 
 Revision 1.1  2007/11/02 03:25:45  sybreon
 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
 Fixed various minor data hazard bugs.
 Code compatible with -O0/1/2/3/s generated code.
 */

Line No.	Rev	Author	Line
1	95	sybreon	`/* $Id: edk32.v,v 1.12 2007-12-23 20:40:51 sybreon Exp $`
2			`**`
3			`** AEMB EDK 3.2 Compatible Core TEST`
4			`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			`** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.`
20			`*/`
21	41	sybreon
22	79	sybreon	`define AEMB_SIMULATION_KERNEL
23
24	41	sybreon	`module edk32 ();`
25	79	sybreon
26	49	sybreon	`include "random.v"
27
28	41	sybreon	`// INITIAL SETUP //////////////////////////////////////////////////////`
29
30			`reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;`
31			`reg svc;`
32			`integer inttime;`
33	49	sybreon	`integer seed;`
34	58	sybreon	`integer theend;`
35	41	sybreon
36			`always #5 sys_clk_i = ~sys_clk_i;`
37
38			`initial begin`
39	69	sybreon	`//$dumpfile("dump.vcd");`
40			`//$dumpvars(1,dut);`
41	41	sybreon	`end`
42
43			`initial begin`
44	58	sybreon	`seed = randseed;`
45			`theend = 0;`
46	41	sybreon	`svc = 0;`
47	49	sybreon	`sys_clk_i = $random(seed);`
48	41	sybreon	`sys_rst_i = 1;`
49			`sys_int_i = 0;`
50			`sys_exc_i = 0;`
51	59	sybreon	`#50 sys_rst_i = 0;`
52	41	sybreon	`end`
53
54			`initial fork`
55			`//inttime $display("FSADFASDFSDAF");`
56	43	sybreon	`//#10000 sys_int_i = 1;`
57	41	sybreon	`//#1100 sys_int_i = 0;`
58			`//#100000 $displayh("\nTest Completed.");`
59			`//#4000 $finish;`
60			`join`
61
62
63			`// FAKE MEMORY ////////////////////////////////////////////////////////`
64	53	sybreon
65			`wire fsl_stb_o;`
66			`wire fsl_wre_o;`
67			`wire [31:0] fsl_dat_o;`
68			`wire [31:0] fsl_dat_i;`
69	67	sybreon	`wire [6:2] fsl_adr_o;`
70	41	sybreon
71			`wire [15:2] iwb_adr_o;`
72			`wire iwb_stb_o;`
73			`wire dwb_stb_o;`
74			`reg [31:0] rom [0:65535];`
75			`wire [31:0] iwb_dat_i;`
76	53	sybreon	`reg iwb_ack_i, dwb_ack_i, fsl_ack_i;`
77	41	sybreon
78			`reg [31:0] ram[0:65535];`
79			`wire [31:0] dwb_dat_i;`
80			`reg [31:0] dwblat;`
81			`wire dwb_we_o;`
82			`reg [15:2] dadr,iadr;`
83			`wire [3:0] dwb_sel_o;`
84			`wire [31:0] dwb_dat_o;`
85			`wire [15:2] dwb_adr_o;`
86	59	sybreon	`wire [31:0] dwb_dat_t;`
87
88			`initial begin`
89			`dwb_ack_i = 0;`
90			`iwb_ack_i = 0;`
91			`fsl_ack_i = 0;`
92			`end`
93	41	sybreon
94	69	sybreon	`assign dwb_dat_t = ram[dwb_adr_o];`
95			`assign iwb_dat_i = ram[iadr];`
96			`assign dwb_dat_i = ram[dadr];`
97	53	sybreon	`assign fsl_dat_i = fsl_adr_o;`
98	59	sybreon
99			`ifdef POSEDGE
100	41	sybreon
101	59	sybreon	`always @(posedge sys_clk_i)`
102			`if (sys_rst_i) begin`
103			`/AUTORESET/`
104			`// Beginning of autoreset for uninitialized flops`
105			`dwb_ack_i <= 1'h0;`
106			`fsl_ack_i <= 1'h0;`
107			`iwb_ack_i <= 1'h0;`
108			`// End of automatics`
109			`end else begin`
110			`iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;`
111			`dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;`
112			`fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;`
113	73	sybreon	`end // else: !if(sys_rst_i)`
114	59	sybreon
115			`always @(posedge sys_clk_i) begin`
116			`iadr <= #1 iwb_adr_o;`
117			`dadr <= #1 dwb_adr_o;`
118
119			`if (dwb_we_o & dwb_stb_o) begin`
120			`case (dwb_sel_o)`
121	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
122			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
123			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
124			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
125			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
126			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
127			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
128	59	sybreon	`endcase // case (dwb_sel_o)`
129			`end // if (dwb_we_o & dwb_stb_o)`
130	73	sybreon	`end // always @ (posedge sys_clk_i)`
131	59	sybreon
132			`else // !`ifdef POSEDGE
133
134			`always @(negedge sys_clk_i)`
135			`if (sys_rst_i) begin`
136			`/AUTORESET/`
137			`// Beginning of autoreset for uninitialized flops`
138			`dwb_ack_i <= 1'h0;`
139			`fsl_ack_i <= 1'h0;`
140			`iwb_ack_i <= 1'h0;`
141			`// End of automatics`
142			`end else begin`
143			`iwb_ack_i <= #1 iwb_stb_o;`
144			`dwb_ack_i <= #1 dwb_stb_o;`
145			`fsl_ack_i <= #1 fsl_stb_o;`
146	73	sybreon	`end // else: !if(sys_rst_i)`
147	59	sybreon
148	41	sybreon	`always @(negedge sys_clk_i) begin`
149	59	sybreon	`iadr <= #1 iwb_adr_o;`
150			`dadr <= #1 dwb_adr_o;`
151	53	sybreon
152	41	sybreon	`if (dwb_we_o & dwb_stb_o) begin`
153			`case (dwb_sel_o)`
154	69	sybreon	`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
155			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
156			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
157			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
158			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
159			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
160			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
161	43	sybreon	`endcase // case (dwb_sel_o)`
162			`end // if (dwb_we_o & dwb_stb_o)`
163			`end // always @ (negedge sys_clk_i)`
164	59	sybreon
165			`endif // !`ifdef POSEDGE
166
167	41	sybreon
168			`integer i;`
169			`initial begin`
170			`for (i=0;i<65535;i=i+1) begin`
171			`ram[i] <= $random;`
172	43	sybreon	`end`
173	79	sybreon	`#1 $readmemh("dump.vmem",ram);`
174	41	sybreon	`end`
175
176			`// DISPLAY OUTPUTS ///////////////////////////////////////////////////`
177
178	58	sybreon	`integer rnd;`
179
180	41	sybreon	`always @(posedge sys_clk_i) begin`
181	43	sybreon
182			`// Interrupt Monitors`
183	95	sybreon	`if (!dut.cpu.rMSR_IE) begin`
184	43	sybreon	`rnd = $random % 30;`
185			`inttime = $stime + 1000 + (rndrnd 10);`
186			`end`
187			`if ($stime > inttime) begin`
188			`sys_int_i = 1;`
189			`svc = 0;`
190			`end`
191			`if (($stime > inttime + 500) && !svc) begin`
192			`$display("\n\t* INTERRUPT TIMEOUT *", inttime);`
193			`$finish;`
194			`end`
195			`if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;`
196	95	sybreon	`if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin`
197	59	sybreon	`svc = 1;`
198			`//$display("\nLATENCY: ", ($stime - inttime)/10);`
199			`end`
200	41	sybreon
201			`// Pass/Fail Monitors`
202			`if (dwb_we_o & (dwb_dat_o == "FAIL")) begin`
203			`$display("\n\tFAIL");`
204			`$finish;`
205	43	sybreon	`end`
206	58	sybreon
207	41	sybreon	`if (iwb_dat_i == 32'hb8000000) begin`
208	58	sybreon	`theend = theend + 1;`
209			`end`
210
211			`if (theend == 5) begin`
212	41	sybreon	`$display("\n\t* PASSED ALL TESTS *");`
213			`$finish;`
214			`end`
215			`end // always @ (posedge sys_clk_i)`
216
217			`// INTERNAL WIRING ////////////////////////////////////////////////////`
218
219	95	sybreon	`aeMB_sim #(16,16)`
220	41	sybreon	`dut (`
221			`.sys_int_i(sys_int_i),`
222			`.dwb_ack_i(dwb_ack_i),`
223			`.dwb_stb_o(dwb_stb_o),`
224			`.dwb_adr_o(dwb_adr_o),`
225			`.dwb_dat_o(dwb_dat_o),`
226			`.dwb_dat_i(dwb_dat_i),`
227			`.dwb_wre_o(dwb_we_o),`
228			`.dwb_sel_o(dwb_sel_o),`
229	53	sybreon
230			`.fsl_ack_i(fsl_ack_i),`
231			`.fsl_stb_o(fsl_stb_o),`
232			`.fsl_adr_o(fsl_adr_o),`
233			`.fsl_dat_o(fsl_dat_o),`
234			`.fsl_dat_i(fsl_dat_i),`
235			`.fsl_wre_o(fsl_we_o),`
236
237	41	sybreon	`.iwb_adr_o(iwb_adr_o),`
238			`.iwb_dat_i(iwb_dat_i),`
239			`.iwb_stb_o(iwb_stb_o),`
240			`.iwb_ack_i(iwb_ack_i),`
241			`.sys_clk_i(sys_clk_i),`
242			`.sys_rst_i(sys_rst_i)`
243			`);`
244
245	43	sybreon	`endmodule // edk32`
246	95	sybreon
247			`/*`
248			$Log: not supported by cvs2svn $
249			`Revision 1.11 2007/12/11 00:44:31 sybreon`
250			`Modified for AEMB2`
251
252			`Revision 1.10 2007/11/30 17:08:30 sybreon`
253			`Moved simulation kernel into code.`
254
255			`Revision 1.9 2007/11/20 18:36:00 sybreon`
256			`Removed unnecessary byte acrobatics with VMEM data.`
257
258			`Revision 1.8 2007/11/18 19:41:45 sybreon`
259			`Minor simulation fixes.`
260
261			`Revision 1.7 2007/11/14 22:11:41 sybreon`
262			`Added posedge/negedge bus interface.`
263			`Modified interrupt test system.`
264
265			`Revision 1.6 2007/11/13 23:37:28 sybreon`
266			`Updated simulation to also check BRI 0x00 instruction.`
267
268			`Revision 1.5 2007/11/09 20:51:53 sybreon`
269			`Added GET/PUT support through a FSL bus.`
270
271			`Revision 1.4 2007/11/08 14:18:00 sybreon`
272			`Parameterised optional components.`
273
274			`Revision 1.3 2007/11/05 10:59:31 sybreon`
275			`Added random seed for simulation.`
276
277			`Revision 1.2 2007/11/02 19:16:10 sybreon`
278			`Added interrupt simulation.`
279			`Changed "human readable" simulation output.`
280
281			`Revision 1.1 2007/11/02 03:25:45 sybreon`
282			`New EDK 3.2 compatible design with optional barrel-shifter and multiplier.`
283			`Fixed various minor data hazard bugs.`
284			`Code compatible with -O0/1/2/3/s generated code.`
285			`*/`

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