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/*
** AEMB2 EDK 6.3 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
 
/**
 Simulation Test Bench
 @file edk62.v
 
*/
 
`include "random.v"
 
module edk63();
   localparam AEMB_DWB = 18;
   localparam AEMB_XWB = 5;
   localparam AEMB_IWB = 18;
   localparam AEMB_ICH = 11;
   localparam AEMB_IDX = 6;
   localparam AEMB_HTX = 1;
   localparam AEMB_BSF = 1;
   localparam AEMB_MUL = 1;
   localparam AEMB_XSL = 1;
   localparam AEMB_DIV = 0;
   localparam AEMB_FPU = 0;
 
   /*AUTOREGINPUT*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg                  dwb_ack_i;              // To uut of aeMB2_edk63.v
   reg                  iwb_ack_i;              // To uut of aeMB2_edk63.v
   reg                  sys_clk_i;              // To uut of aeMB2_edk63.v
   reg                  sys_ena_i;              // To uut of aeMB2_edk63.v
   reg                  sys_int_i;              // To uut of aeMB2_edk63.v
   reg                  sys_rst_i;              // To uut of aeMB2_edk63.v
   reg                  xwb_ack_i;              // To uut of aeMB2_edk63.v
   // End of automatics
 
   always #5 sys_clk_i <= !sys_clk_i;
 
   initial begin
      `ifdef VCD_DUMP
      $dumpfile ("dump.vcd");
      $dumpvars (1,uut);
      `endif
 
      sys_clk_i = $random(`randseed);
      sys_rst_i = 1;
      sys_ena_i = 1;
      sys_int_i = 1;
 
      xwb_ack_i = 0;
 
      #50 sys_rst_i = 0;
      #4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
 
   end // initial begin
 
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [AEMB_DWB-1:2]  dwb_adr_o;              // From uut of aeMB2_edk63.v
   wire                 dwb_cyc_o;              // From uut of aeMB2_edk63.v
   wire [31:0]           dwb_dat_o;              // From uut of aeMB2_edk63.v
   wire [3:0]            dwb_sel_o;              // From uut of aeMB2_edk63.v
   wire                 dwb_stb_o;              // From uut of aeMB2_edk63.v
   wire                 dwb_tag_o;              // From uut of aeMB2_edk63.v
   wire                 dwb_wre_o;              // From uut of aeMB2_edk63.v
   wire [AEMB_IWB-1:2]  iwb_adr_o;              // From uut of aeMB2_edk63.v
   wire                 iwb_cyc_o;              // From uut of aeMB2_edk63.v
   wire [3:0]            iwb_sel_o;              // From uut of aeMB2_edk63.v
   wire                 iwb_stb_o;              // From uut of aeMB2_edk63.v
   wire                 iwb_tag_o;              // From uut of aeMB2_edk63.v
   wire                 iwb_wre_o;              // From uut of aeMB2_edk63.v
   wire [AEMB_XWB-1:2]  xwb_adr_o;              // From uut of aeMB2_edk63.v
   wire                 xwb_cyc_o;              // From uut of aeMB2_edk63.v
   wire [31:0]           xwb_dat_o;              // From uut of aeMB2_edk63.v
   wire [3:0]            xwb_sel_o;              // From uut of aeMB2_edk63.v
   wire                 xwb_stb_o;              // From uut of aeMB2_edk63.v
   wire                 xwb_tag_o;              // From uut of aeMB2_edk63.v
   wire                 xwb_wre_o;              // From uut of aeMB2_edk63.v
   // End of automatics
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
   reg [31:0]            rom[0:65535];
   reg [31:0]            ram[0:65535];
   reg [31:0]            dwblat;
   reg [31:0]            xwblat;
   reg [31:2]           dadr, iadr;
 
   wire [31:0]           dwb_dat_t = ram[dwb_adr_o];
   wire [31:0]           iwb_dat_i = rom[iadr];
   wire [31:0]           dwb_dat_i = ram[dadr];
   wire [31:0]           xwb_dat_i = xwblat;
 
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        dwb_ack_i <= 1'h0;
        iwb_ack_i <= 1'h0;
        xwb_ack_i <= 1'h0;
        // End of automatics
     end else begin
        iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i;
        dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i;
        xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i;
     end // else: !if(sys_rst_i)
 
   always @(posedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;
      dadr <= #1 dwb_adr_o;
 
      if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin
         xwblat <= #1 xwb_dat_o;
      end
 
      // SPECIAL PORTS
      if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
         case ({dwb_adr_o,2'o0})
           32'hFFFFFFD0: $displayh(dwb_dat_o);
           32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
           32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;
         endcase // case ({dwb_adr_o,2'o0})
 
         case (dwb_sel_o)
           4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
           4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
           4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
           4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
           4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
           4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
           4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
           default: begin
              $displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
              //$finish;              
           end
         endcase // case (dwb_sel_o)
      end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
 
      if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
         case (dwb_sel_o)
           4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
           end
           default: begin
              $displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
              //$finish;              
           end
         endcase // case (dwb_sel_o)     
      end
 
   end // always @ (posedge sys_clk_i)
 
   integer i;
   initial begin
      for (i=0;i<65535;i=i+1) begin
         ram[i] <= $random;
      end
      #1 $readmemh("dump.vmem",rom);
      #1 $readmemh("dump.vmem",ram);
   end
 
   // DUMP CYCLES   
   always @(posedge sys_clk_i)
     if (uut.dena) begin
     //begin
`ifdef AEMB2_SIM_KERNEL
        $displayh("TME=",($stime/10),
                  ",PHA=",uut.gpha,
                  ",IWB=",{uut.rpc_if,2'o0},
                  ",ASM=",uut.ich_dat,
                  ",OPA=",uut.opa_of,
                  ",OPB=",uut.opb_of,
                  ",OPD=",uut.opd_of,
                  ",MSR=",uut.msr_ex,
                  ",MEM=",{uut.mem_ex,2'o0},
                  ",BRA=",uut.bra_ex,
                  ",BPC=",{uut.bpc_ex,2'o0},
                  ",MUX=",uut.mux_ex,
                  ",ALU=",uut.alu_mx,
                  //",WRE=",dwb_wre_o,
                  ",SEL=",dwb_sel_o,
                  //",DWB=",dwb_dat_o,
                  ",REG=",uut.regs0.gprf0.wRW0,
                  //",DAT=",uut.regs0.gprf0.regd,
                  ",MUL=",uut.mul_mx,
                  ",BSF=",uut.bsf_mx,
                  ",DWB=",uut.dwb_mx,
                  ",LNK=",{uut.rpc_mx,2'o0},
                  ",SFR=",uut.sfr_mx,
                  ",E"
                  );
`endif
        if (uut.ich_dat == 32'hB8000000) begin
           $displayh("\n*** EXIT ", $stime, " ***");
           $finish;
        end
     end // if (uut.dena)
 
   aeMB2_edk63
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AEMB_IWB                        (AEMB_IWB),
       .AEMB_DWB                        (AEMB_DWB),
       .AEMB_XWB                        (AEMB_XWB),
       .AEMB_ICH                        (AEMB_ICH),
       .AEMB_IDX                        (AEMB_IDX),
       .AEMB_BSF                        (AEMB_BSF),
       .AEMB_MUL                        (AEMB_MUL),
       .AEMB_DIV                        (AEMB_DIV),
       .AEMB_FPU                        (AEMB_FPU))
   uut
     (/*AUTOINST*/
      // Outputs
      .dwb_adr_o                        (dwb_adr_o[AEMB_DWB-1:2]),
      .dwb_cyc_o                        (dwb_cyc_o),
      .dwb_dat_o                        (dwb_dat_o[31:0]),
      .dwb_sel_o                        (dwb_sel_o[3:0]),
      .dwb_stb_o                        (dwb_stb_o),
      .dwb_tag_o                        (dwb_tag_o),
      .dwb_wre_o                        (dwb_wre_o),
      .iwb_adr_o                        (iwb_adr_o[AEMB_IWB-1:2]),
      .iwb_cyc_o                        (iwb_cyc_o),
      .iwb_sel_o                        (iwb_sel_o[3:0]),
      .iwb_stb_o                        (iwb_stb_o),
      .iwb_tag_o                        (iwb_tag_o),
      .iwb_wre_o                        (iwb_wre_o),
      .xwb_adr_o                        (xwb_adr_o[AEMB_XWB-1:2]),
      .xwb_cyc_o                        (xwb_cyc_o),
      .xwb_dat_o                        (xwb_dat_o[31:0]),
      .xwb_sel_o                        (xwb_sel_o[3:0]),
      .xwb_stb_o                        (xwb_stb_o),
      .xwb_tag_o                        (xwb_tag_o),
      .xwb_wre_o                        (xwb_wre_o),
      // Inputs
      .dwb_ack_i                        (dwb_ack_i),
      .dwb_dat_i                        (dwb_dat_i[31:0]),
      .iwb_ack_i                        (iwb_ack_i),
      .iwb_dat_i                        (iwb_dat_i[31:0]),
      .sys_clk_i                        (sys_clk_i),
      .sys_ena_i                        (sys_ena_i),
      .sys_int_i                        (sys_int_i),
      .sys_rst_i                        (sys_rst_i),
      .xwb_ack_i                        (xwb_ack_i),
      .xwb_dat_i                        (xwb_dat_i[31:0]));
 
endmodule // edk62
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/")
// verilog-library-files:("")
// End:

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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk63.v] - Blame information for rev 206

Line No.	Rev	Author	Line
1	206	sybreon	`/*`
2			`** AEMB2 EDK 6.3 COMPATIBLE CORE`
3			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
4			`**`
5			`** This file is part of AEMB.`
6			`**`
7			`** AEMB is free software: you can redistribute it and/or modify it`
8			`** under the terms of the GNU Lesser General Public License as`
9			`** published by the Free Software Foundation, either version 3 of the`
10			`** License, or (at your option) any later version.`
11			`**`
12			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
13			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
14			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
15			`** Public License for more details.`
16			`**`
17			`** You should have received a copy of the GNU Lesser General Public`
18			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
19			`*/`
20
21			`/**`
22			`Simulation Test Bench`
23			`@file edk62.v`
24
25			`*/`
26
27			`include "random.v"
28
29			`module edk63();`
30			`localparam AEMB_DWB = 18;`
31			`localparam AEMB_XWB = 5;`
32			`localparam AEMB_IWB = 18;`
33			`localparam AEMB_ICH = 11;`
34			`localparam AEMB_IDX = 6;`
35			`localparam AEMB_HTX = 1;`
36			`localparam AEMB_BSF = 1;`
37			`localparam AEMB_MUL = 1;`
38			`localparam AEMB_XSL = 1;`
39			`localparam AEMB_DIV = 0;`
40			`localparam AEMB_FPU = 0;`
41
42			`/AUTOREGINPUT/`
43			`// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)`
44			`reg dwb_ack_i; // To uut of aeMB2_edk63.v`
45			`reg iwb_ack_i; // To uut of aeMB2_edk63.v`
46			`reg sys_clk_i; // To uut of aeMB2_edk63.v`
47			`reg sys_ena_i; // To uut of aeMB2_edk63.v`
48			`reg sys_int_i; // To uut of aeMB2_edk63.v`
49			`reg sys_rst_i; // To uut of aeMB2_edk63.v`
50			`reg xwb_ack_i; // To uut of aeMB2_edk63.v`
51			`// End of automatics`
52
53			`always #5 sys_clk_i <= !sys_clk_i;`
54
55			`initial begin`
56			`ifdef VCD_DUMP
57			`$dumpfile ("dump.vcd");`
58			`$dumpvars (1,uut);`
59			`endif
60
61			sys_clk_i = $random(`randseed);
62			`sys_rst_i = 1;`
63			`sys_ena_i = 1;`
64			`sys_int_i = 1;`
65
66			`xwb_ack_i = 0;`
67
68			`#50 sys_rst_i = 0;`
69			`#4000000 $displayh("\n* TIMEOUT ", $stime, " *"); $finish;`
70
71			`end // initial begin`
72
73			`/AUTOWIRE/`
74			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
75			`wire [AEMB_DWB-1:2] dwb_adr_o; // From uut of aeMB2_edk63.v`
76			`wire dwb_cyc_o; // From uut of aeMB2_edk63.v`
77			`wire [31:0] dwb_dat_o; // From uut of aeMB2_edk63.v`
78			`wire [3:0] dwb_sel_o; // From uut of aeMB2_edk63.v`
79			`wire dwb_stb_o; // From uut of aeMB2_edk63.v`
80			`wire dwb_tag_o; // From uut of aeMB2_edk63.v`
81			`wire dwb_wre_o; // From uut of aeMB2_edk63.v`
82			`wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk63.v`
83			`wire iwb_cyc_o; // From uut of aeMB2_edk63.v`
84			`wire [3:0] iwb_sel_o; // From uut of aeMB2_edk63.v`
85			`wire iwb_stb_o; // From uut of aeMB2_edk63.v`
86			`wire iwb_tag_o; // From uut of aeMB2_edk63.v`
87			`wire iwb_wre_o; // From uut of aeMB2_edk63.v`
88			`wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk63.v`
89			`wire xwb_cyc_o; // From uut of aeMB2_edk63.v`
90			`wire [31:0] xwb_dat_o; // From uut of aeMB2_edk63.v`
91			`wire [3:0] xwb_sel_o; // From uut of aeMB2_edk63.v`
92			`wire xwb_stb_o; // From uut of aeMB2_edk63.v`
93			`wire xwb_tag_o; // From uut of aeMB2_edk63.v`
94			`wire xwb_wre_o; // From uut of aeMB2_edk63.v`
95			`// End of automatics`
96
97			`// FAKE MEMORY ////////////////////////////////////////////////////////`
98
99			`reg [31:0] rom[0:65535];`
100			`reg [31:0] ram[0:65535];`
101			`reg [31:0] dwblat;`
102			`reg [31:0] xwblat;`
103			`reg [31:2] dadr, iadr;`
104
105			`wire [31:0] dwb_dat_t = ram[dwb_adr_o];`
106			`wire [31:0] iwb_dat_i = rom[iadr];`
107			`wire [31:0] dwb_dat_i = ram[dadr];`
108			`wire [31:0] xwb_dat_i = xwblat;`
109
110			`always @(posedge sys_clk_i)`
111			`if (sys_rst_i) begin`
112			`/AUTORESET/`
113			`// Beginning of autoreset for uninitialized flops`
114			`dwb_ack_i <= 1'h0;`
115			`iwb_ack_i <= 1'h0;`
116			`xwb_ack_i <= 1'h0;`
117			`// End of automatics`
118			`end else begin`
119			`iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i;`
120			`dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i;`
121			`xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i;`
122			`end // else: !if(sys_rst_i)`
123
124			`always @(posedge sys_clk_i) begin`
125			`iadr <= #1 iwb_adr_o;`
126			`dadr <= #1 dwb_adr_o;`
127
128			`if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin`
129			`xwblat <= #1 xwb_dat_o;`
130			`end`
131
132			`// SPECIAL PORTS`
133			`if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin`
134			`case ({dwb_adr_o,2'o0})`
135			`32'hFFFFFFD0: $displayh(dwb_dat_o);`
136			`32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);`
137			`32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;`
138			`endcase // case ({dwb_adr_o,2'o0})`
139
140			`case (dwb_sel_o)`
141			`4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};`
142			`4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};`
143			`4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};`
144			`4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};`
145			`4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};`
146			`4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};`
147			`4'hF: ram[dwb_adr_o] <= {dwb_dat_o};`
148			`default: begin`
149			`$displayh("\n* INVALID WRITE ",{dwb_adr_o,2'o0}, " *");`
150			`//$finish;`
151			`end`
152			`endcase // case (dwb_sel_o)`
153			`end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)`
154
155			`if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin`
156			`case (dwb_sel_o)`
157			`4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin`
158			`end`
159			`default: begin`
160			`$displayh("\n* INVALID READ ",{dwb_adr_o,2'd0}, " *");`
161			`//$finish;`
162			`end`
163			`endcase // case (dwb_sel_o)`
164			`end`
165
166			`end // always @ (posedge sys_clk_i)`
167
168			`integer i;`
169			`initial begin`
170			`for (i=0;i<65535;i=i+1) begin`
171			`ram[i] <= $random;`
172			`end`
173			`#1 $readmemh("dump.vmem",rom);`
174			`#1 $readmemh("dump.vmem",ram);`
175			`end`
176
177			`// DUMP CYCLES`
178			`always @(posedge sys_clk_i)`
179			`if (uut.dena) begin`
180			`//begin`
181			`ifdef AEMB2_SIM_KERNEL
182			`$displayh("TME=",($stime/10),`
183			`",PHA=",uut.gpha,`
184			`",IWB=",{uut.rpc_if,2'o0},`
185			`",ASM=",uut.ich_dat,`
186			`",OPA=",uut.opa_of,`
187			`",OPB=",uut.opb_of,`
188			`",OPD=",uut.opd_of,`
189			`",MSR=",uut.msr_ex,`
190			`",MEM=",{uut.mem_ex,2'o0},`
191			`",BRA=",uut.bra_ex,`
192			`",BPC=",{uut.bpc_ex,2'o0},`
193			`",MUX=",uut.mux_ex,`
194			`",ALU=",uut.alu_mx,`
195			`//",WRE=",dwb_wre_o,`
196			`",SEL=",dwb_sel_o,`
197			`//",DWB=",dwb_dat_o,`
198			`",REG=",uut.regs0.gprf0.wRW0,`
199			`//",DAT=",uut.regs0.gprf0.regd,`
200			`",MUL=",uut.mul_mx,`
201			`",BSF=",uut.bsf_mx,`
202			`",DWB=",uut.dwb_mx,`
203			`",LNK=",{uut.rpc_mx,2'o0},`
204			`",SFR=",uut.sfr_mx,`
205			`",E"`
206			`);`
207			`endif
208			`if (uut.ich_dat == 32'hB8000000) begin`
209			`$displayh("\n* EXIT ", $stime, " *");`
210			`$finish;`
211			`end`
212			`end // if (uut.dena)`
213
214			`aeMB2_edk63`
215			`#(/AUTOINSTPARAM/`
216			`// Parameters`
217			`.AEMB_IWB (AEMB_IWB),`
218			`.AEMB_DWB (AEMB_DWB),`
219			`.AEMB_XWB (AEMB_XWB),`
220			`.AEMB_ICH (AEMB_ICH),`
221			`.AEMB_IDX (AEMB_IDX),`
222			`.AEMB_BSF (AEMB_BSF),`
223			`.AEMB_MUL (AEMB_MUL),`
224			`.AEMB_DIV (AEMB_DIV),`
225			`.AEMB_FPU (AEMB_FPU))`
226			`uut`
227			`(/AUTOINST/`
228			`// Outputs`
229			`.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),`
230			`.dwb_cyc_o (dwb_cyc_o),`
231			`.dwb_dat_o (dwb_dat_o[31:0]),`
232			`.dwb_sel_o (dwb_sel_o[3:0]),`
233			`.dwb_stb_o (dwb_stb_o),`
234			`.dwb_tag_o (dwb_tag_o),`
235			`.dwb_wre_o (dwb_wre_o),`
236			`.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),`
237			`.iwb_cyc_o (iwb_cyc_o),`
238			`.iwb_sel_o (iwb_sel_o[3:0]),`
239			`.iwb_stb_o (iwb_stb_o),`
240			`.iwb_tag_o (iwb_tag_o),`
241			`.iwb_wre_o (iwb_wre_o),`
242			`.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),`
243			`.xwb_cyc_o (xwb_cyc_o),`
244			`.xwb_dat_o (xwb_dat_o[31:0]),`
245			`.xwb_sel_o (xwb_sel_o[3:0]),`
246			`.xwb_stb_o (xwb_stb_o),`
247			`.xwb_tag_o (xwb_tag_o),`
248			`.xwb_wre_o (xwb_wre_o),`
249			`// Inputs`
250			`.dwb_ack_i (dwb_ack_i),`
251			`.dwb_dat_i (dwb_dat_i[31:0]),`
252			`.iwb_ack_i (iwb_ack_i),`
253			`.iwb_dat_i (iwb_dat_i[31:0]),`
254			`.sys_clk_i (sys_clk_i),`
255			`.sys_ena_i (sys_ena_i),`
256			`.sys_int_i (sys_int_i),`
257			`.sys_rst_i (sys_rst_i),`
258			`.xwb_ack_i (xwb_ack_i),`
259			`.xwb_dat_i (xwb_dat_i[31:0]));`
260
261			`endmodule // edk62`
262
263			`// Local Variables:`
264			`// verilog-library-directories:("." "../../rtl/verilog/")`
265			`// verilog-library-files:("")`
266			`// End:`