OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sw/] [gccrom] - Blame information for rev 79

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sybreon
#!/bin/sh
2 79 sybreon
# $Id: gccrom,v 1.12 2007-12-11 00:44:32 sybreon Exp $
3 2 sybreon
# $Log: not supported by cvs2svn $
4 79 sybreon
# Revision 1.11  2007/11/30 17:09:27  sybreon
5
# Minor code cleanup.
6
#
7 74 sybreon
# Revision 1.10  2007/11/20 18:35:34  sybreon
8
# Generate VMEM instead of HEX dumps of programme.
9
#
10 68 sybreon
# Revision 1.9  2007/11/18 19:41:46  sybreon
11
# Minor simulation fixes.
12
#
13 67 sybreon
# Revision 1.8  2007/11/09 20:52:37  sybreon
14
# Added some compilation optimisations.
15
#
16 54 sybreon
# Revision 1.7  2007/11/04 05:16:25  sybreon
17
# Added -msoft-float and -mxl-soft-div compiler flags.
18
#
19 47 sybreon
# Revision 1.6  2007/11/02 03:25:46  sybreon
20
# New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
21
# Fixed various minor data hazard bugs.
22
# Code compatible with -O0/1/2/3/s generated code.
23
#
24 41 sybreon
# Revision 1.5  2007/10/22 19:14:38  sybreon
25
# Recommended to compile code with -O2/3/s
26
#
27 40 sybreon
# Revision 1.4  2007/04/30 15:57:31  sybreon
28
# Modified compilation sequence.
29
#
30 32 sybreon
# Revision 1.3  2007/04/25 22:15:06  sybreon
31
# Added support for 8-bit and 16-bit data types.
32
#
33 22 sybreon
# Revision 1.2  2007/04/04 06:14:39  sybreon
34
# Minor changes
35
#
36 12 sybreon
# Revision 1.1  2007/03/09 17:41:56  sybreon
37
# initial import
38
#
39 68 sybreon
 
40
# Compile using C++ pre-processor
41 79 sybreon
mb-g++ -g  -Wl,-defsym -Wl,_STACK_SIZE=0x400 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -o rom.elf $@ && \
42 68 sybreon
 
43
# Create a text listing of the compiled code
44
mb-objdump -dSC rom.elf > rom.dump && \
45
 
46
# Convert the ELF file to an SREC file
47
mb-objcopy -O srec rom.elf rom.srec && \
48
 
49
# Generate a Verilog VMEM file from the SREC file
50 79 sybreon
srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \
51 68 sybreon
 
52
# Cleanup code
53
rm rom.srec && \
54
 
55
# Say Cheeze!
56 12 sybreon
echo "ROM generated"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.