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[/] [aemb/] [trunk/] [sw/] [iss/] [cpu/] [FetchUnit.hh] - Blame information for rev 199

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/*!
  AEMB INSTRUCTION SET SIMULATOR
  Copyright (C) 2009 Shawn Tan 
 
  This program is free software: you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation, either version 3 of the License, or
  (at your option) any later version.
 
  This program is distributed in the hope that it will be useful, but
  WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  General Public License for more details.
 
  You should have received a copy of the GNU General Public License
  along with this program.  If not, see
  .
*/
 
#ifndef AEMBINSTRUCTION_H_
#define AEMBINSTRUCTION_H_
 
using namespace std;
 
namespace aemb
{
 
        typedef enum
        {
                OPC_ADD = 000,
                OPC_RSUB = 001,
                OPC_ADDC = 002,
                OPC_RSUBC = 003,
                OPC_ADDK = 004,
                OPC_RSUBK = 005,
                OPC_ADDKC = 006,
                OPC_RSUBKC = 007,
 
                OPC_CMP = 005,
                OPC_CMPU = 005,
 
                OPC_ADDI = 010,
                OPC_RSUBI = 011,
                OPC_ADDIC = 012,
                OPC_RSUBIC = 013,
                OPC_ADDIK = 014,
                OPC_RSUBIK = 015,
                OPC_ADDIKC = 016,
                OPC_RSUBIKC = 017,
 
                OPC_MUL = 020,
                OPC_BSRL = 021,
                OPC_BSRA = 021,
                OPC_BSLL = 021,
                OPC_MULI = 030,
                OPC_BSRLI = 031,
                OPC_BSRAI = 031,
                OPC_BSLLI = 031,
 
                OPC_IDIV = 032,
                OPC_IDIVU = 032,
 
                OPC_OR = 040,
                OPC_AND = 041,
                OPC_XOR = 042,
                OPC_ANDN = 043,
 
 
        } opcodes;
 
/**
 * FetchUnit formats.
 */
union uInstFormat
{
        int word;
 
        /**
         * R-format opcode
         */
        struct sFormatR
        {
                int im:11; // reserved
                unsigned int rb:5; // rb
                unsigned int ra:5; // ra
                unsigned int rd:5; // rd
                unsigned int op:6; // opcode
        } r;
 
        /**
         * I-format opcode
         */
        struct sFormatI
        {
                int im:16; // immediate
                unsigned int ra:5; // ra
                unsigned int rd:5; // rd
                unsigned int op:6; // opcode
        } i;
};
 
typedef uInstFormat InstFormat;
 
class FetchUnit
{
        int r_pc;
 
public:
 
        void reset();
 
        /**
         * Tokenise instructions.
         * Decode the raw instructions into the opcode structure.
         * @param opc Opcode raw value
         * @return structure holding the opcode
         */
 
        InstFormat tokInst(const int opc);
 
        /**
         * Get PC
         */
        int getPC();
 
        /**
         * Set PC
         */
        void setPC(const int pc);
 
        FetchUnit();
        virtual ~FetchUnit();
};
 
}
#endif /*InstRUCTION_H_*/

Line No.	Rev	Author	Line
1	199	sybreon	`/*!`
2			`AEMB INSTRUCTION SET SIMULATOR`
3			`Copyright (C) 2009 Shawn Tan`
4
5			`This program is free software: you can redistribute it and/or modify`
6			`it under the terms of the GNU General Public License as published by`
7			`the Free Software Foundation, either version 3 of the License, or`
8			`(at your option) any later version.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program. If not, see`
17			`.`
18			`*/`
19
20			`#ifndef AEMBINSTRUCTION_H_`
21			`#define AEMBINSTRUCTION_H_`
22
23			`using namespace std;`
24
25			`namespace aemb`
26			`{`
27
28			`typedef enum`
29			`{`
30			`OPC_ADD = 000,`
31			`OPC_RSUB = 001,`
32			`OPC_ADDC = 002,`
33			`OPC_RSUBC = 003,`
34			`OPC_ADDK = 004,`
35			`OPC_RSUBK = 005,`
36			`OPC_ADDKC = 006,`
37			`OPC_RSUBKC = 007,`
38
39			`OPC_CMP = 005,`
40			`OPC_CMPU = 005,`
41
42			`OPC_ADDI = 010,`
43			`OPC_RSUBI = 011,`
44			`OPC_ADDIC = 012,`
45			`OPC_RSUBIC = 013,`
46			`OPC_ADDIK = 014,`
47			`OPC_RSUBIK = 015,`
48			`OPC_ADDIKC = 016,`
49			`OPC_RSUBIKC = 017,`
50
51			`OPC_MUL = 020,`
52			`OPC_BSRL = 021,`
53			`OPC_BSRA = 021,`
54			`OPC_BSLL = 021,`
55			`OPC_MULI = 030,`
56			`OPC_BSRLI = 031,`
57			`OPC_BSRAI = 031,`
58			`OPC_BSLLI = 031,`
59
60			`OPC_IDIV = 032,`
61			`OPC_IDIVU = 032,`
62
63			`OPC_OR = 040,`
64			`OPC_AND = 041,`
65			`OPC_XOR = 042,`
66			`OPC_ANDN = 043,`
67
68
69			`} opcodes;`
70
71			`/**`
72			`* FetchUnit formats.`
73			`*/`
74			`union uInstFormat`
75			`{`
76			`int word;`
77
78			`/**`
79			`* R-format opcode`
80			`*/`
81			`struct sFormatR`
82			`{`
83			`int im:11; // reserved`
84			`unsigned int rb:5; // rb`
85			`unsigned int ra:5; // ra`
86			`unsigned int rd:5; // rd`
87			`unsigned int op:6; // opcode`
88			`} r;`
89
90			`/**`
91			`* I-format opcode`
92			`*/`
93			`struct sFormatI`
94			`{`
95			`int im:16; // immediate`
96			`unsigned int ra:5; // ra`
97			`unsigned int rd:5; // rd`
98			`unsigned int op:6; // opcode`
99			`} i;`
100			`};`
101
102			`typedef uInstFormat InstFormat;`
103
104			`class FetchUnit`
105			`{`
106			`int r_pc;`
107
108			`public:`
109
110			`void reset();`
111
112			`/**`
113			`* Tokenise instructions.`
114			`* Decode the raw instructions into the opcode structure.`
115			`* @param opc Opcode raw value`
116			`* @return structure holding the opcode`
117			`*/`
118
119			`InstFormat tokInst(const int opc);`
120
121			`/**`
122			`* Get PC`
123			`*/`
124			`int getPC();`
125
126			`/**`
127			`* Set PC`
128			`*/`
129			`void setPC(const int pc);`
130
131			`FetchUnit();`
132			`virtual ~FetchUnit();`
133			`};`
134
135			`}`
136			`#endif /InstRUCTION_H_/`

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[/] [aemb/] [trunk/] [sw/] [iss/] [cpu/] [FetchUnit.hh] - Blame information for rev 199