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[/] [aemb/] [trunk/] [sw/] [iss/] [cpu/] [FetchUnit.hh] - Blame information for rev 200

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/*!
  AEMB INSTRUCTION SET SIMULATOR
  Copyright (C) 2009 Shawn Tan 
 
  This program is free software: you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation, either version 3 of the License, or
  (at your option) any later version.
 
  This program is distributed in the hope that it will be useful, but
  WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  General Public License for more details.
 
  You should have received a copy of the GNU General Public License
  along with this program.  If not, see
  .
*/
 
#ifndef AEMBINSTRUCTION_H_
#define AEMBINSTRUCTION_H_
 
using namespace std;
 
namespace aemb
{
        typedef enum
        {
                OPC_ADD = 000,
                OPC_RSUB = 001,
                OPC_ADDC = 002,
                OPC_RSUBC = 003,
                OPC_ADDK = 004,
                OPC_RSUBK = 005,
                OPC_ADDKC = 006,
                OPC_RSUBKC = 007,
 
                OPC_CMP = 005,
                OPC_CMPU = 005,
 
                OPC_ADDI = 010,
                OPC_RSUBI = 011,
                OPC_ADDIC = 012,
                OPC_RSUBIC = 013,
                OPC_ADDIK = 014,
                OPC_RSUBIK = 015,
                OPC_ADDIKC = 016,
                OPC_RSUBIKC = 017,
 
                OPC_MUL = 020,
                OPC_BSRL = 021,
                OPC_BSRA = 021,
                OPC_BSLL = 021,
                OPC_MULI = 030,
                OPC_BSRLI = 031,
                OPC_BSRAI = 031,
                OPC_BSLLI = 031,
 
                OPC_IDIV = 032,
                OPC_IDIVU = 032,
 
                OPC_OR = 040,
                OPC_AND = 041,
                OPC_XOR = 042,
                OPC_ANDN = 043,
 
 
        } opcodes;
 
/**
 * FetchUnit formats.
 */
union uInstFormat
{
        int word;
 
        /**
         * R-format opcode
         */
        struct sFormatR
        {
                int im:11; // reserved
                unsigned int rb:5; // rb
                unsigned int ra:5; // ra
                unsigned int rd:5; // rd
                unsigned int op:6; // opcode
        } r;
 
        /**
         * I-format opcode
         */
        struct sFormatI
        {
                int im:16; // immediate
                unsigned int ra:5; // ra
                unsigned int rd:5; // rd
                unsigned int op:6; // opcode
        } i;
};
 
typedef uInstFormat InstFormat;
 
class FetchUnit
{
        int r_pc;
 
public:
 
        void reset();
 
        /**
         * Tokenise instructions.
         * Decode the raw instructions into the opcode structure.
         * @param opc Opcode raw value
         * @return structure holding the opcode
         */
 
        InstFormat tokInst(const int opc);
 
        /**
         * Get PC
         */
        int getPC();
 
        /**
         * Set PC
         */
        void setPC(const int pc);
 
        FetchUnit();
        virtual ~FetchUnit();
};
 
}
#endif /*InstRUCTION_H_*/

Line No.	Rev	Author	Line
1	199	sybreon	`/*!`
2			`AEMB INSTRUCTION SET SIMULATOR`
3			`Copyright (C) 2009 Shawn Tan`
4
5			`This program is free software: you can redistribute it and/or modify`
6			`it under the terms of the GNU General Public License as published by`
7			`the Free Software Foundation, either version 3 of the License, or`
8			`(at your option) any later version.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program. If not, see`
17			`.`
18			`*/`
19
20			`#ifndef AEMBINSTRUCTION_H_`
21			`#define AEMBINSTRUCTION_H_`
22
23			`using namespace std;`
24
25			`namespace aemb`
26			`{`
27			`typedef enum`
28			`{`
29			`OPC_ADD = 000,`
30			`OPC_RSUB = 001,`
31			`OPC_ADDC = 002,`
32			`OPC_RSUBC = 003,`
33			`OPC_ADDK = 004,`
34			`OPC_RSUBK = 005,`
35			`OPC_ADDKC = 006,`
36			`OPC_RSUBKC = 007,`
37
38			`OPC_CMP = 005,`
39			`OPC_CMPU = 005,`
40
41			`OPC_ADDI = 010,`
42			`OPC_RSUBI = 011,`
43			`OPC_ADDIC = 012,`
44			`OPC_RSUBIC = 013,`
45			`OPC_ADDIK = 014,`
46			`OPC_RSUBIK = 015,`
47			`OPC_ADDIKC = 016,`
48			`OPC_RSUBIKC = 017,`
49
50			`OPC_MUL = 020,`
51			`OPC_BSRL = 021,`
52			`OPC_BSRA = 021,`
53			`OPC_BSLL = 021,`
54			`OPC_MULI = 030,`
55			`OPC_BSRLI = 031,`
56			`OPC_BSRAI = 031,`
57			`OPC_BSLLI = 031,`
58
59			`OPC_IDIV = 032,`
60			`OPC_IDIVU = 032,`
61
62			`OPC_OR = 040,`
63			`OPC_AND = 041,`
64			`OPC_XOR = 042,`
65			`OPC_ANDN = 043,`
66
67
68			`} opcodes;`
69
70			`/**`
71			`* FetchUnit formats.`
72			`*/`
73			`union uInstFormat`
74			`{`
75			`int word;`
76
77			`/**`
78			`* R-format opcode`
79			`*/`
80			`struct sFormatR`
81			`{`
82			`int im:11; // reserved`
83			`unsigned int rb:5; // rb`
84			`unsigned int ra:5; // ra`
85			`unsigned int rd:5; // rd`
86			`unsigned int op:6; // opcode`
87			`} r;`
88
89			`/**`
90			`* I-format opcode`
91			`*/`
92			`struct sFormatI`
93			`{`
94			`int im:16; // immediate`
95			`unsigned int ra:5; // ra`
96			`unsigned int rd:5; // rd`
97			`unsigned int op:6; // opcode`
98			`} i;`
99			`};`
100
101			`typedef uInstFormat InstFormat;`
102
103			`class FetchUnit`
104			`{`
105			`int r_pc;`
106
107			`public:`
108
109			`void reset();`
110
111			`/**`
112			`* Tokenise instructions.`
113			`* Decode the raw instructions into the opcode structure.`
114			`* @param opc Opcode raw value`
115			`* @return structure holding the opcode`
116			`*/`
117
118			`InstFormat tokInst(const int opc);`
119
120			`/**`
121			`* Get PC`
122			`*/`
123			`int getPC();`
124
125			`/**`
126			`* Set PC`
127			`*/`
128			`void setPC(const int pc);`
129
130			`FetchUnit();`
131			`virtual ~FetchUnit();`
132			`};`
133
134			`}`
135			`#endif /InstRUCTION_H_/`

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[/] [aemb/] [trunk/] [sw/] [iss/] [cpu/] [FetchUnit.hh] - Blame information for rev 200